gwj / at91sam9263 · Commits

Commit 2662a059aa2affddfbe42e78b11c802cf30a970f

Authored by j_mayer
1 parent a4bb6c3e

More PowerPC definitions, from POWER 2.04 specifications and misc sources. 

Check that at least instructions set and SPRs are correct for
 PowerPC 401, 403, 405 and 440 cores.
Implement PowerPC 401 MMU model (real-mode only).
Improve INSNs and SPRs dump to ease parse with standard shell tools.
Add more precise status for most PowerPC cores families.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3201 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 1136 additions and 372 deletions
target-ppc/STATUS
  View file @2662a05
@@ -4,6 +4,216 @@ The goal of this file is to provide a reference status to avoid regressions. @@ -4,6 +4,216 @@ The goal of this file is to provide a reference status to avoid regressions.
4 =============================================================================== 4 ===============================================================================
5 PowerPC core emulation status 5 PowerPC core emulation status
6 6
  7 +32 bits PowerPC
  8 +PowerPC 601:
  9 +INSN
  10 +SPR
  11 +MMU
  12 +EXCP
  13 +
  14 +PowerPC 602:
  15 +INSN
  16 +SPR
  17 +MMU
  18 +EXCP
  19 +
  20 +PowerPC 603:
  21 +INSN OK
  22 +SPR OK
  23 +MMU OK
  24 +EXCP OK
  25 +
  26 +PowerPC 604:
  27 +INSN OK
  28 +SPR OK
  29 +MMU OK
  30 +EXCP OK
  31 +
  32 +PowerPC 740:
  33 +INSN OK
  34 +SPR OK
  35 +MMU OK
  36 +EXCP OK
  37 +
  38 +PowerPC 745:
  39 +INSN
  40 +SPR
  41 +MMU
  42 +EXCP
  43 +
  44 +PowerPC 750:
  45 +INSN OK
  46 +SPR OK
  47 +MMU OK
  48 +EXCP OK
  49 +
  50 +PowerPC 755:
  51 +INSN
  52 +SPR
  53 +MMU
  54 +EXCP
  55 +
  56 +PowerPC 7400:
  57 +INSN KO
  58 +SPR KO
  59 +MMU OK
  60 +EXCP OK
  61 +
  62 +PowerPC 7410:
  63 +INSN KO
  64 +SPR KO
  65 +MMU OK
  66 +EXCP OK
  67 +
  68 +PowerPC 7450:
  69 +INSN KO
  70 +SPR KO
  71 +MMU OK
  72 +EXCP OK
  73 +
  74 +PowerPC 7455:
  75 +INSN KO
  76 +SPR KO
  77 +MMU OK
  78 +EXCP OK
  79 +
  80 +PowerPC 7457:
  81 +INSN KO
  82 +SPR KO
  83 +MMU OK
  84 +EXCP OK
  85 +
  86 +PowerPC 7457A:
  87 +INSN KO
  88 +SPR KO
  89 +MMU OK
  90 +EXCP OK
  91 +
  92 +64 bits PowerPC
  93 +PowerPC 970:
  94 +INSN KO
  95 +SPR KO
  96 +MMU KO
  97 +EXCP KO
  98 +
  99 +PowerPC 620: (lack of precise informations)
  100 +INSN KO
  101 +SPR KO
  102 +MMU KO
  103 +EXCP KO
  104 +
  105 +PowerPC 630: (lack of precise informations)
  106 +INSN KO
  107 +SPR KO
  108 +MMU KO
  109 +EXCP KO
  110 +
  111 +PowerPC 631: (lack of precise informations)
  112 +INSN KO
  113 +SPR KO
  114 +MMU KO
  115 +EXCP KO
  116 +
  117 +POWER4: (lack of precise informations)
  118 +INSN KO
  119 +SPR KO
  120 +MMU KO
  121 +EXCP KO
  122 +
  123 +POWER4+: (lack of precise informations)
  124 +INSN KO
  125 +SPR KO
  126 +MMU KO
  127 +EXCP KO
  128 +
  129 +POWER5: (lack of precise informations)
  130 +INSN KO
  131 +SPR KO
  132 +MMU KO
  133 +EXCP KO
  134 +
  135 +POWER5+: (lack of precise informations)
  136 +INSN KO
  137 +SPR KO
  138 +MMU KO
  139 +EXCP KO
  140 +
  141 +POWER6: (lack of precise informations)
  142 +INSN KO
  143 +SPR KO
  144 +MMU KO
  145 +EXCP KO
  146 +
  147 +RS64: (lack of precise informations)
  148 +INSN KO
  149 +SPR KO
  150 +MMU KO
  151 +EXCP KO
  152 +
  153 +RS64-II: (lack of precise informations)
  154 +INSN KO
  155 +SPR KO
  156 +MMU KO
  157 +EXCP KO
  158 +
  159 +RS64-III: (lack of precise informations)
  160 +INSN KO
  161 +SPR KO
  162 +MMU KO
  163 +EXCP KO
  164 +
  165 +RS64-IV: (lack of precise informations)
  166 +INSN KO
  167 +SPR KO
  168 +MMU KO
  169 +EXCP KO
  170 +
  171 +Embedded PowerPC cores
  172 +PowerPC 401:
  173 +INSN OK
  174 +SPR OK
  175 +MMU OK
  176 +EXCP ?
  177 +
  178 +PowerPC 403:
  179 +INSN OK
  180 +SPR OK
  181 +MMU OK
  182 +EXCP ?
  183 +
  184 +PowerPC 405:
  185 +INSN OK
  186 +SPR OK
  187 +MMU OK
  188 +EXCP OK
  189 +
  190 +PowerPC 440:
  191 +INSN OK
  192 +SPR OK
  193 +MMU ?
  194 +EXCP ?
  195 +
  196 +PowerPC 460: (lack of precise informations)
  197 +INSN KO
  198 +SPR KO
  199 +MMU KO
  200 +EXCP KO
  201 +
  202 +Freescale (to be completed) ...
  203 +
  204 +Original POWER
  205 +POWER: (lack of precise informations)
  206 +INSN KO
  207 +SPR KO
  208 +MMU KO
  209 +EXCP KO
  210 +
  211 +POWER2: (lack of precise informations)
  212 +INSN KO
  213 +SPR KO
  214 +MMU KO
  215 +EXCP KO
  216 +
7 PowerPC CPU known to work (ie booting at least Linux 2.4): 217 PowerPC CPU known to work (ie booting at least Linux 2.4):
8 * main stream PowerPC cores 218 * main stream PowerPC cores
9 - PowerPC 603 & derivatives 219 - PowerPC 603 & derivatives
target-ppc/cpu.h
  View file @2662a05
@@ -94,11 +94,17 @@ enum { @@ -94,11 +94,17 @@ enum {
94 /* PowerPC 401 cores */ 94 /* PowerPC 401 cores */
95 CPU_PPC_401A1 = 0x00210000, 95 CPU_PPC_401A1 = 0x00210000,
96 CPU_PPC_401B2 = 0x00220000, 96 CPU_PPC_401B2 = 0x00220000,
  97 +#if 0
  98 + CPU_PPC_401B3 = xxx,
  99 +#endif
97 CPU_PPC_401C2 = 0x00230000, 100 CPU_PPC_401C2 = 0x00230000,
98 CPU_PPC_401D2 = 0x00240000, 101 CPU_PPC_401D2 = 0x00240000,
99 CPU_PPC_401E2 = 0x00250000, 102 CPU_PPC_401E2 = 0x00250000,
100 CPU_PPC_401F2 = 0x00260000, 103 CPU_PPC_401F2 = 0x00260000,
101 CPU_PPC_401G2 = 0x00270000, 104 CPU_PPC_401G2 = 0x00270000,
  105 +#if 0
  106 + CPU_PPC_401GF = xxx,
  107 +#endif
102 #define CPU_PPC_401 CPU_PPC_401G2 108 #define CPU_PPC_401 CPU_PPC_401G2
103 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ 109 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
104 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ 110 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
@@ -107,19 +113,39 @@ enum { @@ -107,19 +113,39 @@ enum {
107 CPU_PPC_403GB = 0x00200100, 113 CPU_PPC_403GB = 0x00200100,
108 CPU_PPC_403GC = 0x00200200, 114 CPU_PPC_403GC = 0x00200200,
109 CPU_PPC_403GCX = 0x00201400, 115 CPU_PPC_403GCX = 0x00201400,
  116 +#if 0
  117 + CPU_PPC_403GP = xxx,
  118 +#endif
110 #define CPU_PPC_403 CPU_PPC_403GCX 119 #define CPU_PPC_403 CPU_PPC_403GCX
111 /* PowerPC 405 cores */ 120 /* PowerPC 405 cores */
  121 +#if 0
  122 + CPU_PPC_405A3 = xxx,
  123 +#endif
  124 +#if 0
  125 + CPU_PPC_405A4 = xxx,
  126 +#endif
  127 +#if 0
  128 + CPU_PPC_405B3 = xxx,
  129 +#endif
  130 + CPU_PPC_405D2 = 0x20010000,
  131 + CPU_PPC_405D4 = 0x41810000,
112 CPU_PPC_405CR = 0x40110145, 132 CPU_PPC_405CR = 0x40110145,
113 #define CPU_PPC_405GP CPU_PPC_405CR 133 #define CPU_PPC_405GP CPU_PPC_405CR
114 CPU_PPC_405EP = 0x51210950, 134 CPU_PPC_405EP = 0x51210950,
  135 +#if 0
  136 + CPU_PPC_405EZ = xxx,
  137 +#endif
115 CPU_PPC_405GPR = 0x50910951, 138 CPU_PPC_405GPR = 0x50910951,
116 - CPU_PPC_405D2 = 0x20010000,  
117 - CPU_PPC_405D4 = 0x41810000, 139 +#if 0
  140 + CPU_PPC_405LP = xxx,
  141 +#endif
118 #define CPU_PPC_405 CPU_PPC_405D4 142 #define CPU_PPC_405 CPU_PPC_405D4
119 CPU_PPC_NPE405H = 0x414100C0, 143 CPU_PPC_NPE405H = 0x414100C0,
120 CPU_PPC_NPE405H2 = 0x41410140, 144 CPU_PPC_NPE405H2 = 0x41410140,
121 CPU_PPC_NPE405L = 0x416100C0, 145 CPU_PPC_NPE405L = 0x416100C0,
122 - /* XXX: missing 405LP, LC77700 */ 146 +#if 0
  147 + CPU_PPC_LC77700 = xxx,
  148 +#endif
123 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ 149 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
124 #if 0 150 #if 0
125 CPU_PPC_STB01000 = xxx, 151 CPU_PPC_STB01000 = xxx,
@@ -150,14 +176,22 @@ enum { @@ -150,14 +176,22 @@ enum {
150 CPU_PPC_440EP = 0x422218D3, 176 CPU_PPC_440EP = 0x422218D3,
151 #define CPU_PPC_440GR CPU_PPC_440EP 177 #define CPU_PPC_440GR CPU_PPC_440EP
152 CPU_PPC_440GP = 0x40120481, 178 CPU_PPC_440GP = 0x40120481,
  179 +#if 0
  180 + CPU_PPC_440GRX = xxx,
  181 +#endif
153 CPU_PPC_440GX = 0x51B21850, 182 CPU_PPC_440GX = 0x51B21850,
154 CPU_PPC_440GXc = 0x51B21892, 183 CPU_PPC_440GXc = 0x51B21892,
155 CPU_PPC_440GXf = 0x51B21894, 184 CPU_PPC_440GXf = 0x51B21894,
156 CPU_PPC_440SP = 0x53221850, 185 CPU_PPC_440SP = 0x53221850,
157 CPU_PPC_440SP2 = 0x53221891, 186 CPU_PPC_440SP2 = 0x53221891,
158 CPU_PPC_440SPE = 0x53421890, 187 CPU_PPC_440SPE = 0x53421890,
159 - /* XXX: missing 440GRX */  
160 - /* PowerPC 460 cores - TODO */ 188 + /* PowerPC 460 cores */
  189 +#if 0
  190 + CPU_PPC_464H90 = xxx,
  191 +#endif
  192 +#if 0
  193 + CPU_PPC_464H90FP = xxx,
  194 +#endif
161 /* PowerPC MPC 5xx cores */ 195 /* PowerPC MPC 5xx cores */
162 CPU_PPC_5xx = 0x00020020, 196 CPU_PPC_5xx = 0x00020020,
163 /* PowerPC MPC 8xx cores (aka PowerQUICC) */ 197 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
@@ -197,14 +231,8 @@ enum { @@ -197,14 +231,8 @@ enum {
197 /* PowerPC 74x/75x cores (aka G3) */ 231 /* PowerPC 74x/75x cores (aka G3) */
198 CPU_PPC_74x = 0x00080000, 232 CPU_PPC_74x = 0x00080000,
199 CPU_PPC_740E = 0x00080100, 233 CPU_PPC_740E = 0x00080100,
200 - CPU_PPC_750E = 0x00080200,  
201 - CPU_PPC_755_10 = 0x00083100,  
202 - CPU_PPC_755_11 = 0x00083101,  
203 - CPU_PPC_755_20 = 0x00083200,  
204 - CPU_PPC_755D = 0x00083202,  
205 - CPU_PPC_755E = 0x00083203,  
206 -#define CPU_PPC_755 CPU_PPC_755E  
207 CPU_PPC_74xP = 0x10080000, 234 CPU_PPC_74xP = 0x10080000,
  235 + CPU_PPC_750E = 0x00080200,
208 CPU_PPC_750CXE21 = 0x00082201, 236 CPU_PPC_750CXE21 = 0x00082201,
209 CPU_PPC_750CXE22 = 0x00082212, 237 CPU_PPC_750CXE22 = 0x00082212,
210 CPU_PPC_750CXE23 = 0x00082203, 238 CPU_PPC_750CXE23 = 0x00082203,
@@ -228,12 +256,20 @@ enum { @@ -228,12 +256,20 @@ enum {
228 CPU_PPC_750GL = 0x70020102, 256 CPU_PPC_750GL = 0x70020102,
229 CPU_PPC_750L30 = 0x00088300, 257 CPU_PPC_750L30 = 0x00088300,
230 CPU_PPC_750L32 = 0x00088302, 258 CPU_PPC_750L32 = 0x00088302,
  259 +#define CPU_PPC_750L CPU_PPC_750L32
231 CPU_PPC_750CL = 0x00087200, 260 CPU_PPC_750CL = 0x00087200,
  261 + CPU_PPC_755_10 = 0x00083100,
  262 + CPU_PPC_755_11 = 0x00083101,
  263 + CPU_PPC_755_20 = 0x00083200,
  264 + CPU_PPC_755D = 0x00083202,
  265 + CPU_PPC_755E = 0x00083203,
  266 +#define CPU_PPC_755 CPU_PPC_755E
232 /* PowerPC 74xx cores (aka G4) */ 267 /* PowerPC 74xx cores (aka G4) */
233 CPU_PPC_7400 = 0x000C0100, 268 CPU_PPC_7400 = 0x000C0100,
234 CPU_PPC_7410C = 0x800C1102, 269 CPU_PPC_7410C = 0x800C1102,
235 CPU_PPC_7410D = 0x800C1103, 270 CPU_PPC_7410D = 0x800C1103,
236 CPU_PPC_7410E = 0x800C1104, 271 CPU_PPC_7410E = 0x800C1104,
  272 +#define CPU_PPC_7410 CPU_PPC_7410E
237 CPU_PPC_7441 = 0x80000210, 273 CPU_PPC_7441 = 0x80000210,
238 CPU_PPC_7445 = 0x80010100, 274 CPU_PPC_7445 = 0x80010100,
239 CPU_PPC_7447 = 0x80020100, 275 CPU_PPC_7447 = 0x80020100,
@@ -257,6 +293,9 @@ enum { @@ -257,6 +293,9 @@ enum {
257 CPU_PPC_POWER4P = 0x00380000, 293 CPU_PPC_POWER4P = 0x00380000,
258 CPU_PPC_POWER5 = 0x003A0000, 294 CPU_PPC_POWER5 = 0x003A0000,
259 CPU_PPC_POWER5P = 0x003B0000, 295 CPU_PPC_POWER5P = 0x003B0000,
  296 +#if 0
  297 + CPU_PPC_POWER6 = xxx,
  298 +#endif
260 CPU_PPC_970 = 0x00390000, 299 CPU_PPC_970 = 0x00390000,
261 CPU_PPC_970FX10 = 0x00391100, 300 CPU_PPC_970FX10 = 0x00391100,
262 CPU_PPC_970FX20 = 0x003C0200, 301 CPU_PPC_970FX20 = 0x003C0200,
@@ -399,59 +438,67 @@ enum { @@ -399,59 +438,67 @@ enum {
399 PPC_SPEFPU = 0x0000000200000000ULL, 438 PPC_SPEFPU = 0x0000000200000000ULL,
400 /* SLB management */ 439 /* SLB management */
401 PPC_SLBI = 0x0000000400000000ULL, 440 PPC_SLBI = 0x0000000400000000ULL,
  441 + /* PowerPC 40x ibct instructions */
  442 + PPC_40x_ICBT = 0x0000000800000000ULL,
402 }; 443 };
403 444
404 /* CPU run-time flags (MMU and exception model) */ 445 /* CPU run-time flags (MMU and exception model) */
405 enum { 446 enum {
406 - /* MMU model */ 447 + /* MMU model */
407 PPC_FLAGS_MMU_MASK = 0x000000FF, 448 PPC_FLAGS_MMU_MASK = 0x000000FF,
408 - /* Standard 32 bits PowerPC MMU */ 449 + /* Standard 32 bits PowerPC MMU */
409 PPC_FLAGS_MMU_32B = 0x00000000, 450 PPC_FLAGS_MMU_32B = 0x00000000,
410 - /* Standard 64 bits PowerPC MMU */ 451 + /* Standard 64 bits PowerPC MMU */
411 PPC_FLAGS_MMU_64B = 0x00000001, 452 PPC_FLAGS_MMU_64B = 0x00000001,
412 - /* PowerPC 601 MMU */ 453 + /* PowerPC 601 MMU */
413 PPC_FLAGS_MMU_601 = 0x00000002, 454 PPC_FLAGS_MMU_601 = 0x00000002,
414 /* PowerPC 6xx MMU with software TLB */ 455 /* PowerPC 6xx MMU with software TLB */
415 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003, 456 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
416 /* PowerPC 4xx MMU with software TLB */ 457 /* PowerPC 4xx MMU with software TLB */
417 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004, 458 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
418 - /* PowerPC 403 MMU */ 459 + /* PowerPC 403 MMU */
419 PPC_FLAGS_MMU_403 = 0x00000005, 460 PPC_FLAGS_MMU_403 = 0x00000005,
420 - /* BookE FSL MMU model */ 461 + /* BookE FSL MMU model */
421 PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006, 462 PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
422 - /* BookE MMU model */ 463 + /* BookE MMU model */
423 PPC_FLAGS_MMU_BOOKE = 0x00000007, 464 PPC_FLAGS_MMU_BOOKE = 0x00000007,
424 - /* 64 bits "bridge" PowerPC MMU */ 465 + /* 64 bits "bridge" PowerPC MMU */
425 PPC_FLAGS_MMU_64BRIDGE = 0x00000008, 466 PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
426 - /* Exception model */ 467 + /* PowerPC 401 MMU (real mode only) */
  468 + PPC_FLAGS_MMU_401 = 0x00000009,
  469 + /* Exception model */
427 PPC_FLAGS_EXCP_MASK = 0x0000FF00, 470 PPC_FLAGS_EXCP_MASK = 0x0000FF00,
428 /* Standard PowerPC exception model */ 471 /* Standard PowerPC exception model */
429 PPC_FLAGS_EXCP_STD = 0x00000000, 472 PPC_FLAGS_EXCP_STD = 0x00000000,
430 - /* PowerPC 40x exception model */ 473 + /* PowerPC 40x exception model */
431 PPC_FLAGS_EXCP_40x = 0x00000100, 474 PPC_FLAGS_EXCP_40x = 0x00000100,
432 - /* PowerPC 601 exception model */ 475 + /* PowerPC 601 exception model */
433 PPC_FLAGS_EXCP_601 = 0x00000200, 476 PPC_FLAGS_EXCP_601 = 0x00000200,
434 - /* PowerPC 602 exception model */ 477 + /* PowerPC 602 exception model */
435 PPC_FLAGS_EXCP_602 = 0x00000300, 478 PPC_FLAGS_EXCP_602 = 0x00000300,
436 - /* PowerPC 603 exception model */ 479 + /* PowerPC 603 exception model */
437 PPC_FLAGS_EXCP_603 = 0x00000400, 480 PPC_FLAGS_EXCP_603 = 0x00000400,
438 - /* PowerPC 604 exception model */ 481 + /* PowerPC 604 exception model */
439 PPC_FLAGS_EXCP_604 = 0x00000500, 482 PPC_FLAGS_EXCP_604 = 0x00000500,
440 - /* PowerPC 7x0 exception model */ 483 + /* PowerPC 7x0 exception model */
441 PPC_FLAGS_EXCP_7x0 = 0x00000600, 484 PPC_FLAGS_EXCP_7x0 = 0x00000600,
442 - /* PowerPC 7x5 exception model */ 485 + /* PowerPC 7x5 exception model */
443 PPC_FLAGS_EXCP_7x5 = 0x00000700, 486 PPC_FLAGS_EXCP_7x5 = 0x00000700,
444 - /* PowerPC 74xx exception model */ 487 + /* PowerPC 74xx exception model */
445 PPC_FLAGS_EXCP_74xx = 0x00000800, 488 PPC_FLAGS_EXCP_74xx = 0x00000800,
446 - /* PowerPC 970 exception model */ 489 + /* PowerPC 970 exception model */
447 PPC_FLAGS_EXCP_970 = 0x00000900, 490 PPC_FLAGS_EXCP_970 = 0x00000900,
448 - /* BookE exception model */ 491 + /* BookE exception model */
449 PPC_FLAGS_EXCP_BOOKE = 0x00000A00, 492 PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
450 - /* Input pins model */ 493 + /* Input pins model */
451 PPC_FLAGS_INPUT_MASK = 0x000F0000, 494 PPC_FLAGS_INPUT_MASK = 0x000F0000,
  495 + /* PowerPC 6xx bus */
452 PPC_FLAGS_INPUT_6xx = 0x00000000, 496 PPC_FLAGS_INPUT_6xx = 0x00000000,
  497 + /* BookE bus */
453 PPC_FLAGS_INPUT_BookE = 0x00010000, 498 PPC_FLAGS_INPUT_BookE = 0x00010000,
  499 + /* PowerPC 4xx bus */
454 PPC_FLAGS_INPUT_40x = 0x00020000, 500 PPC_FLAGS_INPUT_40x = 0x00020000,
  501 + /* PowerPC 970 bus */
455 PPC_FLAGS_INPUT_970 = 0x00030000, 502 PPC_FLAGS_INPUT_970 = 0x00030000,
456 }; 503 };
457 504
@@ -466,36 +513,40 @@ enum { @@ -466,36 +513,40 @@ enum {
466 #define PPC_FLAGS_TODO (0x00000000) 513 #define PPC_FLAGS_TODO (0x00000000)
467 514
468 /* PowerPC 40x instruction set */ 515 /* PowerPC 40x instruction set */
469 -#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON) 516 +#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
470 /* PowerPC 401 */ 517 /* PowerPC 401 */
471 -#define PPC_INSNS_401 (PPC_INSNS_TODO)  
472 -#define PPC_FLAGS_401 (PPC_FLAGS_TODO) 518 +#define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  519 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  520 +#define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x | \
  521 + PPC_FLAGS_INPUT_40x)
473 /* PowerPC 403 */ 522 /* PowerPC 403 */
474 #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 523 #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
475 - PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \  
476 - PPC_40x_SPEC) 524 + PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | \
  525 + PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT)
477 #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \ 526 #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
478 PPC_FLAGS_INPUT_40x) 527 PPC_FLAGS_INPUT_40x)
479 /* PowerPC 405 */ 528 /* PowerPC 405 */
480 #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 529 #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
481 - PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \  
482 - PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \  
483 - PPC_405_MAC) 530 + PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  531 + PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC | \
  532 + PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC)
484 #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ 533 #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
485 PPC_FLAGS_INPUT_40x) 534 PPC_FLAGS_INPUT_40x)
486 /* PowerPC 440 */ 535 /* PowerPC 440 */
487 #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \ 536 #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
488 - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) 537 + PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | \
  538 + PPC_440_SPEC)
489 #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ 539 #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
490 PPC_FLAGS_INPUT_BookE) 540 PPC_FLAGS_INPUT_BookE)
491 /* Generic BookE PowerPC */ 541 /* Generic BookE PowerPC */
492 -#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \  
493 - PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT) 542 +#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
  543 + PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT | \
  544 + PPC_CACHE_OPT)
494 #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ 545 #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
495 PPC_FLAGS_INPUT_BookE) 546 PPC_FLAGS_INPUT_BookE)
496 /* e500 core */ 547 /* e500 core */
497 -#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \  
498 - PPC_CACHE_OPT | PPC_E500_VECTOR) 548 +#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
  549 + PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR)
499 #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ 550 #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
500 PPC_FLAGS_INPUT_BookE) 551 PPC_FLAGS_INPUT_BookE)
501 /* Non-embedded PowerPC */ 552 /* Non-embedded PowerPC */
@@ -941,6 +992,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -941,6 +992,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
941 #define SPR_SDR1 (0x019) 992 #define SPR_SDR1 (0x019)
942 #define SPR_SRR0 (0x01A) 993 #define SPR_SRR0 (0x01A)
943 #define SPR_SRR1 (0x01B) 994 #define SPR_SRR1 (0x01B)
  995 +#define SPR_AMR (0x01D)
944 #define SPR_BOOKE_PID (0x030) 996 #define SPR_BOOKE_PID (0x030)
945 #define SPR_BOOKE_DECAR (0x036) 997 #define SPR_BOOKE_DECAR (0x036)
946 #define SPR_BOOKE_CSRR0 (0x03A) 998 #define SPR_BOOKE_CSRR0 (0x03A)
@@ -951,6 +1003,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -951,6 +1003,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
951 #define SPR_8xx_EIE (0x050) 1003 #define SPR_8xx_EIE (0x050)
952 #define SPR_8xx_EID (0x051) 1004 #define SPR_8xx_EID (0x051)
953 #define SPR_8xx_NRE (0x052) 1005 #define SPR_8xx_NRE (0x052)
  1006 +#define SPR_CTRL (0x088)
954 #define SPR_58x_CMPA (0x090) 1007 #define SPR_58x_CMPA (0x090)
955 #define SPR_58x_CMPB (0x091) 1008 #define SPR_58x_CMPB (0x091)
956 #define SPR_58x_CMPC (0x092) 1009 #define SPR_58x_CMPC (0x092)
@@ -959,6 +1012,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -959,6 +1012,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
959 #define SPR_58x_DER (0x094) 1012 #define SPR_58x_DER (0x094)
960 #define SPR_58x_COUNTA (0x096) 1013 #define SPR_58x_COUNTA (0x096)
961 #define SPR_58x_COUNTB (0x097) 1014 #define SPR_58x_COUNTB (0x097)
  1015 +#define SPR_UCTRL (0x098)
962 #define SPR_58x_CMPE (0x098) 1016 #define SPR_58x_CMPE (0x098)
963 #define SPR_58x_CMPF (0x099) 1017 #define SPR_58x_CMPF (0x099)
964 #define SPR_58x_CMPG (0x09A) 1018 #define SPR_58x_CMPG (0x09A)
@@ -992,14 +1046,18 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -992,14 +1046,18 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
992 #define SPR_EAR (0x11A) 1046 #define SPR_EAR (0x11A)
993 #define SPR_TBL (0x11C) 1047 #define SPR_TBL (0x11C)
994 #define SPR_TBU (0x11D) 1048 #define SPR_TBU (0x11D)
  1049 +#define SPR_TBU40 (0x11E)
995 #define SPR_SVR (0x11E) 1050 #define SPR_SVR (0x11E)
996 #define SPR_BOOKE_PIR (0x11E) 1051 #define SPR_BOOKE_PIR (0x11E)
997 #define SPR_PVR (0x11F) 1052 #define SPR_PVR (0x11F)
998 #define SPR_HSPRG0 (0x130) 1053 #define SPR_HSPRG0 (0x130)
999 #define SPR_BOOKE_DBSR (0x130) 1054 #define SPR_BOOKE_DBSR (0x130)
1000 #define SPR_HSPRG1 (0x131) 1055 #define SPR_HSPRG1 (0x131)
  1056 +#define SPR_HDSISR (0x132)
  1057 +#define SPR_HDAR (0x133)
1001 #define SPR_BOOKE_DBCR0 (0x134) 1058 #define SPR_BOOKE_DBCR0 (0x134)
1002 #define SPR_IBCR (0x135) 1059 #define SPR_IBCR (0x135)
  1060 +#define SPR_PURR (0x135)
1003 #define SPR_BOOKE_DBCR1 (0x135) 1061 #define SPR_BOOKE_DBCR1 (0x135)
1004 #define SPR_DBCR (0x136) 1062 #define SPR_DBCR (0x136)
1005 #define SPR_HDEC (0x136) 1063 #define SPR_HDEC (0x136)
@@ -1039,7 +1097,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -1039,7 +1097,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1039 #define SPR_BOOKE_IVOR13 (0x19D) 1097 #define SPR_BOOKE_IVOR13 (0x19D)
1040 #define SPR_BOOKE_IVOR14 (0x19E) 1098 #define SPR_BOOKE_IVOR14 (0x19E)
1041 #define SPR_BOOKE_IVOR15 (0x19F) 1099 #define SPR_BOOKE_IVOR15 (0x19F)
1042 -#define SPR_E500_SPEFSCR (0x200) 1100 +#define SPR_BOOKE_SPEFSCR (0x200)
1043 #define SPR_E500_BBEAR (0x201) 1101 #define SPR_E500_BBEAR (0x201)
1044 #define SPR_E500_BBTAR (0x202) 1102 #define SPR_E500_BBTAR (0x202)
1045 #define SPR_BOOKE_ATBL (0x20E) 1103 #define SPR_BOOKE_ATBL (0x20E)
@@ -1105,29 +1163,62 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -1105,29 +1163,62 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1105 #define SPR_BOOKE_TLB2CFG (0x2B2) 1163 #define SPR_BOOKE_TLB2CFG (0x2B2)
1106 #define SPR_BOOKE_TLB3CFG (0x2B3) 1164 #define SPR_BOOKE_TLB3CFG (0x2B3)
1107 #define SPR_BOOKE_EPR (0x2BE) 1165 #define SPR_BOOKE_EPR (0x2BE)
  1166 +#define SPR_PERF0 (0x300)
  1167 +#define SPR_PERF1 (0x301)
  1168 +#define SPR_PERF2 (0x302)
  1169 +#define SPR_PERF3 (0x303)
  1170 +#define SPR_PERF4 (0x304)
  1171 +#define SPR_PERF5 (0x305)
  1172 +#define SPR_PERF6 (0x306)
  1173 +#define SPR_PERF7 (0x307)
  1174 +#define SPR_PERF8 (0x308)
  1175 +#define SPR_PERF9 (0x309)
  1176 +#define SPR_PERFA (0x30A)
  1177 +#define SPR_PERFB (0x30B)
  1178 +#define SPR_PERFC (0x30C)
  1179 +#define SPR_PERFD (0x30D)
  1180 +#define SPR_PERFE (0x30E)
  1181 +#define SPR_PERFF (0x30F)
  1182 +#define SPR_UPERF0 (0x310)
  1183 +#define SPR_UPERF1 (0x311)
  1184 +#define SPR_UPERF2 (0x312)
  1185 +#define SPR_UPERF3 (0x313)
  1186 +#define SPR_UPERF4 (0x314)
  1187 +#define SPR_UPERF5 (0x315)
  1188 +#define SPR_UPERF6 (0x316)
  1189 +#define SPR_UPERF7 (0x317)
  1190 +#define SPR_UPERF8 (0x318)
  1191 +#define SPR_UPERF9 (0x319)
  1192 +#define SPR_UPERFA (0x31A)
  1193 +#define SPR_UPERFB (0x31B)
  1194 +#define SPR_UPERFC (0x31C)
  1195 +#define SPR_UPERFD (0x31D)
  1196 +#define SPR_UPERFE (0x31E)
  1197 +#define SPR_UPERFF (0x31F)
1108 #define SPR_440_INV0 (0x370) 1198 #define SPR_440_INV0 (0x370)
1109 #define SPR_440_INV1 (0x371) 1199 #define SPR_440_INV1 (0x371)
1110 #define SPR_440_INV2 (0x372) 1200 #define SPR_440_INV2 (0x372)
1111 #define SPR_440_INV3 (0x373) 1201 #define SPR_440_INV3 (0x373)
1112 -#define SPR_440_IVT0 (0x374)  
1113 -#define SPR_440_IVT1 (0x375)  
1114 -#define SPR_440_IVT2 (0x376)  
1115 -#define SPR_440_IVT3 (0x377) 1202 +#define SPR_440_ITV0 (0x374)
  1203 +#define SPR_440_ITV1 (0x375)
  1204 +#define SPR_440_ITV2 (0x376)
  1205 +#define SPR_440_ITV3 (0x377)
  1206 +#define SPR_PPR (0x380)
1116 #define SPR_440_DNV0 (0x390) 1207 #define SPR_440_DNV0 (0x390)
1117 #define SPR_440_DNV1 (0x391) 1208 #define SPR_440_DNV1 (0x391)
1118 #define SPR_440_DNV2 (0x392) 1209 #define SPR_440_DNV2 (0x392)
1119 #define SPR_440_DNV3 (0x393) 1210 #define SPR_440_DNV3 (0x393)
1120 -#define SPR_440_DVT0 (0x394)  
1121 -#define SPR_440_DVT1 (0x395)  
1122 -#define SPR_440_DVT2 (0x396)  
1123 -#define SPR_440_DVT3 (0x397) 1211 +#define SPR_440_DTV0 (0x394)
  1212 +#define SPR_440_DTV1 (0x395)
  1213 +#define SPR_440_DTV2 (0x396)
  1214 +#define SPR_440_DTV3 (0x397)
1124 #define SPR_440_DVLIM (0x398) 1215 #define SPR_440_DVLIM (0x398)
1125 #define SPR_440_IVLIM (0x399) 1216 #define SPR_440_IVLIM (0x399)
1126 #define SPR_440_RSTCFG (0x39B) 1217 #define SPR_440_RSTCFG (0x39B)
1127 -#define SPR_BOOKE_DCBTRL (0x39C)  
1128 -#define SPR_BOOKE_DCBTRH (0x39D)  
1129 -#define SPR_BOOKE_ICBTRL (0x39E)  
1130 -#define SPR_BOOKE_ICBTRH (0x39F) 1218 +#define SPR_BOOKE_DCDBTRL (0x39C)
  1219 +#define SPR_BOOKE_DCDBTRH (0x39D)
  1220 +#define SPR_BOOKE_ICDBTRL (0x39E)
  1221 +#define SPR_BOOKE_ICDBTRH (0x39F)
1131 #define SPR_UMMCR0 (0x3A8) 1222 #define SPR_UMMCR0 (0x3A8)
1132 #define SPR_UPMC1 (0x3A9) 1223 #define SPR_UPMC1 (0x3A9)
1133 #define SPR_UPMC2 (0x3AA) 1224 #define SPR_UPMC2 (0x3AA)
@@ -1166,7 +1257,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -1166,7 +1257,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1166 #define SPR_DCMP (0x3D1) 1257 #define SPR_DCMP (0x3D1)
1167 #define SPR_HASH1 (0x3D2) 1258 #define SPR_HASH1 (0x3D2)
1168 #define SPR_HASH2 (0x3D3) 1259 #define SPR_HASH2 (0x3D3)
1169 -#define SPR_BOOKE_ICBDR (0x3D3) 1260 +#define SPR_BOOKE_ICDBDR (0x3D3)
1170 #define SPR_IMISS (0x3D4) 1261 #define SPR_IMISS (0x3D4)
1171 #define SPR_40x_ESR (0x3D4) 1262 #define SPR_40x_ESR (0x3D4)
1172 #define SPR_ICMP (0x3D5) 1263 #define SPR_ICMP (0x3D5)
@@ -1204,6 +1295,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); @@ -1204,6 +1295,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1204 #define SPR_40x_IAC2 (0x3F5) 1295 #define SPR_40x_IAC2 (0x3F5)
1205 #define SPR_601_HID5 (0x3F5) 1296 #define SPR_601_HID5 (0x3F5)
1206 #define SPR_40x_DAC1 (0x3F6) 1297 #define SPR_40x_DAC1 (0x3F6)
  1298 +#define SPR_DABRX (0x3F7)
1207 #define SPR_40x_DAC2 (0x3F7) 1299 #define SPR_40x_DAC2 (0x3F7)
1208 #define SPR_BOOKE_MMUCFG (0x3F7) 1300 #define SPR_BOOKE_MMUCFG (0x3F7)
1209 #define SPR_L2PM (0x3F8) 1301 #define SPR_L2PM (0x3F8)
target-ppc/helper.c
  View file @2662a05
@@ -1072,6 +1072,7 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx, @@ -1072,6 +1072,7 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1072 case PPC_FLAGS_MMU_SOFT_6xx: 1072 case PPC_FLAGS_MMU_SOFT_6xx:
1073 case PPC_FLAGS_MMU_601: 1073 case PPC_FLAGS_MMU_601:
1074 case PPC_FLAGS_MMU_SOFT_4xx: 1074 case PPC_FLAGS_MMU_SOFT_4xx:
  1075 + case PPC_FLAGS_MMU_401:
1075 ctx->prot |= PAGE_WRITE; 1076 ctx->prot |= PAGE_WRITE;
1076 break; 1077 break;
1077 #if defined(TARGET_PPC64) 1078 #if defined(TARGET_PPC64)
@@ -1168,6 +1169,9 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, @@ -1168,6 +1169,9 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1168 /* XXX: TODO */ 1169 /* XXX: TODO */
1169 cpu_abort(env, "BookE FSL MMU model not implemented\n"); 1170 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1170 return -1; 1171 return -1;
  1172 + case PPC_FLAGS_MMU_401:
  1173 + cpu_abort(env, "PowerPC 401 does not do any translation\n");
  1174 + return -1;
1171 default: 1175 default:
1172 cpu_abort(env, "Unknown or invalid MMU model\n"); 1176 cpu_abort(env, "Unknown or invalid MMU model\n");
1173 return -1; 1177 return -1;
@@ -1267,6 +1271,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, @@ -1267,6 +1271,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1267 /* XXX: TODO */ 1271 /* XXX: TODO */
1268 cpu_abort(env, "MMU model not implemented\n"); 1272 cpu_abort(env, "MMU model not implemented\n");
1269 return -1; 1273 return -1;
  1274 + case PPC_FLAGS_MMU_401:
  1275 + cpu_abort(env, "PowerPC 401 should never raise any MMU "
  1276 + "exceptions\n");
  1277 + return -1;
1270 default: 1278 default:
1271 cpu_abort(env, "Unknown or invalid MMU model\n"); 1279 cpu_abort(env, "Unknown or invalid MMU model\n");
1272 return -1; 1280 return -1;
@@ -1348,6 +1356,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, @@ -1348,6 +1356,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1348 /* XXX: TODO */ 1356 /* XXX: TODO */
1349 cpu_abort(env, "MMU model not implemented\n"); 1357 cpu_abort(env, "MMU model not implemented\n");
1350 return -1; 1358 return -1;
  1359 + case PPC_FLAGS_MMU_401:
  1360 + cpu_abort(env, "PowerPC 401 should never raise any MMU "
  1361 + "exceptions\n");
  1362 + return -1;
1351 default: 1363 default:
1352 cpu_abort(env, "Unknown or invalid MMU model\n"); 1364 cpu_abort(env, "Unknown or invalid MMU model\n");
1353 return -1; 1365 return -1;
target-ppc/translate.c
  View file @2662a05
@@ -4221,12 +4221,14 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) @@ -4221,12 +4221,14 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4221 } 4221 }
4222 4222
4223 /* BookE specific instructions */ 4223 /* BookE specific instructions */
  4224 +/* XXX: not implemented on 440 ? */
4224 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE) 4225 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE)
4225 { 4226 {
4226 /* XXX: TODO */ 4227 /* XXX: TODO */
4227 RET_INVAL(ctx); 4228 RET_INVAL(ctx);
4228 } 4229 }
4229 4230
  4231 +/* XXX: not implemented on 440 ? */
4230 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE) 4232 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE)
4231 { 4233 {
4232 #if defined(CONFIG_USER_ONLY) 4234 #if defined(CONFIG_USER_ONLY)
@@ -4329,98 +4331,99 @@ static inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3, @@ -4329,98 +4331,99 @@ static inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3,
4329 } 4331 }
4330 } 4332 }
4331 4333
4332 -#define GEN_MAC_HANDLER(name, opc2, opc3) \  
4333 -GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ 4334 +#define GEN_MAC_HANDLER(name, opc2, opc3, is_440) \
  4335 +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, \
  4336 + is_440 ? PPC_440_SPEC : PPC_405_MAC) \
4334 { \ 4337 { \
4335 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 4338 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4336 rD(ctx->opcode), Rc(ctx->opcode)); \ 4339 rD(ctx->opcode), Rc(ctx->opcode)); \
4337 } 4340 }
4338 4341
4339 /* macchw - macchw. */ 4342 /* macchw - macchw. */
4340 -GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 4343 +GEN_MAC_HANDLER(macchw, 0x0C, 0x05, 0);
4341 /* macchwo - macchwo. */ 4344 /* macchwo - macchwo. */
4342 -GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 4345 +GEN_MAC_HANDLER(macchwo, 0x0C, 0x15, 0);
4343 /* macchws - macchws. */ 4346 /* macchws - macchws. */
4344 -GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 4347 +GEN_MAC_HANDLER(macchws, 0x0C, 0x07, 0);
4345 /* macchwso - macchwso. */ 4348 /* macchwso - macchwso. */
4346 -GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 4349 +GEN_MAC_HANDLER(macchwso, 0x0C, 0x17, 0);
4347 /* macchwsu - macchwsu. */ 4350 /* macchwsu - macchwsu. */
4348 -GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 4351 +GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06, 0);
4349 /* macchwsuo - macchwsuo. */ 4352 /* macchwsuo - macchwsuo. */
4350 -GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 4353 +GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16, 0);
4351 /* macchwu - macchwu. */ 4354 /* macchwu - macchwu. */
4352 -GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 4355 +GEN_MAC_HANDLER(macchwu, 0x0C, 0x04, 0);
4353 /* macchwuo - macchwuo. */ 4356 /* macchwuo - macchwuo. */
4354 -GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 4357 +GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14, 0);
4355 /* machhw - machhw. */ 4358 /* machhw - machhw. */
4356 -GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 4359 +GEN_MAC_HANDLER(machhw, 0x0C, 0x01, 0);
4357 /* machhwo - machhwo. */ 4360 /* machhwo - machhwo. */
4358 -GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 4361 +GEN_MAC_HANDLER(machhwo, 0x0C, 0x11, 0);
4359 /* machhws - machhws. */ 4362 /* machhws - machhws. */
4360 -GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 4363 +GEN_MAC_HANDLER(machhws, 0x0C, 0x03, 0);
4361 /* machhwso - machhwso. */ 4364 /* machhwso - machhwso. */
4362 -GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 4365 +GEN_MAC_HANDLER(machhwso, 0x0C, 0x13, 0);
4363 /* machhwsu - machhwsu. */ 4366 /* machhwsu - machhwsu. */
4364 -GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 4367 +GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02, 0);
4365 /* machhwsuo - machhwsuo. */ 4368 /* machhwsuo - machhwsuo. */
4366 -GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 4369 +GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12, 0);
4367 /* machhwu - machhwu. */ 4370 /* machhwu - machhwu. */
4368 -GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 4371 +GEN_MAC_HANDLER(machhwu, 0x0C, 0x00, 0);
4369 /* machhwuo - machhwuo. */ 4372 /* machhwuo - machhwuo. */
4370 -GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 4373 +GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10, 0);
4371 /* maclhw - maclhw. */ 4374 /* maclhw - maclhw. */
4372 -GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 4375 +GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D, 0);
4373 /* maclhwo - maclhwo. */ 4376 /* maclhwo - maclhwo. */
4374 -GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 4377 +GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D, 0);
4375 /* maclhws - maclhws. */ 4378 /* maclhws - maclhws. */
4376 -GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 4379 +GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F, 0);
4377 /* maclhwso - maclhwso. */ 4380 /* maclhwso - maclhwso. */
4378 -GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 4381 +GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F, 0);
4379 /* maclhwu - maclhwu. */ 4382 /* maclhwu - maclhwu. */
4380 -GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 4383 +GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C, 0);
4381 /* maclhwuo - maclhwuo. */ 4384 /* maclhwuo - maclhwuo. */
4382 -GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 4385 +GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C, 0);
4383 /* maclhwsu - maclhwsu. */ 4386 /* maclhwsu - maclhwsu. */
4384 -GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 4387 +GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E, 0);
4385 /* maclhwsuo - maclhwsuo. */ 4388 /* maclhwsuo - maclhwsuo. */
4386 -GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 4389 +GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E, 0);
4387 /* nmacchw - nmacchw. */ 4390 /* nmacchw - nmacchw. */
4388 -GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 4391 +GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05, 0);
4389 /* nmacchwo - nmacchwo. */ 4392 /* nmacchwo - nmacchwo. */
4390 -GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 4393 +GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15, 0);
4391 /* nmacchws - nmacchws. */ 4394 /* nmacchws - nmacchws. */
4392 -GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 4395 +GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07, 0);
4393 /* nmacchwso - nmacchwso. */ 4396 /* nmacchwso - nmacchwso. */
4394 -GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 4397 +GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17, 0);
4395 /* nmachhw - nmachhw. */ 4398 /* nmachhw - nmachhw. */
4396 -GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 4399 +GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01, 0);
4397 /* nmachhwo - nmachhwo. */ 4400 /* nmachhwo - nmachhwo. */
4398 -GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 4401 +GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11, 0);
4399 /* nmachhws - nmachhws. */ 4402 /* nmachhws - nmachhws. */
4400 -GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 4403 +GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03, 1);
4401 /* nmachhwso - nmachhwso. */ 4404 /* nmachhwso - nmachhwso. */
4402 -GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 4405 +GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13, 1);
4403 /* nmaclhw - nmaclhw. */ 4406 /* nmaclhw - nmaclhw. */
4404 -GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 4407 +GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D, 1);
4405 /* nmaclhwo - nmaclhwo. */ 4408 /* nmaclhwo - nmaclhwo. */
4406 -GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 4409 +GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D, 1);
4407 /* nmaclhws - nmaclhws. */ 4410 /* nmaclhws - nmaclhws. */
4408 -GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 4411 +GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F, 1);
4409 /* nmaclhwso - nmaclhwso. */ 4412 /* nmaclhwso - nmaclhwso. */
4410 -GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 4413 +GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F, 1);
4411 4414
4412 /* mulchw - mulchw. */ 4415 /* mulchw - mulchw. */
4413 -GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 4416 +GEN_MAC_HANDLER(mulchw, 0x08, 0x05, 0);
4414 /* mulchwu - mulchwu. */ 4417 /* mulchwu - mulchwu. */
4415 -GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 4418 +GEN_MAC_HANDLER(mulchwu, 0x08, 0x04, 0);
4416 /* mulhhw - mulhhw. */ 4419 /* mulhhw - mulhhw. */
4417 -GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 4420 +GEN_MAC_HANDLER(mulhhw, 0x08, 0x01, 0);
4418 /* mulhhwu - mulhhwu. */ 4421 /* mulhhwu - mulhhwu. */
4419 -GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 4422 +GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00, 0);
4420 /* mullhw - mullhw. */ 4423 /* mullhw - mullhw. */
4421 -GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 4424 +GEN_MAC_HANDLER(mullhw, 0x08, 0x0D, 0);
4422 /* mullhwu - mullhwu. */ 4425 /* mullhwu - mullhwu. */
4423 -GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 4426 +GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C, 0);
4424 4427
4425 /* mfdcr */ 4428 /* mfdcr */
4426 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON) 4429 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
@@ -4459,6 +4462,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON) @@ -4459,6 +4462,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
4459 } 4462 }
4460 4463
4461 /* mfdcrx */ 4464 /* mfdcrx */
  4465 +/* XXX: not implemented on 440 ? */
4462 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE) 4466 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE)
4463 { 4467 {
4464 #if defined(CONFIG_USER_ONLY) 4468 #if defined(CONFIG_USER_ONLY)
@@ -4475,6 +4479,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE) @@ -4475,6 +4479,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE)
4475 } 4479 }
4476 4480
4477 /* mtdcrx */ 4481 /* mtdcrx */
  4482 +/* XXX: not implemented on 440 ? */
4478 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE) 4483 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE)
4479 { 4484 {
4480 #if defined(CONFIG_USER_ONLY) 4485 #if defined(CONFIG_USER_ONLY)
@@ -4521,7 +4526,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) @@ -4521,7 +4526,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4521 } 4526 }
4522 4527
4523 /* icbt */ 4528 /* icbt */
4524 -GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_SPEC) 4529 +GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
4525 { 4530 {
4526 /* interpreted as no-op */ 4531 /* interpreted as no-op */
4527 /* XXX: specification say this is treated as a load by the MMU 4532 /* XXX: specification say this is treated as a load by the MMU
@@ -4589,6 +4594,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) @@ -4589,6 +4594,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4589 } 4594 }
4590 4595
4591 /* BookE specific */ 4596 /* BookE specific */
  4597 +/* XXX: not implemented on 440 ? */
4592 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE) 4598 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE)
4593 { 4599 {
4594 #if defined(CONFIG_USER_ONLY) 4600 #if defined(CONFIG_USER_ONLY)
@@ -4604,6 +4610,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE) @@ -4604,6 +4610,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE)
4604 #endif 4610 #endif
4605 } 4611 }
4606 4612
  4613 +/* XXX: not implemented on 440 ? */
4607 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE) 4614 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE)
4608 { 4615 {
4609 #if defined(CONFIG_USER_ONLY) 4616 #if defined(CONFIG_USER_ONLY)
target-ppc/translate_init.c
  View file @2662a05
@@ -1123,6 +1123,7 @@ static void gen_spr_BookE (CPUPPCState *env) @@ -1123,6 +1123,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1123 SPR_NOACCESS, SPR_NOACCESS, 1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic, 1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000); 1125 0x00000000);
  1126 +#if 0
1126 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1127 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1127 SPR_NOACCESS, SPR_NOACCESS, 1128 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic, 1129 &spr_read_generic, &spr_write_generic,
@@ -1139,6 +1140,7 @@ static void gen_spr_BookE (CPUPPCState *env) @@ -1139,6 +1140,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1139 SPR_NOACCESS, SPR_NOACCESS, 1140 SPR_NOACCESS, SPR_NOACCESS,
1140 &spr_read_generic, &spr_write_generic, 1141 &spr_read_generic, &spr_write_generic,
1141 0x00000000); 1142 0x00000000);
  1143 +#endif
1142 /* Debug */ 1144 /* Debug */
1143 /* XXX : not implemented */ 1145 /* XXX : not implemented */
1144 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1146 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
@@ -1277,6 +1279,7 @@ static void gen_spr_BookE (CPUPPCState *env) @@ -1277,6 +1279,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1277 SPR_NOACCESS, SPR_NOACCESS, 1279 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic, 1280 &spr_read_generic, &spr_write_generic,
1279 0x00000000); 1281 0x00000000);
  1282 +#if 0
1280 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32", 1283 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1281 SPR_NOACCESS, SPR_NOACCESS, 1284 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic, 1285 &spr_read_generic, &spr_write_generic,
@@ -1301,6 +1304,7 @@ static void gen_spr_BookE (CPUPPCState *env) @@ -1301,6 +1304,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1301 SPR_NOACCESS, SPR_NOACCESS, 1304 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic, 1305 &spr_read_generic, &spr_write_generic,
1303 0x00000000); 1306 0x00000000);
  1307 +#endif
1304 spr_register(env, SPR_BOOKE_PID, "PID", 1308 spr_register(env, SPR_BOOKE_PID, "PID",
1305 SPR_NOACCESS, SPR_NOACCESS, 1309 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic, 1310 &spr_read_generic, &spr_write_generic,
@@ -1469,22 +1473,22 @@ static void gen_spr_440 (CPUPPCState *env) @@ -1469,22 +1473,22 @@ static void gen_spr_440 (CPUPPCState *env)
1469 &spr_read_generic, &spr_write_generic, 1473 &spr_read_generic, &spr_write_generic,
1470 0x00000000); 1474 0x00000000);
1471 /* XXX : not implemented */ 1475 /* XXX : not implemented */
1472 - spr_register(env, SPR_440_DVT0, "DVT0", 1476 + spr_register(env, SPR_440_DTV0, "DTV0",
1473 SPR_NOACCESS, SPR_NOACCESS, 1477 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic, 1478 &spr_read_generic, &spr_write_generic,
1475 0x00000000); 1479 0x00000000);
1476 /* XXX : not implemented */ 1480 /* XXX : not implemented */
1477 - spr_register(env, SPR_440_DVT1, "DVT1", 1481 + spr_register(env, SPR_440_DTV1, "DTV1",
1478 SPR_NOACCESS, SPR_NOACCESS, 1482 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic, 1483 &spr_read_generic, &spr_write_generic,
1480 0x00000000); 1484 0x00000000);
1481 /* XXX : not implemented */ 1485 /* XXX : not implemented */
1482 - spr_register(env, SPR_440_DVT2, "DVT2", 1486 + spr_register(env, SPR_440_DTV2, "DTV2",
1483 SPR_NOACCESS, SPR_NOACCESS, 1487 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic, 1488 &spr_read_generic, &spr_write_generic,
1485 0x00000000); 1489 0x00000000);
1486 /* XXX : not implemented */ 1490 /* XXX : not implemented */
1487 - spr_register(env, SPR_440_DVT3, "DVT3", 1491 + spr_register(env, SPR_440_DTV3, "DTV3",
1488 SPR_NOACCESS, SPR_NOACCESS, 1492 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_generic, &spr_write_generic, 1493 &spr_read_generic, &spr_write_generic,
1490 0x00000000); 1494 0x00000000);
@@ -1514,22 +1518,22 @@ static void gen_spr_440 (CPUPPCState *env) @@ -1514,22 +1518,22 @@ static void gen_spr_440 (CPUPPCState *env)
1514 &spr_read_generic, &spr_write_generic, 1518 &spr_read_generic, &spr_write_generic,
1515 0x00000000); 1519 0x00000000);
1516 /* XXX : not implemented */ 1520 /* XXX : not implemented */
1517 - spr_register(env, SPR_440_IVT0, "IVT0", 1521 + spr_register(env, SPR_440_ITV0, "ITV0",
1518 SPR_NOACCESS, SPR_NOACCESS, 1522 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic, 1523 &spr_read_generic, &spr_write_generic,
1520 0x00000000); 1524 0x00000000);
1521 /* XXX : not implemented */ 1525 /* XXX : not implemented */
1522 - spr_register(env, SPR_440_IVT1, "IVT1", 1526 + spr_register(env, SPR_440_ITV1, "ITV1",
1523 SPR_NOACCESS, SPR_NOACCESS, 1527 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic, 1528 &spr_read_generic, &spr_write_generic,
1525 0x00000000); 1529 0x00000000);
1526 /* XXX : not implemented */ 1530 /* XXX : not implemented */
1527 - spr_register(env, SPR_440_IVT2, "IVT2", 1531 + spr_register(env, SPR_440_ITV2, "ITV2",
1528 SPR_NOACCESS, SPR_NOACCESS, 1532 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic, 1533 &spr_read_generic, &spr_write_generic,
1530 0x00000000); 1534 0x00000000);
1531 /* XXX : not implemented */ 1535 /* XXX : not implemented */
1532 - spr_register(env, SPR_440_IVT3, "IVT3", 1536 + spr_register(env, SPR_440_ITV3, "ITV3",
1533 SPR_NOACCESS, SPR_NOACCESS, 1537 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic, 1538 &spr_read_generic, &spr_write_generic,
1535 0x00000000); 1539 0x00000000);
@@ -1540,27 +1544,27 @@ static void gen_spr_440 (CPUPPCState *env) @@ -1540,27 +1544,27 @@ static void gen_spr_440 (CPUPPCState *env)
1540 0x00000000); 1544 0x00000000);
1541 /* Cache debug */ 1545 /* Cache debug */
1542 /* XXX : not implemented */ 1546 /* XXX : not implemented */
1543 - spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH", 1547 + spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1544 SPR_NOACCESS, SPR_NOACCESS, 1548 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, SPR_NOACCESS, 1549 &spr_read_generic, SPR_NOACCESS,
1546 0x00000000); 1550 0x00000000);
1547 /* XXX : not implemented */ 1551 /* XXX : not implemented */
1548 - spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL", 1552 + spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1549 SPR_NOACCESS, SPR_NOACCESS, 1553 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, SPR_NOACCESS, 1554 &spr_read_generic, SPR_NOACCESS,
1551 0x00000000); 1555 0x00000000);
1552 /* XXX : not implemented */ 1556 /* XXX : not implemented */
1553 - spr_register(env, SPR_BOOKE_ICBDR, "ICBDR", 1557 + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1554 SPR_NOACCESS, SPR_NOACCESS, 1558 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, SPR_NOACCESS, 1559 &spr_read_generic, SPR_NOACCESS,
1556 0x00000000); 1560 0x00000000);
1557 /* XXX : not implemented */ 1561 /* XXX : not implemented */
1558 - spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH", 1562 + spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1559 SPR_NOACCESS, SPR_NOACCESS, 1563 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, SPR_NOACCESS, 1564 &spr_read_generic, SPR_NOACCESS,
1561 0x00000000); 1565 0x00000000);
1562 /* XXX : not implemented */ 1566 /* XXX : not implemented */
1563 - spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL", 1567 + spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1564 SPR_NOACCESS, SPR_NOACCESS, 1568 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, SPR_NOACCESS, 1569 &spr_read_generic, SPR_NOACCESS,
1566 0x00000000); 1570 0x00000000);
@@ -1605,7 +1609,7 @@ static void gen_spr_40x (CPUPPCState *env) @@ -1605,7 +1609,7 @@ static void gen_spr_40x (CPUPPCState *env)
1605 &spr_read_generic, &spr_write_generic, 1609 &spr_read_generic, &spr_write_generic,
1606 0x00000000); 1610 0x00000000);
1607 /* XXX : not implemented */ 1611 /* XXX : not implemented */
1608 - spr_register(env, SPR_BOOKE_ICBDR, "ICBDR", 1612 + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1609 SPR_NOACCESS, SPR_NOACCESS, 1613 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, SPR_NOACCESS, 1614 &spr_read_generic, SPR_NOACCESS,
1611 0x00000000); 1615 0x00000000);
@@ -1614,15 +1618,6 @@ static void gen_spr_40x (CPUPPCState *env) @@ -1614,15 +1618,6 @@ static void gen_spr_40x (CPUPPCState *env)
1614 SPR_NOACCESS, SPR_NOACCESS, 1618 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic, 1619 &spr_read_generic, &spr_write_generic,
1616 0xFFFFFFFF); 1620 0xFFFFFFFF);
1617 - spr_register(env, SPR_40x_ZPR, "ZPR",  
1618 - SPR_NOACCESS, SPR_NOACCESS,  
1619 - &spr_read_generic, &spr_write_generic,  
1620 - 0x00000000);  
1621 - /* MMU */  
1622 - spr_register(env, SPR_40x_PID, "PID",  
1623 - SPR_NOACCESS, SPR_NOACCESS,  
1624 - &spr_read_generic, &spr_write_generic,  
1625 - 0x00000000);  
1626 /* Exception */ 1621 /* Exception */
1627 spr_register(env, SPR_40x_DEAR, "DEAR", 1622 spr_register(env, SPR_40x_DEAR, "DEAR",
1628 SPR_NOACCESS, SPR_NOACCESS, 1623 SPR_NOACCESS, SPR_NOACCESS,
@@ -1657,58 +1652,62 @@ static void gen_spr_40x (CPUPPCState *env) @@ -1657,58 +1652,62 @@ static void gen_spr_40x (CPUPPCState *env)
1657 SPR_NOACCESS, SPR_NOACCESS, 1652 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_booke_tsr, 1653 &spr_read_generic, &spr_write_booke_tsr,
1659 0x00000000); 1654 0x00000000);
1660 - /* Debug interface */  
1661 - /* XXX : not implemented */  
1662 - spr_register(env, SPR_40x_DAC1, "DAC1", 1655 +}
  1656 +
  1657 +/* SPR specific to PowerPC 405 implementation */
  1658 +static void gen_spr_405 (CPUPPCState *env)
  1659 +{
  1660 + /* MMU */
  1661 + spr_register(env, SPR_40x_PID, "PID",
1663 SPR_NOACCESS, SPR_NOACCESS, 1662 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic, 1663 &spr_read_generic, &spr_write_generic,
1665 0x00000000); 1664 0x00000000);
1666 - spr_register(env, SPR_40x_DAC2, "DAC2", 1665 + spr_register(env, SPR_4xx_CCR0, "CCR0",
1667 SPR_NOACCESS, SPR_NOACCESS, 1666 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic, 1667 &spr_read_generic, &spr_write_generic,
1669 - 0x00000000); 1668 + 0x00700000);
  1669 + /* Debug interface */
1670 /* XXX : not implemented */ 1670 /* XXX : not implemented */
1671 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1671 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1672 SPR_NOACCESS, SPR_NOACCESS, 1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_40x_dbcr0, 1673 &spr_read_generic, &spr_write_40x_dbcr0,
1674 0x00000000); 1674 0x00000000);
1675 /* XXX : not implemented */ 1675 /* XXX : not implemented */
  1676 + spr_register(env, SPR_405_DBCR1, "DBCR1",
  1677 + SPR_NOACCESS, SPR_NOACCESS,
  1678 + &spr_read_generic, &spr_write_generic,
  1679 + 0x00000000);
  1680 + /* XXX : not implemented */
1676 spr_register(env, SPR_40x_DBSR, "DBSR", 1681 spr_register(env, SPR_40x_DBSR, "DBSR",
1677 SPR_NOACCESS, SPR_NOACCESS, 1682 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_clear, 1683 &spr_read_generic, &spr_write_clear,
1679 /* Last reset was system reset */ 1684 /* Last reset was system reset */
1680 0x00000300); 1685 0x00000300);
1681 /* XXX : not implemented */ 1686 /* XXX : not implemented */
1682 - spr_register(env, SPR_40x_IAC1, "IAC1", 1687 + spr_register(env, SPR_40x_DAC1, "DAC1",
1683 SPR_NOACCESS, SPR_NOACCESS, 1688 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic, 1689 &spr_read_generic, &spr_write_generic,
1685 0x00000000); 1690 0x00000000);
1686 - spr_register(env, SPR_40x_IAC2, "IAC2", 1691 + spr_register(env, SPR_40x_DAC2, "DAC2",
1687 SPR_NOACCESS, SPR_NOACCESS, 1692 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic, 1693 &spr_read_generic, &spr_write_generic,
1689 0x00000000); 1694 0x00000000);
1690 -}  
1691 -  
1692 -/* SPR specific to PowerPC 405 implementation */  
1693 -static void gen_spr_405 (CPUPPCState *env)  
1694 -{  
1695 - spr_register(env, SPR_4xx_CCR0, "CCR0", 1695 + /* XXX : not implemented */
  1696 + spr_register(env, SPR_405_DVC1, "DVC1",
1696 SPR_NOACCESS, SPR_NOACCESS, 1697 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic, 1698 &spr_read_generic, &spr_write_generic,
1698 - 0x00700000);  
1699 - /* Debug */ 1699 + 0x00000000);
1700 /* XXX : not implemented */ 1700 /* XXX : not implemented */
1701 - spr_register(env, SPR_405_DBCR1, "DBCR1", 1701 + spr_register(env, SPR_405_DVC2, "DVC2",
1702 SPR_NOACCESS, SPR_NOACCESS, 1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic, 1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000); 1704 0x00000000);
1705 /* XXX : not implemented */ 1705 /* XXX : not implemented */
1706 - spr_register(env, SPR_405_DVC1, "DVC1", 1706 + spr_register(env, SPR_40x_IAC1, "IAC1",
1707 SPR_NOACCESS, SPR_NOACCESS, 1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic, 1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000); 1709 0x00000000);
1710 - /* XXX : not implemented */  
1711 - spr_register(env, SPR_405_DVC2, "DVC2", 1710 + spr_register(env, SPR_40x_IAC2, "IAC2",
1712 SPR_NOACCESS, SPR_NOACCESS, 1711 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic, 1712 &spr_read_generic, &spr_write_generic,
1714 0x00000000); 1713 0x00000000);
@@ -1727,6 +1726,10 @@ static void gen_spr_405 (CPUPPCState *env) @@ -1727,6 +1726,10 @@ static void gen_spr_405 (CPUPPCState *env)
1727 SPR_NOACCESS, SPR_NOACCESS, 1726 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_40x_sler, 1727 &spr_read_generic, &spr_write_40x_sler,
1729 0x00000000); 1728 0x00000000);
  1729 + spr_register(env, SPR_40x_ZPR, "ZPR",
  1730 + SPR_NOACCESS, SPR_NOACCESS,
  1731 + &spr_read_generic, &spr_write_generic,
  1732 + 0x00000000);
1730 /* XXX : not implemented */ 1733 /* XXX : not implemented */
1731 spr_register(env, SPR_405_SU0R, "SU0R", 1734 spr_register(env, SPR_405_SU0R, "SU0R",
1732 SPR_NOACCESS, SPR_NOACCESS, 1735 SPR_NOACCESS, SPR_NOACCESS,
@@ -1799,10 +1802,76 @@ static void gen_spr_401_403 (CPUPPCState *env) @@ -1799,10 +1802,76 @@ static void gen_spr_401_403 (CPUPPCState *env)
1799 0x00000000); 1802 0x00000000);
1800 } 1803 }
1801 1804
  1805 +/* SPR specific to PowerPC 401 implementation */
  1806 +static void gen_spr_401 (CPUPPCState *env)
  1807 +{
  1808 + /* Debug interface */
  1809 + /* XXX : not implemented */
  1810 + spr_register(env, SPR_40x_DBCR0, "DBCR",
  1811 + SPR_NOACCESS, SPR_NOACCESS,
  1812 + &spr_read_generic, &spr_write_40x_dbcr0,
  1813 + 0x00000000);
  1814 + /* XXX : not implemented */
  1815 + spr_register(env, SPR_40x_DBSR, "DBSR",
  1816 + SPR_NOACCESS, SPR_NOACCESS,
  1817 + &spr_read_generic, &spr_write_clear,
  1818 + /* Last reset was system reset */
  1819 + 0x00000300);
  1820 + /* XXX : not implemented */
  1821 + spr_register(env, SPR_40x_DAC1, "DAC",
  1822 + SPR_NOACCESS, SPR_NOACCESS,
  1823 + &spr_read_generic, &spr_write_generic,
  1824 + 0x00000000);
  1825 + /* XXX : not implemented */
  1826 + spr_register(env, SPR_40x_IAC1, "IAC",
  1827 + SPR_NOACCESS, SPR_NOACCESS,
  1828 + &spr_read_generic, &spr_write_generic,
  1829 + 0x00000000);
  1830 + /* Storage control */
  1831 + spr_register(env, SPR_405_SLER, "SLER",
  1832 + SPR_NOACCESS, SPR_NOACCESS,
  1833 + &spr_read_generic, &spr_write_40x_sler,
  1834 + 0x00000000);
  1835 +}
  1836 +
1802 /* SPR specific to PowerPC 403 implementation */ 1837 /* SPR specific to PowerPC 403 implementation */
1803 static void gen_spr_403 (CPUPPCState *env) 1838 static void gen_spr_403 (CPUPPCState *env)
1804 { 1839 {
  1840 + /* Debug interface */
  1841 + /* XXX : not implemented */
  1842 + spr_register(env, SPR_40x_DBCR0, "DBCR0",
  1843 + SPR_NOACCESS, SPR_NOACCESS,
  1844 + &spr_read_generic, &spr_write_40x_dbcr0,
  1845 + 0x00000000);
  1846 + /* XXX : not implemented */
  1847 + spr_register(env, SPR_40x_DBSR, "DBSR",
  1848 + SPR_NOACCESS, SPR_NOACCESS,
  1849 + &spr_read_generic, &spr_write_clear,
  1850 + /* Last reset was system reset */
  1851 + 0x00000300);
  1852 + /* XXX : not implemented */
  1853 + spr_register(env, SPR_40x_DAC1, "DAC1",
  1854 + SPR_NOACCESS, SPR_NOACCESS,
  1855 + &spr_read_generic, &spr_write_generic,
  1856 + 0x00000000);
  1857 + spr_register(env, SPR_40x_DAC2, "DAC2",
  1858 + SPR_NOACCESS, SPR_NOACCESS,
  1859 + &spr_read_generic, &spr_write_generic,
  1860 + 0x00000000);
  1861 + /* XXX : not implemented */
  1862 + spr_register(env, SPR_40x_IAC1, "IAC1",
  1863 + SPR_NOACCESS, SPR_NOACCESS,
  1864 + &spr_read_generic, &spr_write_generic,
  1865 + 0x00000000);
  1866 + spr_register(env, SPR_40x_IAC2, "IAC2",
  1867 + SPR_NOACCESS, SPR_NOACCESS,
  1868 + &spr_read_generic, &spr_write_generic,
  1869 + 0x00000000);
1805 /* MMU */ 1870 /* MMU */
  1871 + spr_register(env, SPR_40x_PID, "PID",
  1872 + SPR_NOACCESS, SPR_NOACCESS,
  1873 + &spr_read_generic, &spr_write_generic,
  1874 + 0x00000000);
1806 spr_register(env, SPR_403_PBL1, "PBL1", 1875 spr_register(env, SPR_403_PBL1, "PBL1",
1807 SPR_NOACCESS, SPR_NOACCESS, 1876 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_403_pbr, &spr_write_403_pbr, 1877 &spr_read_403_pbr, &spr_write_403_pbr,
@@ -1819,14 +1888,7 @@ static void gen_spr_403 (CPUPPCState *env) @@ -1819,14 +1888,7 @@ static void gen_spr_403 (CPUPPCState *env)
1819 SPR_NOACCESS, SPR_NOACCESS, 1888 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_403_pbr, &spr_write_403_pbr, 1889 &spr_read_403_pbr, &spr_write_403_pbr,
1821 0x00000000); 1890 0x00000000);
1822 - /* Debug */  
1823 - /* XXX : not implemented */  
1824 - spr_register(env, SPR_40x_DAC2, "DAC2",  
1825 - SPR_NOACCESS, SPR_NOACCESS,  
1826 - &spr_read_generic, &spr_write_generic,  
1827 - 0x00000000);  
1828 - /* XXX : not implemented */  
1829 - spr_register(env, SPR_40x_IAC2, "IAC2", 1891 + spr_register(env, SPR_40x_ZPR, "ZPR",
1830 SPR_NOACCESS, SPR_NOACCESS, 1892 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic, 1893 &spr_read_generic, &spr_write_generic,
1832 0x00000000); 1894 0x00000000);
@@ -1843,23 +1905,40 @@ static void gen_spr_compress (CPUPPCState *env) @@ -1843,23 +1905,40 @@ static void gen_spr_compress (CPUPPCState *env)
1843 } 1905 }
1844 #endif 1906 #endif
1845 1907
1846 -// XXX: TODO (64 bits PowerPC SPRs) 1908 +// XXX: TODO
1847 /* 1909 /*
1848 - * ASR => SPR 280 (64 bits)  
1849 - * FPECR => SPR 1022 (?)  
1850 - * VRSAVE => SPR 256 (Altivec)  
1851 - * SCOMC => SPR 276 (64 bits ?)  
1852 - * SCOMD => SPR 277 (64 bits ?)  
1853 - * HSPRG0 => SPR 304 (hypervisor)  
1854 - * HSPRG1 => SPR 305 (hypervisor)  
1855 - * HDEC => SPR 310 (hypervisor)  
1856 - * HIOR => SPR 311 (hypervisor)  
1857 - * RMOR => SPR 312 (970)  
1858 - * HRMOR => SPR 313 (hypervisor)  
1859 - * HSRR0 => SPR 314 (hypervisor)  
1860 - * HSRR1 => SPR 315 (hypervisor)  
1861 - * LPCR => SPR 316 (970)  
1862 - * LPIDR => SPR 317 (970) 1910 + * AMR => SPR 29 (Power 2.04)
  1911 + * CTRL => SPR 136 (Power 2.04)
  1912 + * CTRL => SPR 152 (Power 2.04)
  1913 + * VRSAVE => SPR 256 (Altivec)
  1914 + * SCOMC => SPR 276 (64 bits ?)
  1915 + * SCOMD => SPR 277 (64 bits ?)
  1916 + * ASR => SPR 280 (64 bits)
  1917 + * TBU40 => SPR 286 (Power 2.04 hypv)
  1918 + * HSPRG0 => SPR 304 (Power 2.04 hypv)
  1919 + * HSPRG1 => SPR 305 (Power 2.04 hypv)
  1920 + * HDSISR => SPR 306 (Power 2.04 hypv)
  1921 + * HDAR => SPR 307 (Power 2.04 hypv)
  1922 + * PURR => SPR 309 (Power 2.04 hypv)
  1923 + * HDEC => SPR 310 (Power 2.04 hypv)
  1924 + * HIOR => SPR 311 (hypv)
  1925 + * RMOR => SPR 312 (970)
  1926 + * HRMOR => SPR 313 (Power 2.04 hypv)
  1927 + * HSRR0 => SPR 314 (Power 2.04 hypv)
  1928 + * HSRR1 => SPR 315 (Power 2.04 hypv)
  1929 + * LPCR => SPR 316 (970)
  1930 + * LPIDR => SPR 317 (970)
  1931 + * SPEFSCR => SPR 512 (Power 2.04 emb)
  1932 + * ATBL => SPR 526 (Power 2.04 emb)
  1933 + * ATBU => SPR 527 (Power 2.04 emb)
  1934 + * EPR => SPR 702 (Power 2.04 emb)
  1935 + * perf => 768-783 (Power 2.04)
  1936 + * perf => 784-799 (Power 2.04)
  1937 + * PPR => SPR 896 (Power 2.04)
  1938 + * EPLC => SPR 947 (Power 2.04 emb)
  1939 + * EPSC => SPR 948 (Power 2.04 emb)
  1940 + * DABRX => 1015 (Power 2.04 hypv)
  1941 + * FPECR => SPR 1022 (?)
1863 * ... and more (thermal management, performance counters, ...) 1942 * ... and more (thermal management, performance counters, ...)
1864 */ 1943 */
1865 1944
@@ -1886,6 +1965,9 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) @@ -1886,6 +1965,9 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1886 /* Embedded PowerPC from IBM */ 1965 /* Embedded PowerPC from IBM */
1887 case CPU_PPC_401A1: /* 401 A1 family */ 1966 case CPU_PPC_401A1: /* 401 A1 family */
1888 case CPU_PPC_401B2: /* 401 B2 family */ 1967 case CPU_PPC_401B2: /* 401 B2 family */
  1968 +#if 0
  1969 + case CPU_PPC_401B3: /* 401 B3 family */
  1970 +#endif
1889 case CPU_PPC_401C2: /* 401 C2 family */ 1971 case CPU_PPC_401C2: /* 401 C2 family */
1890 case CPU_PPC_401D2: /* 401 D2 family */ 1972 case CPU_PPC_401D2: /* 401 D2 family */
1891 case CPU_PPC_401E2: /* 401 E2 family */ 1973 case CPU_PPC_401E2: /* 401 E2 family */
@@ -1896,6 +1978,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) @@ -1896,6 +1978,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1896 gen_spr_generic(env); 1978 gen_spr_generic(env);
1897 gen_spr_40x(env); 1979 gen_spr_40x(env);
1898 gen_spr_401_403(env); 1980 gen_spr_401_403(env);
  1981 + gen_spr_401(env);
1899 #if defined (TODO) 1982 #if defined (TODO)
1900 /* XXX: optional ? */ 1983 /* XXX: optional ? */
1901 gen_spr_compress(env); 1984 gen_spr_compress(env);
@@ -2413,7 +2496,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) @@ -2413,7 +2496,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
2413 #endif /* defined (TARGET_PPC64) */ 2496 #endif /* defined (TARGET_PPC64) */
2414 2497
2415 #if defined (TODO) 2498 #if defined (TODO)
2416 - /* POWER */ 2499 + /* POWER */
2417 case CPU_POWER: /* POWER */ 2500 case CPU_POWER: /* POWER */
2418 case CPU_POWER2: /* POWER2 */ 2501 case CPU_POWER2: /* POWER2 */
2419 break; 2502 break;
@@ -2460,7 +2543,7 @@ static void dump_sprs (CPUPPCState *env) @@ -2460,7 +2543,7 @@ static void dump_sprs (CPUPPCState *env)
2460 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; 2543 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2461 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; 2544 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2462 if (sw || sr || uw || ur) { 2545 if (sw || sr || uw || ur) {
2463 - printf("%4d (%03x) %8s s%c%c u%c%c\n", 2546 + printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
2464 (i << 5) | j, (i << 5) | j, spr->name, 2547 (i << 5) | j, (i << 5) | j, spr->name,
2465 sw ? 'w' : '-', sr ? 'r' : '-', 2548 sw ? 'w' : '-', sr ? 'r' : '-',
2466 uw ? 'w' : '-', ur ? 'r' : '-'); 2549 uw ? 'w' : '-', ur ? 'r' : '-');
@@ -2678,15 +2761,15 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) @@ -2678,15 +2761,15 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2678 if (opc1 != 0x00) { 2761 if (opc1 != 0x00) {
2679 if (opc->opc3 == 0xFF) { 2762 if (opc->opc3 == 0xFF) {
2680 if (opc->opc2 == 0xFF) { 2763 if (opc->opc2 == 0xFF) {
2681 - printf(" %02x -- -- (%2d ----) : %s\n", 2764 + printf("INSN: %02x -- -- (%02d ----) : %s\n",
2682 opc->opc1, opc->opc1, opc->oname); 2765 opc->opc1, opc->opc1, opc->oname);
2683 } else { 2766 } else {
2684 - printf(" %02x %02x -- (%2d %4d) : %s\n", 2767 + printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
2685 opc->opc1, opc->opc2, opc->opc1, opc->opc2, 2768 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2686 opc->oname); 2769 opc->oname);
2687 } 2770 }
2688 } else { 2771 } else {
2689 - printf(" %02x %02x %02x (%2d %4d) : %s\n", 2772 + printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
2690 opc->opc1, opc->opc2, opc->opc3, 2773 opc->opc1, opc->opc2, opc->opc3,
2691 opc->opc1, (opc->opc3 << 5) | opc->opc2, 2774 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2692 opc->oname); 2775 opc->oname);
@@ -2724,15 +2807,98 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def) @@ -2724,15 +2807,98 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2724 /* PowerPC CPU definitions */ 2807 /* PowerPC CPU definitions */
2725 static ppc_def_t ppc_defs[] = { 2808 static ppc_def_t ppc_defs[] = {
2726 /* Embedded PowerPC */ 2809 /* Embedded PowerPC */
2727 -#if defined (TODO)  
2728 - /* PowerPC 401 */ 2810 + /* Generic PowerPC 401 */
2729 { 2811 {
2730 .name = "401", 2812 .name = "401",
2731 .pvr = CPU_PPC_401, 2813 .pvr = CPU_PPC_401,
2732 - .pvr_mask = 0xFFFF0000, 2814 + .pvr_mask = 0xFFFFFFFF,
2733 .insns_flags = PPC_INSNS_401, 2815 .insns_flags = PPC_INSNS_401,
2734 .flags = PPC_FLAGS_401, 2816 .flags = PPC_FLAGS_401,
2735 - .msr_mask = xxx, 2817 + .msr_mask = 0x000FD201,
  2818 + },
  2819 + /* PowerPC 401A1 */
  2820 + {
  2821 + .name = "401a1",
  2822 + .pvr = CPU_PPC_401A1,
  2823 + .pvr_mask = 0xFFFFFFFF,
  2824 + .insns_flags = PPC_INSNS_401,
  2825 + .flags = PPC_FLAGS_401,
  2826 + .msr_mask = 0x000FD201,
  2827 + },
  2828 + /* PowerPC 401B2 */
  2829 + {
  2830 + .name = "401b2",
  2831 + .pvr = CPU_PPC_401B2,
  2832 + .pvr_mask = 0xFFFFFFFF,
  2833 + .insns_flags = PPC_INSNS_401,
  2834 + .flags = PPC_FLAGS_401,
  2835 + .msr_mask = 0x000FD201,
  2836 + },
  2837 +#if defined (TODO)
  2838 + /* PowerPC 401B3 */
  2839 + {
  2840 + .name = "401b3",
  2841 + .pvr = CPU_PPC_401B3,
  2842 + .pvr_mask = 0xFFFFFFFF,
  2843 + .insns_flags = PPC_INSNS_401,
  2844 + .flags = PPC_FLAGS_401,
  2845 + .msr_mask = 0x000FD201,
  2846 + },
  2847 +#endif
  2848 + /* PowerPC 401C2 */
  2849 + {
  2850 + .name = "401c2",
  2851 + .pvr = CPU_PPC_401C2,
  2852 + .pvr_mask = 0xFFFFFFFF,
  2853 + .insns_flags = PPC_INSNS_401,
  2854 + .flags = PPC_FLAGS_401,
  2855 + .msr_mask = 0x000FD201,
  2856 + },
  2857 + /* PowerPC 401D2 */
  2858 + {
  2859 + .name = "401d2",
  2860 + .pvr = CPU_PPC_401D2,
  2861 + .pvr_mask = 0xFFFFFFFF,
  2862 + .insns_flags = PPC_INSNS_401,
  2863 + .flags = PPC_FLAGS_401,
  2864 + .msr_mask = 0x000FD201,
  2865 + },
  2866 + /* PowerPC 401E2 */
  2867 + {
  2868 + .name = "401e2",
  2869 + .pvr = CPU_PPC_401E2,
  2870 + .pvr_mask = 0xFFFFFFFF,
  2871 + .insns_flags = PPC_INSNS_401,
  2872 + .flags = PPC_FLAGS_401,
  2873 + .msr_mask = 0x000FD201,
  2874 + },
  2875 + /* PowerPC 401F2 */
  2876 + {
  2877 + .name = "401f2",
  2878 + .pvr = CPU_PPC_401F2,
  2879 + .pvr_mask = 0xFFFFFFFF,
  2880 + .insns_flags = PPC_INSNS_401,
  2881 + .flags = PPC_FLAGS_401,
  2882 + .msr_mask = 0x000FD201,
  2883 + },
  2884 + /* PowerPC 401G2 */
  2885 + {
  2886 + .name = "401g2",
  2887 + .pvr = CPU_PPC_401G2,
  2888 + .pvr_mask = 0xFFFFFFFF,
  2889 + .insns_flags = PPC_INSNS_401,
  2890 + .flags = PPC_FLAGS_401,
  2891 + .msr_mask = 0x000FD201,
  2892 + },
  2893 +#if defined (TODO)
  2894 + /* PowerPC 401G2 */
  2895 + {
  2896 + .name = "401gf",
  2897 + .pvr = CPU_PPC_401GF,
  2898 + .pvr_mask = 0xFFFFFFFF,
  2899 + .insns_flags = PPC_INSNS_401,
  2900 + .flags = PPC_FLAGS_401,
  2901 + .msr_mask = 0x000FD201,
2736 }, 2902 },
2737 #endif 2903 #endif
2738 #if defined (TODO) 2904 #if defined (TODO)
@@ -2740,10 +2906,10 @@ static ppc_def_t ppc_defs[] = { @@ -2740,10 +2906,10 @@ static ppc_def_t ppc_defs[] = {
2740 { 2906 {
2741 .name = "iop480", 2907 .name = "iop480",
2742 .pvr = CPU_PPC_IOP480, 2908 .pvr = CPU_PPC_IOP480,
2743 - .pvr_mask = 0xFFFF0000, 2909 + .pvr_mask = 0xFFFFFFFF,
2744 .insns_flags = PPC_INSNS_401, 2910 .insns_flags = PPC_INSNS_401,
2745 .flags = PPC_FLAGS_401, 2911 .flags = PPC_FLAGS_401,
2746 - .msr_mask = xxx, 2912 + .msr_mask = 0x000FD201,
2747 }, 2913 },
2748 #endif 2914 #endif
2749 #if defined (TODO) 2915 #if defined (TODO)
@@ -2751,62 +2917,63 @@ static ppc_def_t ppc_defs[] = { @@ -2751,62 +2917,63 @@ static ppc_def_t ppc_defs[] = {
2751 { 2917 {
2752 .name = "Cobra", 2918 .name = "Cobra",
2753 .pvr = CPU_PPC_COBRA, 2919 .pvr = CPU_PPC_COBRA,
2754 - .pvr_mask = 0xFFFF0000, 2920 + .pvr_mask = 0xFFFFFFFF,
2755 .insns_flags = PPC_INSNS_401, 2921 .insns_flags = PPC_INSNS_401,
2756 .flags = PPC_FLAGS_401, 2922 .flags = PPC_FLAGS_401,
2757 - .msr_mask = xxx, 2923 + .msr_mask = 0x000FD201,
2758 }, 2924 },
2759 #endif 2925 #endif
2760 -#if defined (TODO)  
2761 /* Generic PowerPC 403 */ 2926 /* Generic PowerPC 403 */
2762 { 2927 {
2763 .name = "403", 2928 .name = "403",
2764 .pvr = CPU_PPC_403, 2929 .pvr = CPU_PPC_403,
2765 - .pvr_mask = 0xFFFFFF00, 2930 + .pvr_mask = 0xFFFFFFFF,
2766 .insns_flags = PPC_INSNS_403, 2931 .insns_flags = PPC_INSNS_403,
2767 .flags = PPC_FLAGS_403, 2932 .flags = PPC_FLAGS_403,
2768 .msr_mask = 0x000000000007D23DULL, 2933 .msr_mask = 0x000000000007D23DULL,
2769 }, 2934 },
2770 -#endif  
2771 -#if defined (TODO)  
2772 /* PowerPC 403 GA */ 2935 /* PowerPC 403 GA */
2773 { 2936 {
2774 .name = "403ga", 2937 .name = "403ga",
2775 .pvr = CPU_PPC_403GA, 2938 .pvr = CPU_PPC_403GA,
2776 - .pvr_mask = 0xFFFFFF00, 2939 + .pvr_mask = 0xFFFFFFFF,
2777 .insns_flags = PPC_INSNS_403, 2940 .insns_flags = PPC_INSNS_403,
2778 .flags = PPC_FLAGS_403, 2941 .flags = PPC_FLAGS_403,
2779 .msr_mask = 0x000000000007D23DULL, 2942 .msr_mask = 0x000000000007D23DULL,
2780 }, 2943 },
2781 -#endif  
2782 -#if defined (TODO)  
2783 /* PowerPC 403 GB */ 2944 /* PowerPC 403 GB */
2784 { 2945 {
2785 .name = "403gb", 2946 .name = "403gb",
2786 .pvr = CPU_PPC_403GB, 2947 .pvr = CPU_PPC_403GB,
2787 - .pvr_mask = 0xFFFFFF00, 2948 + .pvr_mask = 0xFFFFFFFF,
2788 .insns_flags = PPC_INSNS_403, 2949 .insns_flags = PPC_INSNS_403,
2789 .flags = PPC_FLAGS_403, 2950 .flags = PPC_FLAGS_403,
2790 .msr_mask = 0x000000000007D23DULL, 2951 .msr_mask = 0x000000000007D23DULL,
2791 }, 2952 },
2792 -#endif  
2793 -#if defined (TODO)  
2794 /* PowerPC 403 GC */ 2953 /* PowerPC 403 GC */
2795 { 2954 {
2796 .name = "403gc", 2955 .name = "403gc",
2797 .pvr = CPU_PPC_403GC, 2956 .pvr = CPU_PPC_403GC,
2798 - .pvr_mask = 0xFFFFFF00, 2957 + .pvr_mask = 0xFFFFFFFF,
2799 .insns_flags = PPC_INSNS_403, 2958 .insns_flags = PPC_INSNS_403,
2800 .flags = PPC_FLAGS_403, 2959 .flags = PPC_FLAGS_403,
2801 .msr_mask = 0x000000000007D23DULL, 2960 .msr_mask = 0x000000000007D23DULL,
2802 }, 2961 },
2803 -#endif  
2804 -#if defined (TODO)  
2805 /* PowerPC 403 GCX */ 2962 /* PowerPC 403 GCX */
2806 { 2963 {
2807 .name = "403gcx", 2964 .name = "403gcx",
2808 .pvr = CPU_PPC_403GCX, 2965 .pvr = CPU_PPC_403GCX,
2809 - .pvr_mask = 0xFFFFFF00, 2966 + .pvr_mask = 0xFFFFFFFF,
  2967 + .insns_flags = PPC_INSNS_403,
  2968 + .flags = PPC_FLAGS_403,
  2969 + .msr_mask = 0x000000000007D23DULL,
  2970 + },
  2971 +#if defined (TODO)
  2972 + /* PowerPC 403 GP */
  2973 + {
  2974 + .name = "403gp",
  2975 + .pvr = CPU_PPC_403GP,
  2976 + .pvr_mask = 0xFFFFFFFF,
2810 .insns_flags = PPC_INSNS_403, 2977 .insns_flags = PPC_INSNS_403,
2811 .flags = PPC_FLAGS_403, 2978 .flags = PPC_FLAGS_403,
2812 .msr_mask = 0x000000000007D23DULL, 2979 .msr_mask = 0x000000000007D23DULL,
@@ -2816,45 +2983,27 @@ static ppc_def_t ppc_defs[] = { @@ -2816,45 +2983,27 @@ static ppc_def_t ppc_defs[] = {
2816 { 2983 {
2817 .name = "405", 2984 .name = "405",
2818 .pvr = CPU_PPC_405, 2985 .pvr = CPU_PPC_405,
2819 - .pvr_mask = 0xFFFF0000,  
2820 - .insns_flags = PPC_INSNS_405,  
2821 - .flags = PPC_FLAGS_405,  
2822 - .msr_mask = 0x00000000020EFF30ULL,  
2823 - },  
2824 - /* PowerPC 405 CR */  
2825 - {  
2826 - .name = "405cr",  
2827 - .pvr = CPU_PPC_405,  
2828 .pvr_mask = 0xFFFFFFFF, 2986 .pvr_mask = 0xFFFFFFFF,
2829 .insns_flags = PPC_INSNS_405, 2987 .insns_flags = PPC_INSNS_405,
2830 .flags = PPC_FLAGS_405, 2988 .flags = PPC_FLAGS_405,
2831 .msr_mask = 0x00000000020EFF30ULL, 2989 .msr_mask = 0x00000000020EFF30ULL,
2832 }, 2990 },
2833 #if defined (TODO) 2991 #if defined (TODO)
2834 - /* PowerPC 405 GP */ 2992 + /* PowerPC 405 A3 */
2835 { 2993 {
2836 - .name = "405gp",  
2837 - .pvr = CPU_PPC_405, 2994 + .name = "405a3",
  2995 + .pvr = CPU_PPC_405A3,
2838 .pvr_mask = 0xFFFFFFFF, 2996 .pvr_mask = 0xFFFFFFFF,
2839 .insns_flags = PPC_INSNS_405, 2997 .insns_flags = PPC_INSNS_405,
2840 .flags = PPC_FLAGS_405, 2998 .flags = PPC_FLAGS_405,
2841 .msr_mask = 0x00000000020EFF30ULL, 2999 .msr_mask = 0x00000000020EFF30ULL,
2842 }, 3000 },
2843 #endif 3001 #endif
2844 - /* PowerPC 405 EP */  
2845 - {  
2846 - .name = "405ep",  
2847 - .pvr = CPU_PPC_405EP,  
2848 - .pvr_mask = 0xFFFFFFFF,  
2849 - .insns_flags = PPC_INSNS_405,  
2850 - .flags = PPC_FLAGS_405,  
2851 - .msr_mask = 0x00000000000ED630ULL,  
2852 - },  
2853 #if defined (TODO) 3002 #if defined (TODO)
2854 - /* PowerPC 405 EZ */ 3003 + /* PowerPC 405 A4 */
2855 { 3004 {
2856 - .name = "405ez",  
2857 - .pvr = CPU_PPC_405EZ, 3005 + .name = "405a4",
  3006 + .pvr = CPU_PPC_405A4,
2858 .pvr_mask = 0xFFFFFFFF, 3007 .pvr_mask = 0xFFFFFFFF,
2859 .insns_flags = PPC_INSNS_405, 3008 .insns_flags = PPC_INSNS_405,
2860 .flags = PPC_FLAGS_405, 3009 .flags = PPC_FLAGS_405,
@@ -2862,10 +3011,10 @@ static ppc_def_t ppc_defs[] = { @@ -2862,10 +3011,10 @@ static ppc_def_t ppc_defs[] = {
2862 }, 3011 },
2863 #endif 3012 #endif
2864 #if defined (TODO) 3013 #if defined (TODO)
2865 - /* PowerPC 405 GPR */ 3014 + /* PowerPC 405 B3 */
2866 { 3015 {
2867 - .name = "405gpr",  
2868 - .pvr = CPU_PPC_405GPR, 3016 + .name = "405b3",
  3017 + .pvr = CPU_PPC_405B3,
2869 .pvr_mask = 0xFFFFFFFF, 3018 .pvr_mask = 0xFFFFFFFF,
2870 .insns_flags = PPC_INSNS_405, 3019 .insns_flags = PPC_INSNS_405,
2871 .flags = PPC_FLAGS_405, 3020 .flags = PPC_FLAGS_405,
@@ -2890,41 +3039,117 @@ static ppc_def_t ppc_defs[] = { @@ -2890,41 +3039,117 @@ static ppc_def_t ppc_defs[] = {
2890 .flags = PPC_FLAGS_405, 3039 .flags = PPC_FLAGS_405,
2891 .msr_mask = 0x00000000020EFF30ULL, 3040 .msr_mask = 0x00000000020EFF30ULL,
2892 }, 3041 },
2893 -#if defined (TODO)  
2894 - /* Npe405 H */ 3042 + /* PowerPC 405 CR */
2895 { 3043 {
2896 - .name = "Npe405H",  
2897 - .pvr = CPU_PPC_NPE405H, 3044 + .name = "405cr",
  3045 + .pvr = CPU_PPC_405CR,
2898 .pvr_mask = 0xFFFFFFFF, 3046 .pvr_mask = 0xFFFFFFFF,
2899 .insns_flags = PPC_INSNS_405, 3047 .insns_flags = PPC_INSNS_405,
2900 .flags = PPC_FLAGS_405, 3048 .flags = PPC_FLAGS_405,
2901 .msr_mask = 0x00000000020EFF30ULL, 3049 .msr_mask = 0x00000000020EFF30ULL,
2902 }, 3050 },
2903 -#endif  
2904 -#if defined (TODO)  
2905 - /* Npe405 L */ 3051 + /* PowerPC 405 GP */
2906 { 3052 {
2907 - .name = "Npe405L",  
2908 - .pvr = CPU_PPC_NPE405L, 3053 + .name = "405gp",
  3054 + .pvr = CPU_PPC_405GP,
2909 .pvr_mask = 0xFFFFFFFF, 3055 .pvr_mask = 0xFFFFFFFF,
2910 .insns_flags = PPC_INSNS_405, 3056 .insns_flags = PPC_INSNS_405,
2911 .flags = PPC_FLAGS_405, 3057 .flags = PPC_FLAGS_405,
2912 .msr_mask = 0x00000000020EFF30ULL, 3058 .msr_mask = 0x00000000020EFF30ULL,
2913 }, 3059 },
2914 -#endif  
2915 -#if defined (TODO)  
2916 - /* STB010000 */ 3060 + /* PowerPC 405 EP */
2917 { 3061 {
2918 - .name = "STB01000",  
2919 - .pvr = CPU_PPC_STB01000, 3062 + .name = "405ep",
  3063 + .pvr = CPU_PPC_405EP,
2920 .pvr_mask = 0xFFFFFFFF, 3064 .pvr_mask = 0xFFFFFFFF,
2921 .insns_flags = PPC_INSNS_405, 3065 .insns_flags = PPC_INSNS_405,
2922 .flags = PPC_FLAGS_405, 3066 .flags = PPC_FLAGS_405,
2923 - .msr_mask = 0x00000000020EFF30ULL, 3067 + .msr_mask = 0x00000000000ED630ULL,
2924 }, 3068 },
2925 -#endif  
2926 #if defined (TODO) 3069 #if defined (TODO)
2927 - /* STB01010 */ 3070 + /* PowerPC 405 EZ */
  3071 + {
  3072 + .name = "405ez",
  3073 + .pvr = CPU_PPC_405EZ,
  3074 + .pvr_mask = 0xFFFFFFFF,
  3075 + .insns_flags = PPC_INSNS_405,
  3076 + .flags = PPC_FLAGS_405,
  3077 + .msr_mask = 0x00000000020EFF30ULL,
  3078 + },
  3079 +#endif
  3080 +#if defined (TODO)
  3081 + /* PowerPC 405 GPR */
  3082 + {
  3083 + .name = "405gpr",
  3084 + .pvr = CPU_PPC_405GPR,
  3085 + .pvr_mask = 0xFFFFFFFF,
  3086 + .insns_flags = PPC_INSNS_405,
  3087 + .flags = PPC_FLAGS_405,
  3088 + .msr_mask = 0x00000000020EFF30ULL,
  3089 + },
  3090 +#endif
  3091 +#if defined (TODO)
  3092 + /* PowerPC 405 LP */
  3093 + {
  3094 + .name = "405lp",
  3095 + .pvr = CPU_PPC_405EZ,
  3096 + .pvr_mask = 0xFFFFFFFF,
  3097 + .insns_flags = PPC_INSNS_405,
  3098 + .flags = PPC_FLAGS_405,
  3099 + .msr_mask = 0x00000000020EFF30ULL,
  3100 + },
  3101 +#endif
  3102 + /* Npe405 H */
  3103 + {
  3104 + .name = "Npe405H",
  3105 + .pvr = CPU_PPC_NPE405H,
  3106 + .pvr_mask = 0xFFFFFFFF,
  3107 + .insns_flags = PPC_INSNS_405,
  3108 + .flags = PPC_FLAGS_405,
  3109 + .msr_mask = 0x00000000020EFF30ULL,
  3110 + },
  3111 + /* Npe405 H2 */
  3112 + {
  3113 + .name = "Npe405H2",
  3114 + .pvr = CPU_PPC_NPE405H2,
  3115 + .pvr_mask = 0xFFFFFFFF,
  3116 + .insns_flags = PPC_INSNS_405,
  3117 + .flags = PPC_FLAGS_405,
  3118 + .msr_mask = 0x00000000020EFF30ULL,
  3119 + },
  3120 + /* Npe405 L */
  3121 + {
  3122 + .name = "Npe405L",
  3123 + .pvr = CPU_PPC_NPE405L,
  3124 + .pvr_mask = 0xFFFFFFFF,
  3125 + .insns_flags = PPC_INSNS_405,
  3126 + .flags = PPC_FLAGS_405,
  3127 + .msr_mask = 0x00000000020EFF30ULL,
  3128 + },
  3129 +#if defined (TODO)
  3130 + /* PowerPC LP777000 */
  3131 + {
  3132 + .name = "lp777000",
  3133 + .pvr = CPU_PPC_LP777000,
  3134 + .pvr_mask = 0xFFFFFFFF,
  3135 + .insns_flags = PPC_INSNS_405,
  3136 + .flags = PPC_FLAGS_405,
  3137 + .msr_mask = 0x00000000020EFF30ULL,
  3138 + },
  3139 +#endif
  3140 +#if defined (TODO)
  3141 + /* STB010000 */
  3142 + {
  3143 + .name = "STB01000",
  3144 + .pvr = CPU_PPC_STB01000,
  3145 + .pvr_mask = 0xFFFFFFFF,
  3146 + .insns_flags = PPC_INSNS_405,
  3147 + .flags = PPC_FLAGS_405,
  3148 + .msr_mask = 0x00000000020EFF30ULL,
  3149 + },
  3150 +#endif
  3151 +#if defined (TODO)
  3152 + /* STB01010 */
2928 { 3153 {
2929 .name = "STB01010", 3154 .name = "STB01010",
2930 .pvr = CPU_PPC_STB01010, 3155 .pvr = CPU_PPC_STB01010,
@@ -2978,7 +3203,7 @@ static ppc_def_t ppc_defs[] = { @@ -2978,7 +3203,7 @@ static ppc_def_t ppc_defs[] = {
2978 .msr_mask = 0x00000000020EFF30ULL, 3203 .msr_mask = 0x00000000020EFF30ULL,
2979 }, 3204 },
2980 #endif 3205 #endif
2981 -#if defined (TODO) 3206 +#if defined (TODO) || 1
2982 /* STB25xx */ 3207 /* STB25xx */
2983 { 3208 {
2984 .name = "STB25", 3209 .name = "STB25",
@@ -3035,105 +3260,98 @@ static ppc_def_t ppc_defs[] = { @@ -3035,105 +3260,98 @@ static ppc_def_t ppc_defs[] = {
3035 .msr_mask = 0x00000000020EFF30ULL, 3260 .msr_mask = 0x00000000020EFF30ULL,
3036 }, 3261 },
3037 #endif 3262 #endif
3038 -#if defined (TODO)  
3039 /* PowerPC 440 EP */ 3263 /* PowerPC 440 EP */
3040 { 3264 {
3041 .name = "440ep", 3265 .name = "440ep",
3042 .pvr = CPU_PPC_440EP, 3266 .pvr = CPU_PPC_440EP,
3043 - .pvr_mask = 0xFFFF0000, 3267 + .pvr_mask = 0xFFFFFFFF,
3044 .insns_flags = PPC_INSNS_440, 3268 .insns_flags = PPC_INSNS_440,
3045 .flags = PPC_FLAGS_440, 3269 .flags = PPC_FLAGS_440,
3046 .msr_mask = 0x000000000006D630ULL, 3270 .msr_mask = 0x000000000006D630ULL,
3047 }, 3271 },
3048 -#endif  
3049 -#if defined (TODO)  
3050 /* PowerPC 440 GR */ 3272 /* PowerPC 440 GR */
3051 { 3273 {
3052 .name = "440gr", 3274 .name = "440gr",
3053 .pvr = CPU_PPC_440GR, 3275 .pvr = CPU_PPC_440GR,
3054 - .pvr_mask = 0xFFFF0000, 3276 + .pvr_mask = 0xFFFFFFFF,
3055 .insns_flags = PPC_INSNS_440, 3277 .insns_flags = PPC_INSNS_440,
3056 .flags = PPC_FLAGS_440, 3278 .flags = PPC_FLAGS_440,
3057 .msr_mask = 0x000000000006D630ULL, 3279 .msr_mask = 0x000000000006D630ULL,
3058 }, 3280 },
3059 -#endif  
3060 -#if defined (TODO)  
3061 /* PowerPC 440 GP */ 3281 /* PowerPC 440 GP */
3062 { 3282 {
3063 .name = "440gp", 3283 .name = "440gp",
3064 .pvr = CPU_PPC_440GP, 3284 .pvr = CPU_PPC_440GP,
3065 - .pvr_mask = 0xFFFFFF00, 3285 + .pvr_mask = 0xFFFFFFFF,
3066 .insns_flags = PPC_INSNS_440, 3286 .insns_flags = PPC_INSNS_440,
3067 .flags = PPC_FLAGS_440, 3287 .flags = PPC_FLAGS_440,
3068 .msr_mask = 0x000000000006D630ULL, 3288 .msr_mask = 0x000000000006D630ULL,
3069 }, 3289 },
3070 -#endif  
3071 #if defined (TODO) 3290 #if defined (TODO)
  3291 + /* PowerPC 440 GRX */
  3292 + {
  3293 + .name = "440grx",
  3294 + .pvr = CPU_PPC_440GRX,
  3295 + .pvr_mask = 0xFFFFFFFF,
  3296 + .insns_flags = PPC_INSNS_440,
  3297 + .flags = PPC_FLAGS_440,
  3298 + .msr_mask = 0x000000000006D630ULL,
  3299 + },
  3300 +#endif
3072 /* PowerPC 440 GX */ 3301 /* PowerPC 440 GX */
3073 { 3302 {
3074 .name = "440gx", 3303 .name = "440gx",
3075 .pvr = CPU_PPC_440GX, 3304 .pvr = CPU_PPC_440GX,
3076 - .pvr_mask = 0xFFFF0000,  
3077 - .insns_flags = PPC_INSNS_405, 3305 + .pvr_mask = 0xFFFFFFFF,
  3306 + .insns_flags = PPC_INSNS_440,
3078 .flags = PPC_FLAGS_440, 3307 .flags = PPC_FLAGS_440,
3079 .msr_mask = 0x000000000006D630ULL, 3308 .msr_mask = 0x000000000006D630ULL,
3080 }, 3309 },
3081 -#endif  
3082 -#if defined (TODO)  
3083 /* PowerPC 440 GXc */ 3310 /* PowerPC 440 GXc */
3084 { 3311 {
3085 .name = "440gxc", 3312 .name = "440gxc",
3086 - .pvr = CPU_PPC_440GXC,  
3087 - .pvr_mask = 0xFFFF0000,  
3088 - .insns_flags = PPC_INSNS_405, 3313 + .pvr = CPU_PPC_440GXc,
  3314 + .pvr_mask = 0xFFFFFFFF,
  3315 + .insns_flags = PPC_INSNS_440,
3089 .flags = PPC_FLAGS_440, 3316 .flags = PPC_FLAGS_440,
3090 .msr_mask = 0x000000000006D630ULL, 3317 .msr_mask = 0x000000000006D630ULL,
3091 }, 3318 },
3092 -#endif  
3093 -#if defined (TODO)  
3094 /* PowerPC 440 GXf */ 3319 /* PowerPC 440 GXf */
3095 { 3320 {
3096 .name = "440gxf", 3321 .name = "440gxf",
3097 - .pvr = CPU_PPC_440GXF,  
3098 - .pvr_mask = 0xFFFF0000,  
3099 - .insns_flags = PPC_INSNS_405, 3322 + .pvr = CPU_PPC_440GXf,
  3323 + .pvr_mask = 0xFFFFFFFF,
  3324 + .insns_flags = PPC_INSNS_440,
3100 .flags = PPC_FLAGS_440, 3325 .flags = PPC_FLAGS_440,
3101 .msr_mask = 0x000000000006D630ULL, 3326 .msr_mask = 0x000000000006D630ULL,
3102 }, 3327 },
3103 -#endif  
3104 -#if defined (TODO)  
3105 /* PowerPC 440 SP */ 3328 /* PowerPC 440 SP */
3106 { 3329 {
3107 .name = "440sp", 3330 .name = "440sp",
3108 .pvr = CPU_PPC_440SP, 3331 .pvr = CPU_PPC_440SP,
3109 - .pvr_mask = 0xFFFF0000,  
3110 - .insns_flags = PPC_INSNS_405, 3332 + .pvr_mask = 0xFFFFFFFF,
  3333 + .insns_flags = PPC_INSNS_440,
3111 .flags = PPC_FLAGS_440, 3334 .flags = PPC_FLAGS_440,
3112 .msr_mask = 0x000000000006D630ULL, 3335 .msr_mask = 0x000000000006D630ULL,
3113 }, 3336 },
3114 -#endif  
3115 -#if defined (TODO)  
3116 /* PowerPC 440 SP2 */ 3337 /* PowerPC 440 SP2 */
3117 { 3338 {
3118 .name = "440sp2", 3339 .name = "440sp2",
3119 .pvr = CPU_PPC_440SP2, 3340 .pvr = CPU_PPC_440SP2,
3120 - .pvr_mask = 0xFFFF0000,  
3121 - .insns_flags = PPC_INSNS_405, 3341 + .pvr_mask = 0xFFFFFFFF,
  3342 + .insns_flags = PPC_INSNS_440,
3122 .flags = PPC_FLAGS_440, 3343 .flags = PPC_FLAGS_440,
3123 .msr_mask = 0x000000000006D630ULL, 3344 .msr_mask = 0x000000000006D630ULL,
3124 }, 3345 },
3125 -#endif  
3126 -#if defined (TODO)  
3127 /* PowerPC 440 SPE */ 3346 /* PowerPC 440 SPE */
3128 { 3347 {
3129 .name = "440spe", 3348 .name = "440spe",
3130 .pvr = CPU_PPC_440SPE, 3349 .pvr = CPU_PPC_440SPE,
3131 - .pvr_mask = 0xFFFF0000,  
3132 - .insns_flags = PPC_INSNS_405, 3350 + .pvr_mask = 0xFFFFFFFF,
  3351 + .insns_flags = PPC_INSNS_440,
3133 .flags = PPC_FLAGS_440, 3352 .flags = PPC_FLAGS_440,
3134 .msr_mask = 0x000000000006D630ULL, 3353 .msr_mask = 0x000000000006D630ULL,
3135 }, 3354 },
3136 -#endif  
3137 /* Fake generic BookE PowerPC */ 3355 /* Fake generic BookE PowerPC */
3138 { 3356 {
3139 .name = "BookE", 3357 .name = "BookE",
@@ -3157,7 +3375,7 @@ static ppc_def_t ppc_defs[] = { @@ -3157,7 +3375,7 @@ static ppc_def_t ppc_defs[] = {
3157 { 3375 {
3158 .name = "601", 3376 .name = "601",
3159 .pvr = CPU_PPC_601, 3377 .pvr = CPU_PPC_601,
3160 - .pvr_mask = 0xFFFF0000, 3378 + .pvr_mask = 0xFFFFFFFF,
3161 .insns_flags = PPC_INSNS_601, 3379 .insns_flags = PPC_INSNS_601,
3162 .flags = PPC_FLAGS_601, 3380 .flags = PPC_FLAGS_601,
3163 .msr_mask = 0x000000000000FD70ULL, 3381 .msr_mask = 0x000000000000FD70ULL,
@@ -3168,7 +3386,7 @@ static ppc_def_t ppc_defs[] = { @@ -3168,7 +3386,7 @@ static ppc_def_t ppc_defs[] = {
3168 { 3386 {
3169 .name = "602", 3387 .name = "602",
3170 .pvr = CPU_PPC_602, 3388 .pvr = CPU_PPC_602,
3171 - .pvr_mask = 0xFFFF0000, 3389 + .pvr_mask = 0xFFFFFFFF,
3172 .insns_flags = PPC_INSNS_602, 3390 .insns_flags = PPC_INSNS_602,
3173 .flags = PPC_FLAGS_602, 3391 .flags = PPC_FLAGS_602,
3174 .msr_mask = 0x0000000000C7FF73ULL, 3392 .msr_mask = 0x0000000000C7FF73ULL,
@@ -3258,7 +3476,7 @@ static ppc_def_t ppc_defs[] = { @@ -3258,7 +3476,7 @@ static ppc_def_t ppc_defs[] = {
3258 { 3476 {
3259 .name = "G2", 3477 .name = "G2",
3260 .pvr = CPU_PPC_G2, 3478 .pvr = CPU_PPC_G2,
3261 - .pvr_mask = 0xFFFF0000, 3479 + .pvr_mask = 0xFFFFFFFF,
3262 .insns_flags = PPC_INSNS_G2, 3480 .insns_flags = PPC_INSNS_G2,
3263 .flags = PPC_FLAGS_G2, 3481 .flags = PPC_FLAGS_G2,
3264 .msr_mask = 0x000000000006FFF2ULL, 3482 .msr_mask = 0x000000000006FFF2ULL,
@@ -3266,7 +3484,7 @@ static ppc_def_t ppc_defs[] = { @@ -3266,7 +3484,7 @@ static ppc_def_t ppc_defs[] = {
3266 { 3484 {
3267 .name = "G2h4", 3485 .name = "G2h4",
3268 .pvr = CPU_PPC_G2H4, 3486 .pvr = CPU_PPC_G2H4,
3269 - .pvr_mask = 0xFFFF0000, 3487 + .pvr_mask = 0xFFFFFFFF,
3270 .insns_flags = PPC_INSNS_G2, 3488 .insns_flags = PPC_INSNS_G2,
3271 .flags = PPC_FLAGS_G2, 3489 .flags = PPC_FLAGS_G2,
3272 .msr_mask = 0x000000000006FFF2ULL, 3490 .msr_mask = 0x000000000006FFF2ULL,
@@ -3274,7 +3492,7 @@ static ppc_def_t ppc_defs[] = { @@ -3274,7 +3492,7 @@ static ppc_def_t ppc_defs[] = {
3274 { 3492 {
3275 .name = "G2gp", 3493 .name = "G2gp",
3276 .pvr = CPU_PPC_G2gp, 3494 .pvr = CPU_PPC_G2gp,
3277 - .pvr_mask = 0xFFFF0000, 3495 + .pvr_mask = 0xFFFFFFFF,
3278 .insns_flags = PPC_INSNS_G2, 3496 .insns_flags = PPC_INSNS_G2,
3279 .flags = PPC_FLAGS_G2, 3497 .flags = PPC_FLAGS_G2,
3280 .msr_mask = 0x000000000006FFF2ULL, 3498 .msr_mask = 0x000000000006FFF2ULL,
@@ -3282,7 +3500,7 @@ static ppc_def_t ppc_defs[] = { @@ -3282,7 +3500,7 @@ static ppc_def_t ppc_defs[] = {
3282 { 3500 {
3283 .name = "G2ls", 3501 .name = "G2ls",
3284 .pvr = CPU_PPC_G2ls, 3502 .pvr = CPU_PPC_G2ls,
3285 - .pvr_mask = 0xFFFF0000, 3503 + .pvr_mask = 0xFFFFFFFF,
3286 .insns_flags = PPC_INSNS_G2, 3504 .insns_flags = PPC_INSNS_G2,
3287 .flags = PPC_FLAGS_G2, 3505 .flags = PPC_FLAGS_G2,
3288 .msr_mask = 0x000000000006FFF2ULL, 3506 .msr_mask = 0x000000000006FFF2ULL,
@@ -3290,7 +3508,7 @@ static ppc_def_t ppc_defs[] = { @@ -3290,7 +3508,7 @@ static ppc_def_t ppc_defs[] = {
3290 { /* Same as G2, with LE mode support */ 3508 { /* Same as G2, with LE mode support */
3291 .name = "G2le", 3509 .name = "G2le",
3292 .pvr = CPU_PPC_G2LE, 3510 .pvr = CPU_PPC_G2LE,
3293 - .pvr_mask = 0xFFFF0000, 3511 + .pvr_mask = 0xFFFFFFFF,
3294 .insns_flags = PPC_INSNS_G2, 3512 .insns_flags = PPC_INSNS_G2,
3295 .flags = PPC_FLAGS_G2, 3513 .flags = PPC_FLAGS_G2,
3296 .msr_mask = 0x000000000007FFF3ULL, 3514 .msr_mask = 0x000000000007FFF3ULL,
@@ -3298,7 +3516,7 @@ static ppc_def_t ppc_defs[] = { @@ -3298,7 +3516,7 @@ static ppc_def_t ppc_defs[] = {
3298 { 3516 {
3299 .name = "G2legp", 3517 .name = "G2legp",
3300 .pvr = CPU_PPC_G2LEgp, 3518 .pvr = CPU_PPC_G2LEgp,
3301 - .pvr_mask = 0xFFFF0000, 3519 + .pvr_mask = 0xFFFFFFFF,
3302 .insns_flags = PPC_INSNS_G2, 3520 .insns_flags = PPC_INSNS_G2,
3303 .flags = PPC_FLAGS_G2, 3521 .flags = PPC_FLAGS_G2,
3304 .msr_mask = 0x000000000007FFF3ULL, 3522 .msr_mask = 0x000000000007FFF3ULL,
@@ -3306,7 +3524,7 @@ static ppc_def_t ppc_defs[] = { @@ -3306,7 +3524,7 @@ static ppc_def_t ppc_defs[] = {
3306 { 3524 {
3307 .name = "G2lels", 3525 .name = "G2lels",
3308 .pvr = CPU_PPC_G2LEls, 3526 .pvr = CPU_PPC_G2LEls,
3309 - .pvr_mask = 0xFFFF0000, 3527 + .pvr_mask = 0xFFFFFFFF,
3310 .insns_flags = PPC_INSNS_G2, 3528 .insns_flags = PPC_INSNS_G2,
3311 .flags = PPC_FLAGS_G2, 3529 .flags = PPC_FLAGS_G2,
3312 .msr_mask = 0x000000000007FFF3ULL, 3530 .msr_mask = 0x000000000007FFF3ULL,
@@ -3365,45 +3583,15 @@ static ppc_def_t ppc_defs[] = { @@ -3365,45 +3583,15 @@ static ppc_def_t ppc_defs[] = {
3365 .flags = PPC_FLAGS_7x0, 3583 .flags = PPC_FLAGS_7x0,
3366 .msr_mask = 0x000000000007FF77ULL, 3584 .msr_mask = 0x000000000007FF77ULL,
3367 }, 3585 },
3368 -#if defined (TODO)  
3369 - /* MPC745 (G3) */  
3370 - {  
3371 - .name = "745",  
3372 - .pvr = CPU_PPC_74x,  
3373 - .pvr_mask = 0xFFFFF000,  
3374 - .insns_flags = PPC_INSNS_7x5,  
3375 - .flags = PPC_FLAGS_7x5,  
3376 - .msr_mask = 0x000000000007FF77ULL,  
3377 - },  
3378 - {  
3379 - .name = "Goldfinger",  
3380 - .pvr = CPU_PPC_74x,  
3381 - .pvr_mask = 0xFFFFF000,  
3382 - .insns_flags = PPC_INSNS_7x5,  
3383 - .flags = PPC_FLAGS_7x5,  
3384 - .msr_mask = 0x000000000007FF77ULL,  
3385 - },  
3386 -#endif  
3387 - /* MPC750 (G3) */ 3586 + /* 740E (G3) */
3388 { 3587 {
3389 - .name = "750",  
3390 - .pvr = CPU_PPC_74x, 3588 + .name = "740e",
  3589 + .pvr = CPU_PPC_740E,
3391 .pvr_mask = 0xFFFFFFFF, 3590 .pvr_mask = 0xFFFFFFFF,
3392 .insns_flags = PPC_INSNS_7x0, 3591 .insns_flags = PPC_INSNS_7x0,
3393 .flags = PPC_FLAGS_7x0, 3592 .flags = PPC_FLAGS_7x0,
3394 .msr_mask = 0x000000000007FF77ULL, 3593 .msr_mask = 0x000000000007FF77ULL,
3395 }, 3594 },
3396 -#if defined (TODO)  
3397 - /* MPC755 (G3) */  
3398 - {  
3399 - .name = "755",  
3400 - .pvr = CPU_PPC_755,  
3401 - .pvr_mask = 0xFFFFF000,  
3402 - .insns_flags = PPC_INSNS_7x5,  
3403 - .flags = PPC_FLAGS_7x5,  
3404 - .msr_mask = 0x000000000007FF77ULL,  
3405 - },  
3406 -#endif  
3407 /* MPC740P (G3) */ 3595 /* MPC740P (G3) */
3408 { 3596 {
3409 .name = "740p", 3597 .name = "740p",
@@ -3422,16 +3610,44 @@ static ppc_def_t ppc_defs[] = { @@ -3422,16 +3610,44 @@ static ppc_def_t ppc_defs[] = {
3422 .msr_mask = 0x000000000007FF77ULL, 3610 .msr_mask = 0x000000000007FF77ULL,
3423 }, 3611 },
3424 #if defined (TODO) 3612 #if defined (TODO)
  3613 + /* MPC745 (G3) */
  3614 + {
  3615 + .name = "745",
  3616 + .pvr = CPU_PPC_74x,
  3617 + .pvr_mask = 0xFFFFFFFF,
  3618 + .insns_flags = PPC_INSNS_7x5,
  3619 + .flags = PPC_FLAGS_7x5,
  3620 + .msr_mask = 0x000000000007FF77ULL,
  3621 + },
  3622 + {
  3623 + .name = "Goldfinger",
  3624 + .pvr = CPU_PPC_74x,
  3625 + .pvr_mask = 0xFFFFFFFF,
  3626 + .insns_flags = PPC_INSNS_7x5,
  3627 + .flags = PPC_FLAGS_7x5,
  3628 + .msr_mask = 0x000000000007FF77ULL,
  3629 + },
  3630 +#endif
  3631 +#if defined (TODO)
3425 /* MPC745P (G3) */ 3632 /* MPC745P (G3) */
3426 { 3633 {
3427 .name = "745p", 3634 .name = "745p",
3428 .pvr = CPU_PPC_74xP, 3635 .pvr = CPU_PPC_74xP,
3429 - .pvr_mask = 0xFFFFF000, 3636 + .pvr_mask = 0xFFFFFFFF,
3430 .insns_flags = PPC_INSNS_7x5, 3637 .insns_flags = PPC_INSNS_7x5,
3431 .flags = PPC_FLAGS_7x5, 3638 .flags = PPC_FLAGS_7x5,
3432 .msr_mask = 0x000000000007FF77ULL, 3639 .msr_mask = 0x000000000007FF77ULL,
3433 }, 3640 },
3434 #endif 3641 #endif
  3642 + /* MPC750 (G3) */
  3643 + {
  3644 + .name = "750",
  3645 + .pvr = CPU_PPC_74x,
  3646 + .pvr_mask = 0xFFFFFFFF,
  3647 + .insns_flags = PPC_INSNS_7x0,
  3648 + .flags = PPC_FLAGS_7x0,
  3649 + .msr_mask = 0x000000000007FF77ULL,
  3650 + },
3435 /* MPC750P (G3) */ 3651 /* MPC750P (G3) */
3436 { 3652 {
3437 .name = "750p", 3653 .name = "750p",
@@ -3441,17 +3657,15 @@ static ppc_def_t ppc_defs[] = { @@ -3441,17 +3657,15 @@ static ppc_def_t ppc_defs[] = {
3441 .flags = PPC_FLAGS_7x0, 3657 .flags = PPC_FLAGS_7x0,
3442 .msr_mask = 0x000000000007FF77ULL, 3658 .msr_mask = 0x000000000007FF77ULL,
3443 }, 3659 },
3444 -#if defined (TODO)  
3445 - /* MPC755P (G3) */ 3660 + /* 750E (G3) */
3446 { 3661 {
3447 - .name = "755p",  
3448 - .pvr = CPU_PPC_74xP,  
3449 - .pvr_mask = 0xFFFFF000,  
3450 - .insns_flags = PPC_INSNS_7x5,  
3451 - .flags = PPC_FLAGS_7x5, 3662 + .name = "750e",
  3663 + .pvr = CPU_PPC_750E,
  3664 + .pvr_mask = 0xFFFFFFFF,
  3665 + .insns_flags = PPC_INSNS_7x0,
  3666 + .flags = PPC_FLAGS_7x0,
3452 .msr_mask = 0x000000000007FF77ULL, 3667 .msr_mask = 0x000000000007FF77ULL,
3453 }, 3668 },
3454 -#endif  
3455 /* IBM 750CXe (G3 embedded) */ 3669 /* IBM 750CXe (G3 embedded) */
3456 { 3670 {
3457 .name = "750cxe", 3671 .name = "750cxe",
@@ -3461,6 +3675,15 @@ static ppc_def_t ppc_defs[] = { @@ -3461,6 +3675,15 @@ static ppc_def_t ppc_defs[] = {
3461 .flags = PPC_FLAGS_7x0, 3675 .flags = PPC_FLAGS_7x0,
3462 .msr_mask = 0x000000000007FF77ULL, 3676 .msr_mask = 0x000000000007FF77ULL,
3463 }, 3677 },
  3678 + /* IBM 750CXr (G3 embedded) */
  3679 + {
  3680 + .name = "750cxr",
  3681 + .pvr = CPU_PPC_750CXR,
  3682 + .pvr_mask = 0xFFFFFFFF,
  3683 + .insns_flags = PPC_INSNS_7x0,
  3684 + .flags = PPC_FLAGS_7x0,
  3685 + .msr_mask = 0x000000000007FF77ULL,
  3686 + },
3464 /* IBM 750FX (G3 embedded) */ 3687 /* IBM 750FX (G3 embedded) */
3465 { 3688 {
3466 .name = "750fx", 3689 .name = "750fx",
@@ -3470,6 +3693,15 @@ static ppc_def_t ppc_defs[] = { @@ -3470,6 +3693,15 @@ static ppc_def_t ppc_defs[] = {
3470 .flags = PPC_FLAGS_7x0, 3693 .flags = PPC_FLAGS_7x0,
3471 .msr_mask = 0x000000000007FF77ULL, 3694 .msr_mask = 0x000000000007FF77ULL,
3472 }, 3695 },
  3696 + /* IBM 750FL (G3 embedded) */
  3697 + {
  3698 + .name = "750fl",
  3699 + .pvr = CPU_PPC_750FL,
  3700 + .pvr_mask = 0xFFFFFFFF,
  3701 + .insns_flags = PPC_INSNS_7x0,
  3702 + .flags = PPC_FLAGS_7x0,
  3703 + .msr_mask = 0x000000000007FF77ULL,
  3704 + },
3473 /* IBM 750GX (G3 embedded) */ 3705 /* IBM 750GX (G3 embedded) */
3474 { 3706 {
3475 .name = "750gx", 3707 .name = "750gx",
@@ -3479,12 +3711,74 @@ static ppc_def_t ppc_defs[] = { @@ -3479,12 +3711,74 @@ static ppc_def_t ppc_defs[] = {
3479 .flags = PPC_FLAGS_7x0, 3711 .flags = PPC_FLAGS_7x0,
3480 .msr_mask = 0x000000000007FF77ULL, 3712 .msr_mask = 0x000000000007FF77ULL,
3481 }, 3713 },
  3714 + /* IBM 750L (G3 embedded) */
  3715 + {
  3716 + .name = "750l",
  3717 + .pvr = CPU_PPC_750L,
  3718 + .pvr_mask = 0xFFFFFFFF,
  3719 + .insns_flags = PPC_INSNS_7x0,
  3720 + .flags = PPC_FLAGS_7x0,
  3721 + .msr_mask = 0x000000000007FF77ULL,
  3722 + },
  3723 + /* IBM 750CL (G3 embedded) */
  3724 + {
  3725 + .name = "750cl",
  3726 + .pvr = CPU_PPC_750CL,
  3727 + .pvr_mask = 0xFFFFFFFF,
  3728 + .insns_flags = PPC_INSNS_7x0,
  3729 + .flags = PPC_FLAGS_7x0,
  3730 + .msr_mask = 0x000000000007FF77ULL,
  3731 + },
  3732 +#if defined (TODO)
  3733 + /* MPC755 (G3) */
  3734 + {
  3735 + .name = "755",
  3736 + .pvr = CPU_PPC_755,
  3737 + .pvr_mask = 0xFFFFFFFF,
  3738 + .insns_flags = PPC_INSNS_7x5,
  3739 + .flags = PPC_FLAGS_7x5,
  3740 + .msr_mask = 0x000000000007FF77ULL,
  3741 + },
  3742 +#endif
  3743 +#if defined (TODO)
  3744 + /* MPC755D (G3) */
  3745 + {
  3746 + .name = "755d",
  3747 + .pvr = CPU_PPC_755D,
  3748 + .pvr_mask = 0xFFFFFFFF,
  3749 + .insns_flags = PPC_INSNS_7x5,
  3750 + .flags = PPC_FLAGS_7x5,
  3751 + .msr_mask = 0x000000000007FF77ULL,
  3752 + },
  3753 +#endif
  3754 +#if defined (TODO)
  3755 + /* MPC755E (G3) */
  3756 + {
  3757 + .name = "755e",
  3758 + .pvr = CPU_PPC_755E,
  3759 + .pvr_mask = 0xFFFFFFFF,
  3760 + .insns_flags = PPC_INSNS_7x5,
  3761 + .flags = PPC_FLAGS_7x5,
  3762 + .msr_mask = 0x000000000007FF77ULL,
  3763 + },
  3764 +#endif
  3765 +#if defined (TODO)
  3766 + /* MPC755P (G3) */
  3767 + {
  3768 + .name = "755p",
  3769 + .pvr = CPU_PPC_74xP,
  3770 + .pvr_mask = 0xFFFFFFFF,
  3771 + .insns_flags = PPC_INSNS_7x5,
  3772 + .flags = PPC_FLAGS_7x5,
  3773 + .msr_mask = 0x000000000007FF77ULL,
  3774 + },
  3775 +#endif
3482 #if defined (TODO) 3776 #if defined (TODO)
3483 /* generic G4 */ 3777 /* generic G4 */
3484 { 3778 {
3485 .name = "G4", 3779 .name = "G4",
3486 .pvr = CPU_PPC_7400, 3780 .pvr = CPU_PPC_7400,
3487 - .pvr_mask = 0xFFFF0000, 3781 + .pvr_mask = 0xFFFFFFFF,
3488 .insns_flags = PPC_INSNS_74xx, 3782 .insns_flags = PPC_INSNS_74xx,
3489 .flags = PPC_FLAGS_74xx, 3783 .flags = PPC_FLAGS_74xx,
3490 .msr_mask = 0x000000000205FF77ULL, 3784 .msr_mask = 0x000000000205FF77ULL,
@@ -3495,7 +3789,7 @@ static ppc_def_t ppc_defs[] = { @@ -3495,7 +3789,7 @@ static ppc_def_t ppc_defs[] = {
3495 { 3789 {
3496 .name = "7400", 3790 .name = "7400",
3497 .pvr = CPU_PPC_7400, 3791 .pvr = CPU_PPC_7400,
3498 - .pvr_mask = 0xFFFF0000, 3792 + .pvr_mask = 0xFFFFFFFF,
3499 .insns_flags = PPC_INSNS_74xx, 3793 .insns_flags = PPC_INSNS_74xx,
3500 .flags = PPC_FLAGS_74xx, 3794 .flags = PPC_FLAGS_74xx,
3501 .msr_mask = 0x000000000205FF77ULL, 3795 .msr_mask = 0x000000000205FF77ULL,
@@ -3503,7 +3797,7 @@ static ppc_def_t ppc_defs[] = { @@ -3503,7 +3797,7 @@ static ppc_def_t ppc_defs[] = {
3503 { 3797 {
3504 .name = "Max", 3798 .name = "Max",
3505 .pvr = CPU_PPC_7400, 3799 .pvr = CPU_PPC_7400,
3506 - .pvr_mask = 0xFFFF0000, 3800 + .pvr_mask = 0xFFFFFFFF,
3507 .insns_flags = PPC_INSNS_74xx, 3801 .insns_flags = PPC_INSNS_74xx,
3508 .flags = PPC_FLAGS_74xx, 3802 .flags = PPC_FLAGS_74xx,
3509 .msr_mask = 0x000000000205FF77ULL, 3803 .msr_mask = 0x000000000205FF77ULL,
@@ -3514,7 +3808,7 @@ static ppc_def_t ppc_defs[] = { @@ -3514,7 +3808,7 @@ static ppc_def_t ppc_defs[] = {
3514 { 3808 {
3515 .name = "7410", 3809 .name = "7410",
3516 .pvr = CPU_PPC_7410, 3810 .pvr = CPU_PPC_7410,
3517 - .pvr_mask = 0xFFFF0000, 3811 + .pvr_mask = 0xFFFFFFFF,
3518 .insns_flags = PPC_INSNS_74xx, 3812 .insns_flags = PPC_INSNS_74xx,
3519 .flags = PPC_FLAGS_74xx, 3813 .flags = PPC_FLAGS_74xx,
3520 .msr_mask = 0x000000000205FF77ULL, 3814 .msr_mask = 0x000000000205FF77ULL,
@@ -3522,22 +3816,73 @@ static ppc_def_t ppc_defs[] = { @@ -3522,22 +3816,73 @@ static ppc_def_t ppc_defs[] = {
3522 { 3816 {
3523 .name = "Nitro", 3817 .name = "Nitro",
3524 .pvr = CPU_PPC_7410, 3818 .pvr = CPU_PPC_7410,
3525 - .pvr_mask = 0xFFFF0000, 3819 + .pvr_mask = 0xFFFFFFFF,
  3820 + .insns_flags = PPC_INSNS_74xx,
  3821 + .flags = PPC_FLAGS_74xx,
  3822 + .msr_mask = 0x000000000205FF77ULL,
  3823 + },
  3824 +#endif
  3825 +#if defined (TODO)
  3826 + /* PowerPC 7441 (G4) */
  3827 + {
  3828 + .name = "7441",
  3829 + .pvr = CPU_PPC_7441,
  3830 + .pvr_mask = 0xFFFFFFFF,
  3831 + .insns_flags = PPC_INSNS_74xx,
  3832 + .flags = PPC_FLAGS_74xx,
  3833 + .msr_mask = 0x000000000205FF77ULL,
  3834 + },
  3835 +#endif
  3836 +#if defined (TODO)
  3837 + /* PowerPC 7445 (G4) */
  3838 + {
  3839 + .name = "7445",
  3840 + .pvr = CPU_PPC_7445,
  3841 + .pvr_mask = 0xFFFFFFFF,
  3842 + .insns_flags = PPC_INSNS_74xx,
  3843 + .flags = PPC_FLAGS_74xx,
  3844 + .msr_mask = 0x000000000205FF77ULL,
  3845 + },
  3846 +#endif
  3847 +#if defined (TODO)
  3848 + /* PowerPC 7447 (G4) */
  3849 + {
  3850 + .name = "7447",
  3851 + .pvr = CPU_PPC_7447,
  3852 + .pvr_mask = 0xFFFFFFFF,
  3853 + .insns_flags = PPC_INSNS_74xx,
  3854 + .flags = PPC_FLAGS_74xx,
  3855 + .msr_mask = 0x000000000205FF77ULL,
  3856 + },
  3857 +#endif
  3858 +#if defined (TODO)
  3859 + /* PowerPC 7447A (G4) */
  3860 + {
  3861 + .name = "7447A",
  3862 + .pvr = CPU_PPC_7447A,
  3863 + .pvr_mask = 0xFFFFFFFF,
  3864 + .insns_flags = PPC_INSNS_74xx,
  3865 + .flags = PPC_FLAGS_74xx,
  3866 + .msr_mask = 0x000000000205FF77ULL,
  3867 + },
  3868 +#endif
  3869 +#if defined (TODO)
  3870 + /* PowerPC 7448 (G4) */
  3871 + {
  3872 + .name = "7448",
  3873 + .pvr = CPU_PPC_7448,
  3874 + .pvr_mask = 0xFFFFFFFF,
3526 .insns_flags = PPC_INSNS_74xx, 3875 .insns_flags = PPC_INSNS_74xx,
3527 .flags = PPC_FLAGS_74xx, 3876 .flags = PPC_FLAGS_74xx,
3528 .msr_mask = 0x000000000205FF77ULL, 3877 .msr_mask = 0x000000000205FF77ULL,
3529 }, 3878 },
3530 #endif 3879 #endif
3531 - /* XXX: 7441 */  
3532 - /* XXX: 7445 */  
3533 - /* XXX: 7447 */  
3534 - /* XXX: 7447A */  
3535 #if defined (TODO) 3880 #if defined (TODO)
3536 /* PowerPC 7450 (G4) */ 3881 /* PowerPC 7450 (G4) */
3537 { 3882 {
3538 .name = "7450", 3883 .name = "7450",
3539 .pvr = CPU_PPC_7450, 3884 .pvr = CPU_PPC_7450,
3540 - .pvr_mask = 0xFFFF0000, 3885 + .pvr_mask = 0xFFFFFFFF,
3541 .insns_flags = PPC_INSNS_74xx, 3886 .insns_flags = PPC_INSNS_74xx,
3542 .flags = PPC_FLAGS_74xx, 3887 .flags = PPC_FLAGS_74xx,
3543 .msr_mask = 0x000000000205FF77ULL, 3888 .msr_mask = 0x000000000205FF77ULL,
@@ -3545,19 +3890,51 @@ static ppc_def_t ppc_defs[] = { @@ -3545,19 +3890,51 @@ static ppc_def_t ppc_defs[] = {
3545 { 3890 {
3546 .name = "Vger", 3891 .name = "Vger",
3547 .pvr = CPU_PPC_7450, 3892 .pvr = CPU_PPC_7450,
3548 - .pvr_mask = 0xFFFF0000, 3893 + .pvr_mask = 0xFFFFFFFF,
  3894 + .insns_flags = PPC_INSNS_74xx,
  3895 + .flags = PPC_FLAGS_74xx,
  3896 + .msr_mask = 0x000000000205FF77ULL,
  3897 + },
  3898 +#endif
  3899 +#if defined (TODO)
  3900 + /* PowerPC 7450b (G4) */
  3901 + {
  3902 + .name = "7450b",
  3903 + .pvr = CPU_PPC_7450B,
  3904 + .pvr_mask = 0xFFFFFFFF,
  3905 + .insns_flags = PPC_INSNS_74xx,
  3906 + .flags = PPC_FLAGS_74xx,
  3907 + .msr_mask = 0x000000000205FF77ULL,
  3908 + },
  3909 +#endif
  3910 +#if defined (TODO)
  3911 + /* PowerPC 7451 (G4) */
  3912 + {
  3913 + .name = "7451",
  3914 + .pvr = CPU_PPC_7451,
  3915 + .pvr_mask = 0xFFFFFFFF,
  3916 + .insns_flags = PPC_INSNS_74xx,
  3917 + .flags = PPC_FLAGS_74xx,
  3918 + .msr_mask = 0x000000000205FF77ULL,
  3919 + },
  3920 +#endif
  3921 +#if defined (TODO)
  3922 + /* PowerPC 7451g (G4) */
  3923 + {
  3924 + .name = "7451g",
  3925 + .pvr = CPU_PPC_7451G,
  3926 + .pvr_mask = 0xFFFFFFFF,
3549 .insns_flags = PPC_INSNS_74xx, 3927 .insns_flags = PPC_INSNS_74xx,
3550 .flags = PPC_FLAGS_74xx, 3928 .flags = PPC_FLAGS_74xx,
3551 .msr_mask = 0x000000000205FF77ULL, 3929 .msr_mask = 0x000000000205FF77ULL,
3552 }, 3930 },
3553 #endif 3931 #endif
3554 - /* XXX: 7451 */  
3555 #if defined (TODO) 3932 #if defined (TODO)
3556 /* PowerPC 7455 (G4) */ 3933 /* PowerPC 7455 (G4) */
3557 { 3934 {
3558 .name = "7455", 3935 .name = "7455",
3559 .pvr = CPU_PPC_7455, 3936 .pvr = CPU_PPC_7455,
3560 - .pvr_mask = 0xFFFF0000, 3937 + .pvr_mask = 0xFFFFFFFF,
3561 .insns_flags = PPC_INSNS_74xx, 3938 .insns_flags = PPC_INSNS_74xx,
3562 .flags = PPC_FLAGS_74xx, 3939 .flags = PPC_FLAGS_74xx,
3563 .msr_mask = 0x000000000205FF77ULL, 3940 .msr_mask = 0x000000000205FF77ULL,
@@ -3565,7 +3942,29 @@ static ppc_def_t ppc_defs[] = { @@ -3565,7 +3942,29 @@ static ppc_def_t ppc_defs[] = {
3565 { 3942 {
3566 .name = "Apollo 6", 3943 .name = "Apollo 6",
3567 .pvr = CPU_PPC_7455, 3944 .pvr = CPU_PPC_7455,
3568 - .pvr_mask = 0xFFFF0000, 3945 + .pvr_mask = 0xFFFFFFFF,
  3946 + .insns_flags = PPC_INSNS_74xx,
  3947 + .flags = PPC_FLAGS_74xx,
  3948 + .msr_mask = 0x000000000205FF77ULL,
  3949 + },
  3950 +#endif
  3951 +#if defined (TODO)
  3952 + /* PowerPC 7455F (G4) */
  3953 + {
  3954 + .name = "7455f",
  3955 + .pvr = CPU_PPC_7455F,
  3956 + .pvr_mask = 0xFFFFFFFF,
  3957 + .insns_flags = PPC_INSNS_74xx,
  3958 + .flags = PPC_FLAGS_74xx,
  3959 + .msr_mask = 0x000000000205FF77ULL,
  3960 + },
  3961 +#endif
  3962 +#if defined (TODO)
  3963 + /* PowerPC 7455G (G4) */
  3964 + {
  3965 + .name = "7455g",
  3966 + .pvr = CPU_PPC_7455G,
  3967 + .pvr_mask = 0xFFFFFFFF,
3569 .insns_flags = PPC_INSNS_74xx, 3968 .insns_flags = PPC_INSNS_74xx,
3570 .flags = PPC_FLAGS_74xx, 3969 .flags = PPC_FLAGS_74xx,
3571 .msr_mask = 0x000000000205FF77ULL, 3970 .msr_mask = 0x000000000205FF77ULL,
@@ -3576,7 +3975,7 @@ static ppc_def_t ppc_defs[] = { @@ -3576,7 +3975,7 @@ static ppc_def_t ppc_defs[] = {
3576 { 3975 {
3577 .name = "7457", 3976 .name = "7457",
3578 .pvr = CPU_PPC_7457, 3977 .pvr = CPU_PPC_7457,
3579 - .pvr_mask = 0xFFFF0000, 3978 + .pvr_mask = 0xFFFFFFFF,
3580 .insns_flags = PPC_INSNS_74xx, 3979 .insns_flags = PPC_INSNS_74xx,
3581 .flags = PPC_FLAGS_74xx, 3980 .flags = PPC_FLAGS_74xx,
3582 .msr_mask = 0x000000000205FF77ULL, 3981 .msr_mask = 0x000000000205FF77ULL,
@@ -3584,7 +3983,7 @@ static ppc_def_t ppc_defs[] = { @@ -3584,7 +3983,7 @@ static ppc_def_t ppc_defs[] = {
3584 { 3983 {
3585 .name = "Apollo 7", 3984 .name = "Apollo 7",
3586 .pvr = CPU_PPC_7457, 3985 .pvr = CPU_PPC_7457,
3587 - .pvr_mask = 0xFFFF0000, 3986 + .pvr_mask = 0xFFFFFFFF,
3588 .insns_flags = PPC_INSNS_74xx, 3987 .insns_flags = PPC_INSNS_74xx,
3589 .flags = PPC_FLAGS_74xx, 3988 .flags = PPC_FLAGS_74xx,
3590 .msr_mask = 0x000000000205FF77ULL, 3989 .msr_mask = 0x000000000205FF77ULL,
@@ -3595,7 +3994,7 @@ static ppc_def_t ppc_defs[] = { @@ -3595,7 +3994,7 @@ static ppc_def_t ppc_defs[] = {
3595 { 3994 {
3596 .name = "7457A", 3995 .name = "7457A",
3597 .pvr = CPU_PPC_7457A, 3996 .pvr = CPU_PPC_7457A,
3598 - .pvr_mask = 0xFFFF0000, 3997 + .pvr_mask = 0xFFFFFFFF,
3599 .insns_flags = PPC_INSNS_74xx, 3998 .insns_flags = PPC_INSNS_74xx,
3600 .flags = PPC_FLAGS_74xx, 3999 .flags = PPC_FLAGS_74xx,
3601 .msr_mask = 0x000000000205FF77ULL, 4000 .msr_mask = 0x000000000205FF77ULL,
@@ -3603,7 +4002,18 @@ static ppc_def_t ppc_defs[] = { @@ -3603,7 +4002,18 @@ static ppc_def_t ppc_defs[] = {
3603 { 4002 {
3604 .name = "Apollo 7 PM", 4003 .name = "Apollo 7 PM",
3605 .pvr = CPU_PPC_7457A, 4004 .pvr = CPU_PPC_7457A,
3606 - .pvr_mask = 0xFFFF0000, 4005 + .pvr_mask = 0xFFFFFFFF,
  4006 + .insns_flags = PPC_INSNS_74xx,
  4007 + .flags = PPC_FLAGS_74xx,
  4008 + .msr_mask = 0x000000000205FF77ULL,
  4009 + },
  4010 +#endif
  4011 +#if defined (TODO)
  4012 + /* PowerPC 7457C (G4) */
  4013 + {
  4014 + .name = "7457c",
  4015 + .pvr = CPU_PPC_7457C,
  4016 + .pvr_mask = 0xFFFFFFFF,
3607 .insns_flags = PPC_INSNS_74xx, 4017 .insns_flags = PPC_INSNS_74xx,
3608 .flags = PPC_FLAGS_74xx, 4018 .flags = PPC_FLAGS_74xx,
3609 .msr_mask = 0x000000000205FF77ULL, 4019 .msr_mask = 0x000000000205FF77ULL,
@@ -3616,7 +4026,7 @@ static ppc_def_t ppc_defs[] = { @@ -3616,7 +4026,7 @@ static ppc_def_t ppc_defs[] = {
3616 { 4026 {
3617 .name = "620", 4027 .name = "620",
3618 .pvr = CPU_PPC_620, 4028 .pvr = CPU_PPC_620,
3619 - .pvr_mask = 0xFFFF0000, 4029 + .pvr_mask = 0xFFFFFFFF,
3620 .insns_flags = PPC_INSNS_620, 4030 .insns_flags = PPC_INSNS_620,
3621 .flags = PPC_FLAGS_620, 4031 .flags = PPC_FLAGS_620,
3622 .msr_mask = 0x800000000005FF73ULL, 4032 .msr_mask = 0x800000000005FF73ULL,
@@ -3627,7 +4037,7 @@ static ppc_def_t ppc_defs[] = { @@ -3627,7 +4037,7 @@ static ppc_def_t ppc_defs[] = {
3627 { 4037 {
3628 .name = "630", 4038 .name = "630",
3629 .pvr = CPU_PPC_630, 4039 .pvr = CPU_PPC_630,
3630 - .pvr_mask = 0xFFFF0000, 4040 + .pvr_mask = 0xFFFFFFFF,
3631 .insns_flags = PPC_INSNS_630, 4041 .insns_flags = PPC_INSNS_630,
3632 .flags = PPC_FLAGS_630, 4042 .flags = PPC_FLAGS_630,
3633 .msr_mask = xxx, 4043 .msr_mask = xxx,
@@ -3635,7 +4045,7 @@ static ppc_def_t ppc_defs[] = { @@ -3635,7 +4045,7 @@ static ppc_def_t ppc_defs[] = {
3635 { 4045 {
3636 .name = "POWER3", 4046 .name = "POWER3",
3637 .pvr = CPU_PPC_630, 4047 .pvr = CPU_PPC_630,
3638 - .pvr_mask = 0xFFFF0000, 4048 + .pvr_mask = 0xFFFFFFFF,
3639 .insns_flags = PPC_INSNS_630, 4049 .insns_flags = PPC_INSNS_630,
3640 .flags = PPC_FLAGS_630, 4050 .flags = PPC_FLAGS_630,
3641 .msr_mask = xxx, 4051 .msr_mask = xxx,
@@ -3646,7 +4056,7 @@ static ppc_def_t ppc_defs[] = { @@ -3646,7 +4056,7 @@ static ppc_def_t ppc_defs[] = {
3646 { 4056 {
3647 .name = "631", 4057 .name = "631",
3648 .pvr = CPU_PPC_631, 4058 .pvr = CPU_PPC_631,
3649 - .pvr_mask = 0xFFFF0000, 4059 + .pvr_mask = 0xFFFFFFFF,
3650 .insns_flags = PPC_INSNS_631, 4060 .insns_flags = PPC_INSNS_631,
3651 .flags = PPC_FLAGS_631, 4061 .flags = PPC_FLAGS_631,
3652 .msr_mask = xxx, 4062 .msr_mask = xxx,
@@ -3654,7 +4064,7 @@ static ppc_def_t ppc_defs[] = { @@ -3654,7 +4064,7 @@ static ppc_def_t ppc_defs[] = {
3654 { 4064 {
3655 .name = "POWER3+", 4065 .name = "POWER3+",
3656 .pvr = CPU_PPC_631, 4066 .pvr = CPU_PPC_631,
3657 - .pvr_mask = 0xFFFF0000, 4067 + .pvr_mask = 0xFFFFFFFF,
3658 .insns_flags = PPC_INSNS_631, 4068 .insns_flags = PPC_INSNS_631,
3659 .flags = PPC_FLAGS_631, 4069 .flags = PPC_FLAGS_631,
3660 .msr_mask = xxx, 4070 .msr_mask = xxx,
@@ -3665,7 +4075,7 @@ static ppc_def_t ppc_defs[] = { @@ -3665,7 +4075,7 @@ static ppc_def_t ppc_defs[] = {
3665 { 4075 {
3666 .name = "POWER4", 4076 .name = "POWER4",
3667 .pvr = CPU_PPC_POWER4, 4077 .pvr = CPU_PPC_POWER4,
3668 - .pvr_mask = 0xFFFF0000, 4078 + .pvr_mask = 0xFFFFFFFF,
3669 .insns_flags = PPC_INSNS_POWER4, 4079 .insns_flags = PPC_INSNS_POWER4,
3670 .flags = PPC_FLAGS_POWER4, 4080 .flags = PPC_FLAGS_POWER4,
3671 .msr_mask = xxx, 4081 .msr_mask = xxx,
@@ -3676,7 +4086,7 @@ static ppc_def_t ppc_defs[] = { @@ -3676,7 +4086,7 @@ static ppc_def_t ppc_defs[] = {
3676 { 4086 {
3677 .name = "POWER4+", 4087 .name = "POWER4+",
3678 .pvr = CPU_PPC_POWER4P, 4088 .pvr = CPU_PPC_POWER4P,
3679 - .pvr_mask = 0xFFFF0000, 4089 + .pvr_mask = 0xFFFFFFFF,
3680 .insns_flags = PPC_INSNS_POWER4, 4090 .insns_flags = PPC_INSNS_POWER4,
3681 .flags = PPC_FLAGS_POWER4, 4091 .flags = PPC_FLAGS_POWER4,
3682 .msr_mask = xxx, 4092 .msr_mask = xxx,
@@ -3687,7 +4097,7 @@ static ppc_def_t ppc_defs[] = { @@ -3687,7 +4097,7 @@ static ppc_def_t ppc_defs[] = {
3687 { 4097 {
3688 .name = "POWER5", 4098 .name = "POWER5",
3689 .pvr = CPU_PPC_POWER5, 4099 .pvr = CPU_PPC_POWER5,
3690 - .pvr_mask = 0xFFFF0000, 4100 + .pvr_mask = 0xFFFFFFFF,
3691 .insns_flags = PPC_INSNS_POWER5, 4101 .insns_flags = PPC_INSNS_POWER5,
3692 .flags = PPC_FLAGS_POWER5, 4102 .flags = PPC_FLAGS_POWER5,
3693 .msr_mask = xxx, 4103 .msr_mask = xxx,
@@ -3698,18 +4108,29 @@ static ppc_def_t ppc_defs[] = { @@ -3698,18 +4108,29 @@ static ppc_def_t ppc_defs[] = {
3698 { 4108 {
3699 .name = "POWER5+", 4109 .name = "POWER5+",
3700 .pvr = CPU_PPC_POWER5P, 4110 .pvr = CPU_PPC_POWER5P,
3701 - .pvr_mask = 0xFFFF0000, 4111 + .pvr_mask = 0xFFFFFFFF,
3702 .insns_flags = PPC_INSNS_POWER5, 4112 .insns_flags = PPC_INSNS_POWER5,
3703 .flags = PPC_FLAGS_POWER5, 4113 .flags = PPC_FLAGS_POWER5,
3704 .msr_mask = xxx, 4114 .msr_mask = xxx,
3705 }, 4115 },
3706 #endif 4116 #endif
3707 #if defined (TODO) 4117 #if defined (TODO)
  4118 + /* POWER6 */
  4119 + {
  4120 + .name = "POWER6",
  4121 + .pvr = CPU_PPC_POWER6,
  4122 + .pvr_mask = 0xFFFFFFFF,
  4123 + .insns_flags = PPC_INSNS_POWER6,
  4124 + .flags = PPC_FLAGS_POWER6,
  4125 + .msr_mask = xxx,
  4126 + },
  4127 +#endif
  4128 +#if defined (TODO)
3708 /* PowerPC 970 */ 4129 /* PowerPC 970 */
3709 { 4130 {
3710 .name = "970", 4131 .name = "970",
3711 .pvr = CPU_PPC_970, 4132 .pvr = CPU_PPC_970,
3712 - .pvr_mask = 0xFFFF0000, 4133 + .pvr_mask = 0xFFFFFFFF,
3713 .insns_flags = PPC_INSNS_970, 4134 .insns_flags = PPC_INSNS_970,
3714 .flags = PPC_FLAGS_970, 4135 .flags = PPC_FLAGS_970,
3715 .msr_mask = 0x900000000204FF36ULL, 4136 .msr_mask = 0x900000000204FF36ULL,
@@ -3720,13 +4141,35 @@ static ppc_def_t ppc_defs[] = { @@ -3720,13 +4141,35 @@ static ppc_def_t ppc_defs[] = {
3720 { 4141 {
3721 .name = "970fx", 4142 .name = "970fx",
3722 .pvr = CPU_PPC_970FX, 4143 .pvr = CPU_PPC_970FX,
3723 - .pvr_mask = 0xFFFF0000, 4144 + .pvr_mask = 0xFFFFFFFF,
3724 .insns_flags = PPC_INSNS_970FX, 4145 .insns_flags = PPC_INSNS_970FX,
3725 .flags = PPC_FLAGS_970FX, 4146 .flags = PPC_FLAGS_970FX,
3726 .msr_mask = 0x800000000204FF36ULL, 4147 .msr_mask = 0x800000000204FF36ULL,
3727 }, 4148 },
3728 #endif 4149 #endif
3729 #if defined (TODO) 4150 #if defined (TODO)
  4151 + /* PowerPC 970MP */
  4152 + {
  4153 + .name = "970MP",
  4154 + .pvr = CPU_PPC_970MP,
  4155 + .pvr_mask = 0xFFFFFFFF,
  4156 + .insns_flags = PPC_INSNS_970,
  4157 + .flags = PPC_FLAGS_970,
  4158 + .msr_mask = 0x900000000204FF36ULL,
  4159 + },
  4160 +#endif
  4161 +#if defined (TODO)
  4162 + /* PowerPC Cell */
  4163 + {
  4164 + .name = "Cell",
  4165 + .pvr = CPU_PPC_CELL,
  4166 + .pvr_mask = 0xFFFFFFFF,
  4167 + .insns_flags = PPC_INSNS_970,
  4168 + .flags = PPC_FLAGS_970,
  4169 + .msr_mask = 0x900000000204FF36ULL,
  4170 + },
  4171 +#endif
  4172 +#if defined (TODO)
3730 /* RS64 (Apache/A35) */ 4173 /* RS64 (Apache/A35) */
3731 /* This one seems to support the whole POWER2 instruction set 4174 /* This one seems to support the whole POWER2 instruction set
3732 * and the PowerPC 64 one. 4175 * and the PowerPC 64 one.
@@ -3734,7 +4177,7 @@ static ppc_def_t ppc_defs[] = { @@ -3734,7 +4177,7 @@ static ppc_def_t ppc_defs[] = {
3734 { 4177 {
3735 .name = "RS64", 4178 .name = "RS64",
3736 .pvr = CPU_PPC_RS64, 4179 .pvr = CPU_PPC_RS64,
3737 - .pvr_mask = 0xFFFF0000, 4180 + .pvr_mask = 0xFFFFFFFF,
3738 .insns_flags = PPC_INSNS_RS64, 4181 .insns_flags = PPC_INSNS_RS64,
3739 .flags = PPC_FLAGS_RS64, 4182 .flags = PPC_FLAGS_RS64,
3740 .msr_mask = xxx, 4183 .msr_mask = xxx,
@@ -3742,7 +4185,7 @@ static ppc_def_t ppc_defs[] = { @@ -3742,7 +4185,7 @@ static ppc_def_t ppc_defs[] = {
3742 { 4185 {
3743 .name = "Apache", 4186 .name = "Apache",
3744 .pvr = CPU_PPC_RS64, 4187 .pvr = CPU_PPC_RS64,
3745 - .pvr_mask = 0xFFFF0000, 4188 + .pvr_mask = 0xFFFFFFFF,
3746 .insns_flags = PPC_INSNS_RS64, 4189 .insns_flags = PPC_INSNS_RS64,
3747 .flags = PPC_FLAGS_RS64, 4190 .flags = PPC_FLAGS_RS64,
3748 .msr_mask = xxx, 4191 .msr_mask = xxx,
@@ -3750,7 +4193,7 @@ static ppc_def_t ppc_defs[] = { @@ -3750,7 +4193,7 @@ static ppc_def_t ppc_defs[] = {
3750 { 4193 {
3751 .name = "A35", 4194 .name = "A35",
3752 .pvr = CPU_PPC_RS64, 4195 .pvr = CPU_PPC_RS64,
3753 - .pvr_mask = 0xFFFF0000, 4196 + .pvr_mask = 0xFFFFFFFF,
3754 .insns_flags = PPC_INSNS_RS64, 4197 .insns_flags = PPC_INSNS_RS64,
3755 .flags = PPC_FLAGS_RS64, 4198 .flags = PPC_FLAGS_RS64,
3756 .msr_mask = xxx, 4199 .msr_mask = xxx,
@@ -3761,7 +4204,7 @@ static ppc_def_t ppc_defs[] = { @@ -3761,7 +4204,7 @@ static ppc_def_t ppc_defs[] = {
3761 { 4204 {
3762 .name = "RS64-II", 4205 .name = "RS64-II",
3763 .pvr = CPU_PPC_RS64II, 4206 .pvr = CPU_PPC_RS64II,
3764 - .pvr_mask = 0xFFFF0000, 4207 + .pvr_mask = 0xFFFFFFFF,
3765 .insns_flags = PPC_INSNS_RS64, 4208 .insns_flags = PPC_INSNS_RS64,
3766 .flags = PPC_FLAGS_RS64, 4209 .flags = PPC_FLAGS_RS64,
3767 .msr_mask = xxx, 4210 .msr_mask = xxx,
@@ -3769,7 +4212,7 @@ static ppc_def_t ppc_defs[] = { @@ -3769,7 +4212,7 @@ static ppc_def_t ppc_defs[] = {
3769 { 4212 {
3770 .name = "NortStar", 4213 .name = "NortStar",
3771 .pvr = CPU_PPC_RS64II, 4214 .pvr = CPU_PPC_RS64II,
3772 - .pvr_mask = 0xFFFF0000, 4215 + .pvr_mask = 0xFFFFFFFF,
3773 .insns_flags = PPC_INSNS_RS64, 4216 .insns_flags = PPC_INSNS_RS64,
3774 .flags = PPC_FLAGS_RS64, 4217 .flags = PPC_FLAGS_RS64,
3775 .msr_mask = xxx, 4218 .msr_mask = xxx,
@@ -3777,7 +4220,7 @@ static ppc_def_t ppc_defs[] = { @@ -3777,7 +4220,7 @@ static ppc_def_t ppc_defs[] = {
3777 { 4220 {
3778 .name = "A50", 4221 .name = "A50",
3779 .pvr = CPU_PPC_RS64II, 4222 .pvr = CPU_PPC_RS64II,
3780 - .pvr_mask = 0xFFFF0000, 4223 + .pvr_mask = 0xFFFFFFFF,
3781 .insns_flags = PPC_INSNS_RS64, 4224 .insns_flags = PPC_INSNS_RS64,
3782 .flags = PPC_FLAGS_RS64, 4225 .flags = PPC_FLAGS_RS64,
3783 .msr_mask = xxx, 4226 .msr_mask = xxx,
@@ -3788,7 +4231,7 @@ static ppc_def_t ppc_defs[] = { @@ -3788,7 +4231,7 @@ static ppc_def_t ppc_defs[] = {
3788 { 4231 {
3789 .name = "RS64-III", 4232 .name = "RS64-III",
3790 .pvr = CPU_PPC_RS64III, 4233 .pvr = CPU_PPC_RS64III,
3791 - .pvr_mask = 0xFFFF0000, 4234 + .pvr_mask = 0xFFFFFFFF,
3792 .insns_flags = PPC_INSNS_RS64, 4235 .insns_flags = PPC_INSNS_RS64,
3793 .flags = PPC_FLAGS_RS64, 4236 .flags = PPC_FLAGS_RS64,
3794 .msr_mask = xxx, 4237 .msr_mask = xxx,
@@ -3796,7 +4239,7 @@ static ppc_def_t ppc_defs[] = { @@ -3796,7 +4239,7 @@ static ppc_def_t ppc_defs[] = {
3796 { 4239 {
3797 .name = "Pulsar", 4240 .name = "Pulsar",
3798 .pvr = CPU_PPC_RS64III, 4241 .pvr = CPU_PPC_RS64III,
3799 - .pvr_mask = 0xFFFF0000, 4242 + .pvr_mask = 0xFFFFFFFF,
3800 .insns_flags = PPC_INSNS_RS64, 4243 .insns_flags = PPC_INSNS_RS64,
3801 .flags = PPC_FLAGS_RS64, 4244 .flags = PPC_FLAGS_RS64,
3802 .msr_mask = xxx, 4245 .msr_mask = xxx,
@@ -3807,7 +4250,7 @@ static ppc_def_t ppc_defs[] = { @@ -3807,7 +4250,7 @@ static ppc_def_t ppc_defs[] = {
3807 { 4250 {
3808 .name = "RS64-IV", 4251 .name = "RS64-IV",
3809 .pvr = CPU_PPC_RS64IV, 4252 .pvr = CPU_PPC_RS64IV,
3810 - .pvr_mask = 0xFFFF0000, 4253 + .pvr_mask = 0xFFFFFFFF,
3811 .insns_flags = PPC_INSNS_RS64, 4254 .insns_flags = PPC_INSNS_RS64,
3812 .flags = PPC_FLAGS_RS64, 4255 .flags = PPC_FLAGS_RS64,
3813 .msr_mask = xxx, 4256 .msr_mask = xxx,
@@ -3815,7 +4258,7 @@ static ppc_def_t ppc_defs[] = { @@ -3815,7 +4258,7 @@ static ppc_def_t ppc_defs[] = {
3815 { 4258 {
3816 .name = "IceStar", 4259 .name = "IceStar",
3817 .pvr = CPU_PPC_RS64IV, 4260 .pvr = CPU_PPC_RS64IV,
3818 - .pvr_mask = 0xFFFF0000, 4261 + .pvr_mask = 0xFFFFFFFF,
3819 .insns_flags = PPC_INSNS_RS64, 4262 .insns_flags = PPC_INSNS_RS64,
3820 .flags = PPC_FLAGS_RS64, 4263 .flags = PPC_FLAGS_RS64,
3821 .msr_mask = xxx, 4264 .msr_mask = xxx,
@@ -3823,7 +4266,7 @@ static ppc_def_t ppc_defs[] = { @@ -3823,7 +4266,7 @@ static ppc_def_t ppc_defs[] = {
3823 { 4266 {
3824 .name = "IStar", 4267 .name = "IStar",
3825 .pvr = CPU_PPC_RS64IV, 4268 .pvr = CPU_PPC_RS64IV,
3826 - .pvr_mask = 0xFFFF0000, 4269 + .pvr_mask = 0xFFFFFFFF,
3827 .insns_flags = PPC_INSNS_RS64, 4270 .insns_flags = PPC_INSNS_RS64,
3828 .flags = PPC_FLAGS_RS64, 4271 .flags = PPC_FLAGS_RS64,
3829 .msr_mask = xxx, 4272 .msr_mask = xxx,
@@ -3831,7 +4274,7 @@ static ppc_def_t ppc_defs[] = { @@ -3831,7 +4274,7 @@ static ppc_def_t ppc_defs[] = {
3831 { 4274 {
3832 .name = "SStar", 4275 .name = "SStar",
3833 .pvr = CPU_PPC_RS64IV, 4276 .pvr = CPU_PPC_RS64IV,
3834 - .pvr_mask = 0xFFFF0000, 4277 + .pvr_mask = 0xFFFFFFFF,
3835 .insns_flags = PPC_INSNS_RS64, 4278 .insns_flags = PPC_INSNS_RS64,
3836 .flags = PPC_FLAGS_RS64, 4279 .flags = PPC_FLAGS_RS64,
3837 .msr_mask = xxx, 4280 .msr_mask = xxx,
@@ -3843,7 +4286,7 @@ static ppc_def_t ppc_defs[] = { @@ -3843,7 +4286,7 @@ static ppc_def_t ppc_defs[] = {
3843 { 4286 {
3844 .name = "POWER", 4287 .name = "POWER",
3845 .pvr = CPU_POWER, 4288 .pvr = CPU_POWER,
3846 - .pvr_mask = 0xFFFF0000, 4289 + .pvr_mask = 0xFFFFFFFF,
3847 .insns_flags = PPC_INSNS_POWER, 4290 .insns_flags = PPC_INSNS_POWER,
3848 .flags = PPC_FLAGS_POWER, 4291 .flags = PPC_FLAGS_POWER,
3849 .msr_mask = xxx, 4292 .msr_mask = xxx,
@@ -3855,7 +4298,7 @@ static ppc_def_t ppc_defs[] = { @@ -3855,7 +4298,7 @@ static ppc_def_t ppc_defs[] = {
3855 { 4298 {
3856 .name = "POWER2", 4299 .name = "POWER2",
3857 .pvr = CPU_POWER2, 4300 .pvr = CPU_POWER2,
3858 - .pvr_mask = 0xFFFF0000, 4301 + .pvr_mask = 0xFFFFFFFF,
3859 .insns_flags = PPC_INSNS_POWER, 4302 .insns_flags = PPC_INSNS_POWER,
3860 .flags = PPC_FLAGS_POWER, 4303 .flags = PPC_FLAGS_POWER,
3861 .msr_mask = xxx, 4304 .msr_mask = xxx,
@@ -3865,8 +4308,8 @@ static ppc_def_t ppc_defs[] = { @@ -3865,8 +4308,8 @@ static ppc_def_t ppc_defs[] = {
3865 #if defined (TODO) 4308 #if defined (TODO)
3866 { 4309 {
3867 .name = "ppc64", 4310 .name = "ppc64",
3868 - .pvr = CPU_PPC_970,  
3869 - .pvr_mask = 0xFFFF0000, 4311 + .pvr = CPU_PPC_970FX,
  4312 + .pvr_mask = 0xFFFFFFFF,
3870 .insns_flags = PPC_INSNS_PPC64, 4313 .insns_flags = PPC_INSNS_PPC64,
3871 .flags = PPC_FLAGS_PPC64, 4314 .flags = PPC_FLAGS_PPC64,
3872 .msr_mask = 0xA00000000204FF36ULL, 4315 .msr_mask = 0xA00000000204FF36ULL,