gwj / at91sam9263 · Commits

Commit 2642cdb33b3f7469ec679f1034870b96178ca05a

Authored by aurel32
1 parent 100d9891

target-alpha: document more registers used by 21264 

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7032 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 2 additions and 2 deletions
target-alpha/cpu.h
  View file @2642cdb
@@ -158,7 +158,7 @@ enum { @@ -158,7 +158,7 @@ enum {
158 IPR_ITB_PTE = 0x01, /* 21264 */ 158 IPR_ITB_PTE = 0x01, /* 21264 */
159 IPR_ITB_IAP = 0x02, 159 IPR_ITB_IAP = 0x02,
160 IPR_ITB_IA = 0x03, /* 21264 */ 160 IPR_ITB_IA = 0x03, /* 21264 */
161 - IPR_ITB_IS = 0x04, 161 + IPR_ITB_IS = 0x04, /* 21264 */
162 IPR_PMPC = 0x05, 162 IPR_PMPC = 0x05,
163 IPR_EXC_ADDR = 0x06, /* 21264 */ 163 IPR_EXC_ADDR = 0x06, /* 21264 */
164 IPR_IVA_FORM = 0x07, /* 21264 */ 164 IPR_IVA_FORM = 0x07, /* 21264 */
@@ -221,7 +221,7 @@ enum { @@ -221,7 +221,7 @@ enum {
221 IPR_M_CTL = 0x28, /* 21264 */ 221 IPR_M_CTL = 0x28, /* 21264 */
222 #define IPR_M_CTL_SPE_SHIFT 1 222 #define IPR_M_CTL_SPE_SHIFT 1
223 #define IPR_M_CTL_SPE_MASK 7 223 #define IPR_M_CTL_SPE_MASK 7
224 - IPR_DC_CTL = 0x29, 224 + IPR_DC_CTL = 0x29, /* 21264 */
225 IPR_DC_STAT = 0x2A, /* 21264 */ 225 IPR_DC_STAT = 0x2A, /* 21264 */
226 /* Cbox IPRs */ 226 /* Cbox IPRs */
227 IPR_C_DATA = 0x2B, 227 IPR_C_DATA = 0x2B,