Commit 2582cfa0cba4d7efb36cee0ab709af6f5d810adc
1 parent
325f2747
Sparc32: convert slavio_misc to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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3 changed files
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146 additions
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64 deletions
hw/slavio_misc.c
| @@ -21,9 +21,10 @@ | @@ -21,9 +21,10 @@ | ||
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. | 22 | * THE SOFTWARE. |
| 23 | */ | 23 | */ |
| 24 | -#include "hw.h" | 24 | + |
| 25 | #include "sun4m.h" | 25 | #include "sun4m.h" |
| 26 | #include "sysemu.h" | 26 | #include "sysemu.h" |
| 27 | +#include "sysbus.h" | ||
| 27 | 28 | ||
| 28 | /* debug misc */ | 29 | /* debug misc */ |
| 29 | //#define DEBUG_MISC | 30 | //#define DEBUG_MISC |
| @@ -44,16 +45,21 @@ | @@ -44,16 +45,21 @@ | ||
| 44 | #endif | 45 | #endif |
| 45 | 46 | ||
| 46 | typedef struct MiscState { | 47 | typedef struct MiscState { |
| 48 | + SysBusDevice busdev; | ||
| 47 | qemu_irq irq; | 49 | qemu_irq irq; |
| 48 | uint8_t config; | 50 | uint8_t config; |
| 49 | uint8_t aux1, aux2; | 51 | uint8_t aux1, aux2; |
| 50 | uint8_t diag, mctrl; | 52 | uint8_t diag, mctrl; |
| 51 | uint32_t sysctrl; | 53 | uint32_t sysctrl; |
| 52 | uint16_t leds; | 54 | uint16_t leds; |
| 53 | - qemu_irq cpu_halt; | ||
| 54 | qemu_irq fdc_tc; | 55 | qemu_irq fdc_tc; |
| 55 | } MiscState; | 56 | } MiscState; |
| 56 | 57 | ||
| 58 | +typedef struct APCState { | ||
| 59 | + SysBusDevice busdev; | ||
| 60 | + qemu_irq cpu_halt; | ||
| 61 | +} APCState; | ||
| 62 | + | ||
| 57 | #define MISC_SIZE 1 | 63 | #define MISC_SIZE 1 |
| 58 | #define SYSCTRL_SIZE 4 | 64 | #define SYSCTRL_SIZE 4 |
| 59 | 65 | ||
| @@ -283,7 +289,7 @@ static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = { | @@ -283,7 +289,7 @@ static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = { | ||
| 283 | 289 | ||
| 284 | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | 290 | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 285 | { | 291 | { |
| 286 | - MiscState *s = opaque; | 292 | + APCState *s = opaque; |
| 287 | 293 | ||
| 288 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); | 294 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
| 289 | qemu_irq_raise(s->cpu_halt); | 295 | qemu_irq_raise(s->cpu_halt); |
| @@ -434,75 +440,148 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) | @@ -434,75 +440,148 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) | ||
| 434 | return 0; | 440 | return 0; |
| 435 | } | 441 | } |
| 436 | 442 | ||
| 437 | -void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, | 443 | +void *slavio_misc_init(target_phys_addr_t base, |
| 438 | target_phys_addr_t aux1_base, | 444 | target_phys_addr_t aux1_base, |
| 439 | target_phys_addr_t aux2_base, qemu_irq irq, | 445 | target_phys_addr_t aux2_base, qemu_irq irq, |
| 440 | - qemu_irq cpu_halt, qemu_irq **fdc_tc) | 446 | + qemu_irq fdc_tc) |
| 441 | { | 447 | { |
| 442 | - int io; | ||
| 443 | - MiscState *s; | ||
| 444 | - | ||
| 445 | - s = qemu_mallocz(sizeof(MiscState)); | 448 | + DeviceState *dev; |
| 449 | + SysBusDevice *s; | ||
| 450 | + MiscState *d; | ||
| 446 | 451 | ||
| 452 | + dev = qdev_create(NULL, "slavio_misc"); | ||
| 453 | + qdev_init(dev); | ||
| 454 | + s = sysbus_from_qdev(dev); | ||
| 447 | if (base) { | 455 | if (base) { |
| 448 | /* 8 bit registers */ | 456 | /* 8 bit registers */ |
| 449 | - | ||
| 450 | - // Slavio control | ||
| 451 | - io = cpu_register_io_memory(slavio_cfg_mem_read, | ||
| 452 | - slavio_cfg_mem_write, s); | ||
| 453 | - cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io); | ||
| 454 | - | ||
| 455 | - // Diagnostics | ||
| 456 | - io = cpu_register_io_memory(slavio_diag_mem_read, | ||
| 457 | - slavio_diag_mem_write, s); | ||
| 458 | - cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io); | ||
| 459 | - | ||
| 460 | - // Modem control | ||
| 461 | - io = cpu_register_io_memory(slavio_mdm_mem_read, | ||
| 462 | - slavio_mdm_mem_write, s); | ||
| 463 | - cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io); | ||
| 464 | - | 457 | + /* Slavio control */ |
| 458 | + sysbus_mmio_map(s, 0, base + MISC_CFG); | ||
| 459 | + /* Diagnostics */ | ||
| 460 | + sysbus_mmio_map(s, 1, base + MISC_DIAG); | ||
| 461 | + /* Modem control */ | ||
| 462 | + sysbus_mmio_map(s, 2, base + MISC_MDM); | ||
| 465 | /* 16 bit registers */ | 463 | /* 16 bit registers */ |
| 466 | - io = cpu_register_io_memory(slavio_led_mem_read, | ||
| 467 | - slavio_led_mem_write, s); | ||
| 468 | /* ss600mp diag LEDs */ | 464 | /* ss600mp diag LEDs */ |
| 469 | - cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io); | ||
| 470 | - | 465 | + sysbus_mmio_map(s, 3, base + MISC_LEDS); |
| 471 | /* 32 bit registers */ | 466 | /* 32 bit registers */ |
| 472 | - io = cpu_register_io_memory(slavio_sysctrl_mem_read, | ||
| 473 | - slavio_sysctrl_mem_write, s); | ||
| 474 | - // System control | ||
| 475 | - cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io); | 467 | + /* System control */ |
| 468 | + sysbus_mmio_map(s, 4, base + MISC_SYS); | ||
| 476 | } | 469 | } |
| 477 | - | ||
| 478 | - // AUX 1 (Misc System Functions) | ||
| 479 | if (aux1_base) { | 470 | if (aux1_base) { |
| 480 | - io = cpu_register_io_memory(slavio_aux1_mem_read, | ||
| 481 | - slavio_aux1_mem_write, s); | ||
| 482 | - cpu_register_physical_memory(aux1_base, MISC_SIZE, io); | 471 | + /* AUX 1 (Misc System Functions) */ |
| 472 | + sysbus_mmio_map(s, 5, aux1_base); | ||
| 483 | } | 473 | } |
| 484 | - | ||
| 485 | - // AUX 2 (Software Powerdown Control) | ||
| 486 | if (aux2_base) { | 474 | if (aux2_base) { |
| 487 | - io = cpu_register_io_memory(slavio_aux2_mem_read, | ||
| 488 | - slavio_aux2_mem_write, s); | ||
| 489 | - cpu_register_physical_memory(aux2_base, MISC_SIZE, io); | 475 | + /* AUX 2 (Software Powerdown Control) */ |
| 476 | + sysbus_mmio_map(s, 6, aux2_base); | ||
| 490 | } | 477 | } |
| 478 | + sysbus_connect_irq(s, 0, irq); | ||
| 479 | + sysbus_connect_irq(s, 1, fdc_tc); | ||
| 491 | 480 | ||
| 492 | - // Power management (APC) XXX: not a Slavio device | ||
| 493 | - if (power_base) { | ||
| 494 | - io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); | ||
| 495 | - cpu_register_physical_memory(power_base, MISC_SIZE, io); | ||
| 496 | - } | 481 | + d = FROM_SYSBUS(MiscState, s); |
| 497 | 482 | ||
| 498 | - s->irq = irq; | ||
| 499 | - s->cpu_halt = cpu_halt; | ||
| 500 | - *fdc_tc = &s->fdc_tc; | 483 | + return d; |
| 484 | +} | ||
| 485 | + | ||
| 486 | +static void apc_init1(SysBusDevice *dev) | ||
| 487 | +{ | ||
| 488 | + APCState *s = FROM_SYSBUS(APCState, dev); | ||
| 489 | + int io; | ||
| 501 | 490 | ||
| 502 | - register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, | 491 | + sysbus_init_irq(dev, &s->cpu_halt); |
| 492 | + | ||
| 493 | + /* Power management (APC) XXX: not a Slavio device */ | ||
| 494 | + io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); | ||
| 495 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 496 | +} | ||
| 497 | + | ||
| 498 | +void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) | ||
| 499 | +{ | ||
| 500 | + DeviceState *dev; | ||
| 501 | + SysBusDevice *s; | ||
| 502 | + | ||
| 503 | + dev = qdev_create(NULL, "apc"); | ||
| 504 | + qdev_init(dev); | ||
| 505 | + s = sysbus_from_qdev(dev); | ||
| 506 | + /* Power management (APC) XXX: not a Slavio device */ | ||
| 507 | + sysbus_mmio_map(s, 0, power_base); | ||
| 508 | + sysbus_connect_irq(s, 0, cpu_halt); | ||
| 509 | +} | ||
| 510 | + | ||
| 511 | +static void slavio_misc_init1(SysBusDevice *dev) | ||
| 512 | +{ | ||
| 513 | + MiscState *s = FROM_SYSBUS(MiscState, dev); | ||
| 514 | + int io; | ||
| 515 | + | ||
| 516 | + sysbus_init_irq(dev, &s->irq); | ||
| 517 | + sysbus_init_irq(dev, &s->fdc_tc); | ||
| 518 | + | ||
| 519 | + /* 8 bit registers */ | ||
| 520 | + /* Slavio control */ | ||
| 521 | + io = cpu_register_io_memory(slavio_cfg_mem_read, | ||
| 522 | + slavio_cfg_mem_write, s); | ||
| 523 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 524 | + | ||
| 525 | + /* Diagnostics */ | ||
| 526 | + io = cpu_register_io_memory(slavio_diag_mem_read, | ||
| 527 | + slavio_diag_mem_write, s); | ||
| 528 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 529 | + | ||
| 530 | + /* Modem control */ | ||
| 531 | + io = cpu_register_io_memory(slavio_mdm_mem_read, | ||
| 532 | + slavio_mdm_mem_write, s); | ||
| 533 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 534 | + | ||
| 535 | + /* 16 bit registers */ | ||
| 536 | + /* ss600mp diag LEDs */ | ||
| 537 | + io = cpu_register_io_memory(slavio_led_mem_read, | ||
| 538 | + slavio_led_mem_write, s); | ||
| 539 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 540 | + | ||
| 541 | + /* 32 bit registers */ | ||
| 542 | + /* System control */ | ||
| 543 | + io = cpu_register_io_memory(slavio_sysctrl_mem_read, | ||
| 544 | + slavio_sysctrl_mem_write, s); | ||
| 545 | + sysbus_init_mmio(dev, SYSCTRL_SIZE, io); | ||
| 546 | + | ||
| 547 | + /* AUX 1 (Misc System Functions) */ | ||
| 548 | + io = cpu_register_io_memory(slavio_aux1_mem_read, | ||
| 549 | + slavio_aux1_mem_write, s); | ||
| 550 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 551 | + | ||
| 552 | + /* AUX 2 (Software Powerdown Control) */ | ||
| 553 | + io = cpu_register_io_memory(slavio_aux2_mem_read, | ||
| 554 | + slavio_aux2_mem_write, s); | ||
| 555 | + sysbus_init_mmio(dev, MISC_SIZE, io); | ||
| 556 | + | ||
| 557 | + register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load, | ||
| 503 | s); | 558 | s); |
| 504 | qemu_register_reset(slavio_misc_reset, s); | 559 | qemu_register_reset(slavio_misc_reset, s); |
| 505 | slavio_misc_reset(s); | 560 | slavio_misc_reset(s); |
| 561 | +} | ||
| 506 | 562 | ||
| 507 | - return s; | 563 | +static SysBusDeviceInfo slavio_misc_info = { |
| 564 | + .init = slavio_misc_init1, | ||
| 565 | + .qdev.name = "slavio_misc", | ||
| 566 | + .qdev.size = sizeof(MiscState), | ||
| 567 | + .qdev.props = (DevicePropList[]) { | ||
| 568 | + {.name = NULL} | ||
| 569 | + } | ||
| 570 | +}; | ||
| 571 | + | ||
| 572 | +static SysBusDeviceInfo apc_info = { | ||
| 573 | + .init = apc_init1, | ||
| 574 | + .qdev.name = "apc", | ||
| 575 | + .qdev.size = sizeof(MiscState), | ||
| 576 | + .qdev.props = (DevicePropList[]) { | ||
| 577 | + {.name = NULL} | ||
| 578 | + } | ||
| 579 | +}; | ||
| 580 | + | ||
| 581 | +static void slavio_misc_register_devices(void) | ||
| 582 | +{ | ||
| 583 | + sysbus_register_withprop(&slavio_misc_info); | ||
| 584 | + sysbus_register_withprop(&apc_info); | ||
| 508 | } | 585 | } |
| 586 | + | ||
| 587 | +device_init(slavio_misc_register_devices) |
hw/sun4m.c
| @@ -435,7 +435,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | @@ -435,7 +435,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 435 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, | 435 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
| 436 | *espdma_irq, *ledma_irq; | 436 | *espdma_irq, *ledma_irq; |
| 437 | qemu_irq *esp_reset, *le_reset; | 437 | qemu_irq *esp_reset, *le_reset; |
| 438 | - qemu_irq *fdc_tc; | 438 | + qemu_irq fdc_tc; |
| 439 | qemu_irq *cpu_halt; | 439 | qemu_irq *cpu_halt; |
| 440 | ram_addr_t ram_offset, prom_offset; | 440 | ram_addr_t ram_offset, prom_offset; |
| 441 | unsigned long kernel_size; | 441 | unsigned long kernel_size; |
| @@ -553,10 +553,12 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | @@ -553,10 +553,12 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 553 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); | 553 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
| 554 | 554 | ||
| 555 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); | 555 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
| 556 | - slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, | 556 | + slavio_misc = slavio_misc_init(hwdef->slavio_base, |
| 557 | hwdef->aux1_base, hwdef->aux2_base, | 557 | hwdef->aux1_base, hwdef->aux2_base, |
| 558 | - slavio_irq[hwdef->me_irq], cpu_halt[0], | ||
| 559 | - &fdc_tc); | 558 | + slavio_irq[hwdef->me_irq], fdc_tc); |
| 559 | + if (hwdef->apc_base) { | ||
| 560 | + apc_init(hwdef->apc_base, cpu_halt[0]); | ||
| 561 | + } | ||
| 560 | 562 | ||
| 561 | if (hwdef->fd_base) { | 563 | if (hwdef->fd_base) { |
| 562 | /* there is zero or one floppy drive */ | 564 | /* there is zero or one floppy drive */ |
| @@ -566,7 +568,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | @@ -566,7 +568,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 566 | fd[0] = drives_table[drive_index].bdrv; | 568 | fd[0] = drives_table[drive_index].bdrv; |
| 567 | 569 | ||
| 568 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, | 570 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
| 569 | - fdc_tc); | 571 | + &fdc_tc); |
| 570 | } | 572 | } |
| 571 | 573 | ||
| 572 | if (drive_get_max_bus(IF_SCSI) > 0) { | 574 | if (drive_get_max_bus(IF_SCSI) > 0) { |
| @@ -1443,7 +1445,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1443,7 +1445,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 1443 | void *iommu, *espdma, *ledma, *nvram; | 1445 | void *iommu, *espdma, *ledma, *nvram; |
| 1444 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; | 1446 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
| 1445 | qemu_irq *esp_reset, *le_reset; | 1447 | qemu_irq *esp_reset, *le_reset; |
| 1446 | - qemu_irq *fdc_tc; | 1448 | + qemu_irq fdc_tc; |
| 1447 | ram_addr_t ram_offset, prom_offset; | 1449 | ram_addr_t ram_offset, prom_offset; |
| 1448 | unsigned long kernel_size; | 1450 | unsigned long kernel_size; |
| 1449 | int ret; | 1451 | int ret; |
| @@ -1539,8 +1541,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1539,8 +1541,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 1539 | slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1], | 1541 | slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1], |
| 1540 | ESCC_CLOCK, 1); | 1542 | ESCC_CLOCK, 1); |
| 1541 | 1543 | ||
| 1542 | - slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0, | ||
| 1543 | - slavio_irq[hwdef->me_irq], NULL, &fdc_tc); | 1544 | + slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0, |
| 1545 | + slavio_irq[hwdef->me_irq], fdc_tc); | ||
| 1544 | 1546 | ||
| 1545 | if (hwdef->fd_base != (target_phys_addr_t)-1) { | 1547 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
| 1546 | /* there is zero or one floppy drive */ | 1548 | /* there is zero or one floppy drive */ |
| @@ -1550,7 +1552,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1550,7 +1552,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 1550 | fd[0] = drives_table[drive_index].bdrv; | 1552 | fd[0] = drives_table[drive_index].bdrv; |
| 1551 | 1553 | ||
| 1552 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, | 1554 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
| 1553 | - fdc_tc); | 1555 | + &fdc_tc); |
| 1554 | } | 1556 | } |
| 1555 | 1557 | ||
| 1556 | if (drive_get_max_bus(IF_SCSI) > 0) { | 1558 | if (drive_get_max_bus(IF_SCSI) > 0) { |
hw/sun4m.h
| @@ -50,11 +50,12 @@ void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, | @@ -50,11 +50,12 @@ void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, | ||
| 50 | qemu_irq *cpu_irqs, unsigned int num_cpus); | 50 | qemu_irq *cpu_irqs, unsigned int num_cpus); |
| 51 | 51 | ||
| 52 | /* slavio_misc.c */ | 52 | /* slavio_misc.c */ |
| 53 | -void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, | 53 | +void *slavio_misc_init(target_phys_addr_t base, |
| 54 | target_phys_addr_t aux1_base, | 54 | target_phys_addr_t aux1_base, |
| 55 | target_phys_addr_t aux2_base, qemu_irq irq, | 55 | target_phys_addr_t aux2_base, qemu_irq irq, |
| 56 | - qemu_irq cpu_halt, qemu_irq **fdc_tc); | 56 | + qemu_irq fdc_tc); |
| 57 | void slavio_set_power_fail(void *opaque, int power_failing); | 57 | void slavio_set_power_fail(void *opaque, int power_failing); |
| 58 | +void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt); | ||
| 58 | 59 | ||
| 59 | /* cs4231.c */ | 60 | /* cs4231.c */ |
| 60 | void cs_init(target_phys_addr_t base, int irq, void *intctl); | 61 | void cs_init(target_phys_addr_t base, int irq, void *intctl); |