gwj / at91sam9263 · Commits

Commit 2576d836af8386199873b774ee5dfdf03015a6b0

Authored by blueswir1
1 parent 81b5b816

Use TCG not op 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5663 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 12 additions and 14 deletions
target-sparc/translate.c
  View file @2576d83
@@ -363,7 +363,7 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) @@ -363,7 +363,7 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
363 363
364 r_temp = tcg_temp_new(TCG_TYPE_TL); 364 r_temp = tcg_temp_new(TCG_TYPE_TL);
365 tcg_gen_xor_tl(r_temp, src1, src2); 365 tcg_gen_xor_tl(r_temp, src1, src2);
366 - tcg_gen_xori_tl(r_temp, r_temp, -1); 366 + tcg_gen_not_tl(r_temp, r_temp);
367 tcg_gen_xor_tl(cpu_tmp0, src1, dst); 367 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
368 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 368 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
369 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); 369 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
@@ -380,7 +380,7 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) @@ -380,7 +380,7 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
380 380
381 r_temp = tcg_temp_new(TCG_TYPE_TL); 381 r_temp = tcg_temp_new(TCG_TYPE_TL);
382 tcg_gen_xor_tl(r_temp, src1, src2); 382 tcg_gen_xor_tl(r_temp, src1, src2);
383 - tcg_gen_xori_tl(r_temp, r_temp, -1); 383 + tcg_gen_not_tl(r_temp, r_temp);
384 tcg_gen_xor_tl(cpu_tmp0, src1, dst); 384 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
385 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 385 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
386 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); 386 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
@@ -400,7 +400,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) @@ -400,7 +400,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
400 400
401 r_temp = tcg_temp_new(TCG_TYPE_TL); 401 r_temp = tcg_temp_new(TCG_TYPE_TL);
402 tcg_gen_xor_tl(r_temp, src1, src2); 402 tcg_gen_xor_tl(r_temp, src1, src2);
403 - tcg_gen_xori_tl(r_temp, r_temp, -1); 403 + tcg_gen_not_tl(r_temp, r_temp);
404 tcg_gen_xor_tl(cpu_tmp0, src1, dst); 404 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
405 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 405 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
406 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); 406 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
@@ -3089,7 +3089,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3089,7 +3089,7 @@ static void disas_sparc_insn(DisasContext * dc)
3089 gen_op_logic_cc(cpu_dst); 3089 gen_op_logic_cc(cpu_dst);
3090 break; 3090 break;
3091 case 0x7: 3091 case 0x7:
3092 - tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); 3092 + tcg_gen_not_tl(cpu_tmp0, cpu_src2);
3093 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); 3093 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3094 if (xop & 0x10) 3094 if (xop & 0x10)
3095 gen_op_logic_cc(cpu_dst); 3095 gen_op_logic_cc(cpu_dst);
@@ -3928,14 +3928,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3928,14 +3928,13 @@ static void disas_sparc_insn(DisasContext * dc)
3928 break; 3928 break;
3929 case 0x066: /* VIS I fnot2 */ 3929 case 0x066: /* VIS I fnot2 */
3930 CHECK_FPU_FEATURE(dc, VIS1); 3930 CHECK_FPU_FEATURE(dc, VIS1);
3931 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],  
3932 - -1);  
3933 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],  
3934 - cpu_fpr[DFPREG(rs2) + 1], -1); 3931 + tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
  3932 + tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
  3933 + cpu_fpr[DFPREG(rs2) + 1]);
3935 break; 3934 break;
3936 case 0x067: /* VIS I fnot2s */ 3935 case 0x067: /* VIS I fnot2s */
3937 CHECK_FPU_FEATURE(dc, VIS1); 3936 CHECK_FPU_FEATURE(dc, VIS1);
3938 - tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1); 3937 + tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]);
3939 break; 3938 break;
3940 case 0x068: /* VIS I fandnot1 */ 3939 case 0x068: /* VIS I fandnot1 */
3941 CHECK_FPU_FEATURE(dc, VIS1); 3940 CHECK_FPU_FEATURE(dc, VIS1);
@@ -3951,14 +3950,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3951,14 +3950,13 @@ static void disas_sparc_insn(DisasContext * dc)
3951 break; 3950 break;
3952 case 0x06a: /* VIS I fnot1 */ 3951 case 0x06a: /* VIS I fnot1 */
3953 CHECK_FPU_FEATURE(dc, VIS1); 3952 CHECK_FPU_FEATURE(dc, VIS1);
3954 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],  
3955 - -1);  
3956 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],  
3957 - cpu_fpr[DFPREG(rs1) + 1], -1); 3953 + tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
  3954 + tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
  3955 + cpu_fpr[DFPREG(rs1) + 1]);
3958 break; 3956 break;
3959 case 0x06b: /* VIS I fnot1s */ 3957 case 0x06b: /* VIS I fnot1s */
3960 CHECK_FPU_FEATURE(dc, VIS1); 3958 CHECK_FPU_FEATURE(dc, VIS1);
3961 - tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1); 3959 + tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]);
3962 break; 3960 break;
3963 case 0x06c: /* VIS I fxor */ 3961 case 0x06c: /* VIS I fxor */
3964 CHECK_FPU_FEATURE(dc, VIS1); 3962 CHECK_FPU_FEATURE(dc, VIS1);