gwj / at91sam9263 · Commits

Commit 2495152227b73a277019453990eac4025220156b

Authored by aurel32
1 parent 4e47ea67

target-ppc: Add float register read/write using XML 

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 32 additions and 0 deletions
target-ppc/translate_init.c
  View file @2495152
... ... @@ -9272,6 +9272,33 @@ static void dump_ppc_insns (CPUPPCState *env)
9272 9272 }
9273 9273 #endif
9274 9274  
  9275 +static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
  9276 +{
  9277 + if (n < 32) {
  9278 + stfq_p(mem_buf, env->fpr[n]);
  9279 + return 8;
  9280 + }
  9281 + if (n == 32) {
  9282 + /* FPSCR not implemented */
  9283 + memset(mem_buf, 0, 4);
  9284 + return 4;
  9285 + }
  9286 + return 0;
  9287 +}
  9288 +
  9289 +static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
  9290 +{
  9291 + if (n < 32) {
  9292 + env->fpr[n] = ldfq_p(mem_buf);
  9293 + return 8;
  9294 + }
  9295 + if (n == 32) {
  9296 + /* FPSCR not implemented */
  9297 + return 4;
  9298 + }
  9299 + return 0;
  9300 +}
  9301 +
9275 9302 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9276 9303 {
9277 9304 env->msr_mask = def->msr_mask;
... ... @@ -9284,6 +9311,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9284 9311 if (create_ppc_opcodes(env, def) < 0)
9285 9312 return -1;
9286 9313 init_ppc_proc(env, def);
  9314 +
  9315 + if (def->insns_flags & PPC_FLOAT) {
  9316 + gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
  9317 + 33, "power-fpu.xml", 0);
  9318 + }
9287 9319 #if defined(PPC_DUMP_CPU)
9288 9320 {
9289 9321 const char *mmu_model, *excp_model, *bus_model;
... ...