gwj / at91sam9263 · Commits

Commit 21d215831e66c01bafd92a7020c0c1f6a7d49c26

Authored by aurel32
1 parent cd633b10

Add GEN_VXFORM_SIMM macro for subsequent instructions. 

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6172 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 18 additions and 0 deletions
target-ppc/translate.c
  View file @21d2158
... ... @@ -370,6 +370,8 @@ EXTRACT_HELPER(IMM, 12, 8);
370 370 EXTRACT_SHELPER(SIMM, 0, 16);
371 371 /* 16 bits unsigned immediate value */
372 372 EXTRACT_HELPER(UIMM, 0, 16);
  373 +/* 5 bits signed immediate value */
  374 +EXTRACT_HELPER(SIMM5, 16, 5);
373 375 /* Bit count */
374 376 EXTRACT_HELPER(NB, 11, 5);
375 377 /* Shift count */
... ... @@ -6270,6 +6272,22 @@ GEN_VXFORM(vrlb, 2, 0);
6270 6272 GEN_VXFORM(vrlh, 2, 1);
6271 6273 GEN_VXFORM(vrlw, 2, 2);
6272 6274  
  6275 +#define GEN_VXFORM_SIMM(name, opc2, opc3) \
  6276 + GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
  6277 + { \
  6278 + TCGv_ptr rd; \
  6279 + TCGv_i32 simm; \
  6280 + if (unlikely(!ctx->altivec_enabled)) { \
  6281 + gen_exception(ctx, POWERPC_EXCP_VPU); \
  6282 + return; \
  6283 + } \
  6284 + simm = tcg_const_i32(SIMM5(ctx->opcode)); \
  6285 + rd = gen_avr_ptr(rD(ctx->opcode)); \
  6286 + gen_helper_##name (rd, simm); \
  6287 + tcg_temp_free_i32(simm); \
  6288 + tcg_temp_free_ptr(rd); \
  6289 + }
  6290 +
6273 6291 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6274 6292 {
6275 6293 TCGv_ptr ra, rb, rd;
... ...