Commit 20c4c97c9b9bcc413371e1b78e7db5306eb7fdd6

Authored by ths
1 parent a4e7dd52

Switch MIPS movn/movz to TCG.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4506 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips/op.c
@@ -510,20 +510,6 @@ void op_dmultu (void) @@ -510,20 +510,6 @@ void op_dmultu (void)
510 #endif 510 #endif
511 511
512 /* Conditional moves */ 512 /* Conditional moves */
513 -void op_movn (void)  
514 -{  
515 - if (T1 != 0)  
516 - env->gpr[env->current_tc][PARAM1] = T0;  
517 - FORCE_RET();  
518 -}  
519 -  
520 -void op_movz (void)  
521 -{  
522 - if (T1 == 0)  
523 - env->gpr[env->current_tc][PARAM1] = T0;  
524 - FORCE_RET();  
525 -}  
526 -  
527 void op_movf (void) 513 void op_movf (void)
528 { 514 {
529 if (!(env->fpu->fcr31 & PARAM1)) 515 if (!(env->fpu->fcr31 & PARAM1))
target-mips/translate.c
@@ -1707,11 +1707,23 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1707,11 +1707,23 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1707 opn = "mul"; 1707 opn = "mul";
1708 break; 1708 break;
1709 case OPC_MOVN: 1709 case OPC_MOVN:
1710 - gen_op_movn(rd); 1710 + {
  1711 + int l1 = gen_new_label();
  1712 +
  1713 + tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
  1714 + gen_op_store_gpr_T0(rd);
  1715 + gen_set_label(l1);
  1716 + }
1711 opn = "movn"; 1717 opn = "movn";
1712 goto print; 1718 goto print;
1713 case OPC_MOVZ: 1719 case OPC_MOVZ:
1714 - gen_op_movz(rd); 1720 + {
  1721 + int l1 = gen_new_label();
  1722 +
  1723 + tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(0), l1);
  1724 + gen_op_store_gpr_T0(rd);
  1725 + gen_set_label(l1);
  1726 + }
1715 opn = "movz"; 1727 opn = "movz";
1716 goto print; 1728 goto print;
1717 case OPC_SLLV: 1729 case OPC_SLLV: