Commit 1fc7bf6ee8083ef8cd2c636e6481ab2f9beb72d4

Authored by aurel32
1 parent fab9d284

target-mips: optimize gen_cp0()

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7040 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 5 additions and 27 deletions
target-mips/translate.c
@@ -3484,8 +3484,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3484,8 +3484,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3484 default: 3484 default:
3485 goto die; 3485 goto die;
3486 } 3486 }
3487 - /* Stop translation as we may have switched the execution mode */  
3488 - ctx->bstate = BS_STOP;  
3489 break; 3487 break;
3490 case 10: 3488 case 10:
3491 switch (sel) { 3489 switch (sel) {
@@ -3507,8 +3505,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3507,8 +3505,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3507 default: 3505 default:
3508 goto die; 3506 goto die;
3509 } 3507 }
3510 - /* Stop translation as we may have switched the execution mode */  
3511 - ctx->bstate = BS_STOP;  
3512 break; 3508 break;
3513 case 12: 3509 case 12:
3514 switch (sel) { 3510 switch (sel) {
@@ -3553,8 +3549,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se @@ -3553,8 +3549,6 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
3553 default: 3549 default:
3554 goto die; 3550 goto die;
3555 } 3551 }
3556 - /* Stop translation as we may have switched the execution mode */  
3557 - ctx->bstate = BS_STOP;  
3558 break; 3552 break;
3559 case 14: 3553 case 14:
3560 switch (sel) { 3554 switch (sel) {
@@ -4756,7 +4750,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s @@ -4756,7 +4750,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
4756 ctx->bstate = BS_STOP; 4750 ctx->bstate = BS_STOP;
4757 break; 4751 break;
4758 case 1: 4752 case 1:
4759 - /* ignored */ 4753 + /* ignored, read only */
4760 rn = "Config1"; 4754 rn = "Config1";
4761 break; 4755 break;
4762 case 2: 4756 case 2:
@@ -5350,21 +5344,14 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5350,21 +5344,14 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5350 /* Treat as NOP. */ 5344 /* Treat as NOP. */
5351 return; 5345 return;
5352 } 5346 }
5353 - {  
5354 - TCGv t0 = tcg_temp_local_new();  
5355 -  
5356 - gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7);  
5357 - gen_store_gpr(t0, rt);  
5358 - tcg_temp_free(t0);  
5359 - } 5347 + gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5360 opn = "mfc0"; 5348 opn = "mfc0";
5361 break; 5349 break;
5362 case OPC_MTC0: 5350 case OPC_MTC0:
5363 { 5351 {
5364 - TCGv t0 = tcg_temp_local_new(); 5352 + TCGv t0 = tcg_temp_new();
5365 5353
5366 gen_load_gpr(t0, rt); 5354 gen_load_gpr(t0, rt);
5367 - save_cpu_state(ctx, 1);  
5368 gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); 5355 gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5369 tcg_temp_free(t0); 5356 tcg_temp_free(t0);
5370 } 5357 }
@@ -5377,22 +5364,15 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5377,22 +5364,15 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5377 /* Treat as NOP. */ 5364 /* Treat as NOP. */
5378 return; 5365 return;
5379 } 5366 }
5380 - {  
5381 - TCGv t0 = tcg_temp_local_new();  
5382 -  
5383 - gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7);  
5384 - gen_store_gpr(t0, rt);  
5385 - tcg_temp_free(t0);  
5386 - } 5367 + gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5387 opn = "dmfc0"; 5368 opn = "dmfc0";
5388 break; 5369 break;
5389 case OPC_DMTC0: 5370 case OPC_DMTC0:
5390 check_insn(env, ctx, ISA_MIPS3); 5371 check_insn(env, ctx, ISA_MIPS3);
5391 { 5372 {
5392 - TCGv t0 = tcg_temp_local_new(); 5373 + TCGv t0 = tcg_temp_new();
5393 5374
5394 gen_load_gpr(t0, rt); 5375 gen_load_gpr(t0, rt);
5395 - save_cpu_state(ctx, 1);  
5396 gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); 5376 gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5397 tcg_temp_free(t0); 5377 tcg_temp_free(t0);
5398 } 5378 }
@@ -5442,7 +5422,6 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5442,7 +5422,6 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5442 case OPC_ERET: 5422 case OPC_ERET:
5443 opn = "eret"; 5423 opn = "eret";
5444 check_insn(env, ctx, ISA_MIPS2); 5424 check_insn(env, ctx, ISA_MIPS2);
5445 - save_cpu_state(ctx, 1);  
5446 gen_helper_eret(); 5425 gen_helper_eret();
5447 ctx->bstate = BS_EXCP; 5426 ctx->bstate = BS_EXCP;
5448 break; 5427 break;
@@ -5453,7 +5432,6 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5453,7 +5432,6 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5453 MIPS_INVAL(opn); 5432 MIPS_INVAL(opn);
5454 generate_exception(ctx, EXCP_RI); 5433 generate_exception(ctx, EXCP_RI);
5455 } else { 5434 } else {
5456 - save_cpu_state(ctx, 1);  
5457 gen_helper_deret(); 5435 gen_helper_deret();
5458 ctx->bstate = BS_EXCP; 5436 ctx->bstate = BS_EXCP;
5459 } 5437 }