gwj / at91sam9263 · Commits

Commit 1e3d0552f561429ed8236f71857f28c1903e5774

Authored by ths
1 parent 8487327a

Update some comments, 64bit FPU support is functional regardless of 

funny non-standard fcr0 bits on earlier CPUs.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2919 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 8 additions and 5 deletions
target-mips/TODO
  View file @1e3d055
@@ -16,7 +16,7 @@ General @@ -16,7 +16,7 @@ General
16 16
17 MIPS64 17 MIPS64
18 ------ 18 ------
19 -- 64bit FPU enable flag not handled correctly 19 +- Only lighly tested but apparently functional as of 2007-05-31.
20 20
21 "Generic" 4Kc system emulation 21 "Generic" 4Kc system emulation
22 ------------------------------ 22 ------------------------------
target-mips/translate_init.c
  View file @1e3d055
@@ -146,7 +146,7 @@ static mips_def_t mips_defs[] = @@ -146,7 +146,7 @@ static mips_def_t mips_defs[] =
146 .SYNCI_Step = 16, 146 .SYNCI_Step = 16,
147 .CCRes = 2, 147 .CCRes = 2,
148 .Status_rw_bitmask = 0x3678FFFF, 148 .Status_rw_bitmask = 0x3678FFFF,
149 - /* XXX: The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ 149 + /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
150 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), 150 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
151 }, 151 },
152 { 152 {
@@ -176,7 +176,7 @@ static mips_def_t mips_defs[] = @@ -176,7 +176,7 @@ static mips_def_t mips_defs[] =
176 .SYNCI_Step = 32, 176 .SYNCI_Step = 32,
177 .CCRes = 2, 177 .CCRes = 2,
178 .Status_rw_bitmask = 0x3678FFFF, 178 .Status_rw_bitmask = 0x3678FFFF,
179 - /* XXX: The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ 179 + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
180 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | 180 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
181 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), 181 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
182 }, 182 },
@@ -193,7 +193,7 @@ static mips_def_t mips_defs[] = @@ -193,7 +193,7 @@ static mips_def_t mips_defs[] =
193 .SYNCI_Step = 32, 193 .SYNCI_Step = 32,
194 .CCRes = 2, 194 .CCRes = 2,
195 .Status_rw_bitmask = 0x36FBFFFF, 195 .Status_rw_bitmask = 0x36FBFFFF,
196 - /* XXX: The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ 196 + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
197 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | 197 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
198 (1 << FCR0_D) | (1 << FCR0_S) | 198 (1 << FCR0_D) | (1 << FCR0_S) |
199 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), 199 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
@@ -279,6 +279,10 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) @@ -279,6 +279,10 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
279 if (env->fcr0 & (1 << FCR0_F64)) 279 if (env->fcr0 & (1 << FCR0_F64))
280 env->hflags |= MIPS_HFLAG_F64; 280 env->hflags |= MIPS_HFLAG_F64;
281 #else 281 #else
  282 + /* There are more full-featured MMU variants in older MIPS CPUs,
  283 + R3000, R6000 and R8000 come to mind. If we ever support them,
  284 + this check will need to look up a different place than those
  285 + newfangled config registers. */
282 switch ((env->CP0_Config0 >> CP0C0_MT) & 3) { 286 switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
283 case 0: 287 case 0:
284 no_mmu_init(env, def); 288 no_mmu_init(env, def);
@@ -290,7 +294,6 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) @@ -290,7 +294,6 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
290 fixed_mmu_init(env, def); 294 fixed_mmu_init(env, def);
291 break; 295 break;
292 default: 296 default:
293 - /* Older CPUs like the R3000 may need nonstandard handling here. */  
294 cpu_abort(env, "MMU type not supported\n"); 297 cpu_abort(env, "MMU type not supported\n");
295 } 298 }
296 env->CP0_Random = env->nb_tlb - 1; 299 env->CP0_Random = env->nb_tlb - 1;