Commit 18fba28c95d0f504d745e8e25c61f06e13601d10
1 parent
68016c62
ppc fixes - gcc 3.4 compile fix (initial patch by Jocelyn Mayer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1273 c046a42c-6fe2-441c-8c8c-71466251a162
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5 changed files
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34 additions
and
52 deletions
target-ppc/cpu.h
| ... | ... | @@ -26,23 +26,6 @@ |
| 26 | 26 | |
| 27 | 27 | //#define USE_OPEN_FIRMWARE |
| 28 | 28 | |
| 29 | -/*** Sign extend constants ***/ | |
| 30 | -/* 8 to 32 bits */ | |
| 31 | -static inline int32_t s_ext8 (uint8_t value) | |
| 32 | -{ | |
| 33 | - int8_t *tmp = &value; | |
| 34 | - | |
| 35 | - return *tmp; | |
| 36 | -} | |
| 37 | - | |
| 38 | -/* 16 to 32 bits */ | |
| 39 | -static inline int32_t s_ext16 (uint16_t value) | |
| 40 | -{ | |
| 41 | - int16_t *tmp = &value; | |
| 42 | - | |
| 43 | - return *tmp; | |
| 44 | -} | |
| 45 | - | |
| 46 | 29 | #include "config.h" |
| 47 | 30 | #include <setjmp.h> |
| 48 | 31 | ... | ... |
target-ppc/helper.c
| ... | ... | @@ -655,16 +655,21 @@ void _store_msr (CPUState *env, uint32_t value) |
| 655 | 655 | msr_dr = (value >> MSR_DR) & 0x01; |
| 656 | 656 | msr_ri = (value >> MSR_RI) & 0x01; |
| 657 | 657 | msr_le = (value >> MSR_LE) & 0x01; |
| 658 | + /* XXX: should enter PM state if msr_pow has been set */ | |
| 658 | 659 | } |
| 659 | 660 | |
| 661 | +#if defined (CONFIG_USER_ONLY) | |
| 660 | 662 | void do_interrupt (CPUState *env) |
| 661 | 663 | { |
| 662 | -#if defined (CONFIG_USER_ONLY) | |
| 663 | - env->exception_index |= 0x100; | |
| 664 | + env->exception_index = -1; | |
| 665 | +} | |
| 664 | 666 | #else |
| 667 | +void do_interrupt (CPUState *env) | |
| 668 | +{ | |
| 665 | 669 | uint32_t msr; |
| 666 | - int excp = env->exception_index; | |
| 670 | + int excp; | |
| 667 | 671 | |
| 672 | + excp = env->exception_index; | |
| 668 | 673 | msr = _load_msr(env); |
| 669 | 674 | #if defined (DEBUG_EXCEPTIONS) |
| 670 | 675 | if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
| ... | ... | @@ -906,6 +911,6 @@ void do_interrupt (CPUState *env) |
| 906 | 911 | #else |
| 907 | 912 | T0 = 0; |
| 908 | 913 | #endif |
| 909 | -#endif | |
| 910 | 914 | env->exception_index = -1; |
| 911 | 915 | } |
| 916 | +#endif /* !CONFIG_USER_ONLY */ | ... | ... |
target-ppc/op.c
| ... | ... | @@ -147,21 +147,6 @@ PPC_OP(set_Rc0) |
| 147 | 147 | } else { |
| 148 | 148 | tmp = 0x02; |
| 149 | 149 | } |
| 150 | - env->crf[0] = tmp; | |
| 151 | - RETURN(); | |
| 152 | -} | |
| 153 | - | |
| 154 | -PPC_OP(set_Rc0_ov) | |
| 155 | -{ | |
| 156 | - uint32_t tmp; | |
| 157 | - | |
| 158 | - if (Ts0 < 0) { | |
| 159 | - tmp = 0x08; | |
| 160 | - } else if (Ts0 > 0) { | |
| 161 | - tmp = 0x04; | |
| 162 | - } else { | |
| 163 | - tmp = 0x02; | |
| 164 | - } | |
| 165 | 150 | tmp |= xer_ov; |
| 166 | 151 | env->crf[0] = tmp; |
| 167 | 152 | RETURN(); |
| ... | ... | @@ -1062,14 +1047,14 @@ PPC_OP(eqv) |
| 1062 | 1047 | /* extend sign byte */ |
| 1063 | 1048 | PPC_OP(extsb) |
| 1064 | 1049 | { |
| 1065 | - Ts0 = s_ext8(Ts0); | |
| 1050 | + Ts0 = (int8_t)(Ts0); | |
| 1066 | 1051 | RETURN(); |
| 1067 | 1052 | } |
| 1068 | 1053 | |
| 1069 | 1054 | /* extend sign half word */ |
| 1070 | 1055 | PPC_OP(extsh) |
| 1071 | 1056 | { |
| 1072 | - Ts0 = s_ext16(Ts0); | |
| 1057 | + Ts0 = (int16_t)(Ts0); | |
| 1073 | 1058 | RETURN(); |
| 1074 | 1059 | } |
| 1075 | 1060 | ... | ... |
target-ppc/op_helper.c
target-ppc/translate.c
| ... | ... | @@ -179,6 +179,11 @@ static void gen_##name (DisasContext *ctx) |
| 179 | 179 | |
| 180 | 180 | typedef struct opcode_t { |
| 181 | 181 | unsigned char opc1, opc2, opc3; |
| 182 | +#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */ | |
| 183 | + unsigned char pad[5]; | |
| 184 | +#else | |
| 185 | + unsigned char pad[1]; | |
| 186 | +#endif | |
| 182 | 187 | opc_handler_t handler; |
| 183 | 188 | } opcode_t; |
| 184 | 189 | |
| ... | ... | @@ -192,7 +197,7 @@ static inline uint32_t name (uint32_t opcode) \ |
| 192 | 197 | #define EXTRACT_SHELPER(name, shift, nb) \ |
| 193 | 198 | static inline int32_t name (uint32_t opcode) \ |
| 194 | 199 | { \ |
| 195 | - return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \ | |
| 200 | + return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ | |
| 196 | 201 | } |
| 197 | 202 | |
| 198 | 203 | /* Opcode part 1 */ |
| ... | ... | @@ -285,10 +290,11 @@ static inline uint32_t MASK (uint32_t start, uint32_t end) |
| 285 | 290 | #endif |
| 286 | 291 | |
| 287 | 292 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
| 288 | -OPCODES_SECTION static opcode_t opc_##name = { \ | |
| 293 | +OPCODES_SECTION opcode_t opc_##name = { \ | |
| 289 | 294 | .opc1 = op1, \ |
| 290 | 295 | .opc2 = op2, \ |
| 291 | 296 | .opc3 = op3, \ |
| 297 | + .pad = { 0, }, \ | |
| 292 | 298 | .handler = { \ |
| 293 | 299 | .inval = invl, \ |
| 294 | 300 | .type = _typ, \ |
| ... | ... | @@ -297,10 +303,11 @@ OPCODES_SECTION static opcode_t opc_##name = { \ |
| 297 | 303 | } |
| 298 | 304 | |
| 299 | 305 | #define GEN_OPCODE_MARK(name) \ |
| 300 | -OPCODES_SECTION static opcode_t opc_##name = { \ | |
| 306 | +OPCODES_SECTION opcode_t opc_##name = { \ | |
| 301 | 307 | .opc1 = 0xFF, \ |
| 302 | 308 | .opc2 = 0xFF, \ |
| 303 | 309 | .opc3 = 0xFF, \ |
| 310 | + .pad = { 0, }, \ | |
| 304 | 311 | .handler = { \ |
| 305 | 312 | .inval = 0x00000000, \ |
| 306 | 313 | .type = 0x00, \ |
| ... | ... | @@ -361,7 +368,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
| 361 | 368 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
| 362 | 369 | gen_op_##name(); \ |
| 363 | 370 | if (Rc(ctx->opcode) != 0) \ |
| 364 | - gen_op_set_Rc0_ov(); \ | |
| 371 | + gen_op_set_Rc0(); \ | |
| 365 | 372 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
| 366 | 373 | } |
| 367 | 374 | |
| ... | ... | @@ -380,7 +387,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \ |
| 380 | 387 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 381 | 388 | gen_op_##name(); \ |
| 382 | 389 | if (Rc(ctx->opcode) != 0) \ |
| 383 | - gen_op_set_Rc0_ov(); \ | |
| 390 | + gen_op_set_Rc0(); \ | |
| 384 | 391 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
| 385 | 392 | } |
| 386 | 393 | |
| ... | ... | @@ -1558,7 +1565,7 @@ static inline void gen_bcond(DisasContext *ctx, int type) |
| 1558 | 1565 | gen_op_dec_ctr(); |
| 1559 | 1566 | switch(type) { |
| 1560 | 1567 | case BCOND_IM: |
| 1561 | - li = s_ext16(BD(ctx->opcode)); | |
| 1568 | + li = (int32_t)((int16_t)(BD(ctx->opcode))); | |
| 1562 | 1569 | if (AA(ctx->opcode) == 0) { |
| 1563 | 1570 | target = ctx->nip + li - 4; |
| 1564 | 1571 | } else { |
| ... | ... | @@ -2160,11 +2167,6 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
| 2160 | 2167 | case DECR: |
| 2161 | 2168 | gen_op_store_decr(); |
| 2162 | 2169 | break; |
| 2163 | -#if 0 | |
| 2164 | - case HID0: | |
| 2165 | - gen_op_store_hid0(); | |
| 2166 | - break; | |
| 2167 | -#endif | |
| 2168 | 2170 | default: |
| 2169 | 2171 | gen_op_store_spr(sprn); |
| 2170 | 2172 | break; |
| ... | ... | @@ -2894,7 +2896,7 @@ static ppc_def_t ppc_defs[] = |
| 2894 | 2896 | |
| 2895 | 2897 | static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
| 2896 | 2898 | { |
| 2897 | - opcode_t *opc; | |
| 2899 | + opcode_t *opc, *start, *end; | |
| 2898 | 2900 | int i, flags; |
| 2899 | 2901 | |
| 2900 | 2902 | fill_new_table(ppc_opcodes, 0x40); |
| ... | ... | @@ -2906,7 +2908,14 @@ static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
| 2906 | 2908 | } |
| 2907 | 2909 | } |
| 2908 | 2910 | |
| 2909 | - for (opc = &opc_start + 1; opc != &opc_end; opc++) { | |
| 2911 | + if (&opc_start < &opc_end) { | |
| 2912 | + start = &opc_start; | |
| 2913 | + end = &opc_end; | |
| 2914 | + } else { | |
| 2915 | + start = &opc_end; | |
| 2916 | + end = &opc_start; | |
| 2917 | + } | |
| 2918 | + for (opc = start + 1; opc != end; opc++) { | |
| 2910 | 2919 | if ((opc->handler.type & flags) != 0) |
| 2911 | 2920 | if (register_insn(ppc_opcodes, opc) < 0) { |
| 2912 | 2921 | printf("*** ERROR initializing PPC instruction " | ... | ... |