gwj / at91sam9263 · Commits

Commit 187337f8b0ec0813dd3876d1efe37d415fb81c2e

Authored by pbrook
1 parent 1bc012f6

Fix off-by-one memory region sizes. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2931 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 21 changed files with 39 additions and 39 deletions
hw/arm_gic.c
  View file @187337f
@@ -532,10 +532,10 @@ qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq) @@ -532,10 +532,10 @@ qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq)
532 if (base != 0xffffffff) { 532 if (base != 0xffffffff) {
533 iomemtype = cpu_register_io_memory(0, gic_cpu_readfn, 533 iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
534 gic_cpu_writefn, s); 534 gic_cpu_writefn, s);
535 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 535 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
536 iomemtype = cpu_register_io_memory(0, gic_dist_readfn, 536 iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
537 gic_dist_writefn, s); 537 gic_dist_writefn, s);
538 - cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype); 538 + cpu_register_physical_memory(base + 0x1000, 0x00001000, iomemtype);
539 s->base = base; 539 s->base = base;
540 } else { 540 } else {
541 s->base = 0; 541 s->base = 0;
hw/arm_sysctl.c
  View file @187337f
@@ -202,7 +202,7 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id) @@ -202,7 +202,7 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id)
202 s->sys_id = sys_id; 202 s->sys_id = sys_id;
203 iomemtype = cpu_register_io_memory(0, arm_sysctl_readfn, 203 iomemtype = cpu_register_io_memory(0, arm_sysctl_readfn,
204 arm_sysctl_writefn, s); 204 arm_sysctl_writefn, s);
205 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 205 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
206 /* ??? Save/restore. */ 206 /* ??? Save/restore. */
207 } 207 }
208 208
hw/arm_timer.c
  View file @187337f
@@ -233,7 +233,7 @@ void sp804_init(uint32_t base, qemu_irq irq) @@ -233,7 +233,7 @@ void sp804_init(uint32_t base, qemu_irq irq)
233 s->timer[1] = arm_timer_init(1000000, qi[1]); 233 s->timer[1] = arm_timer_init(1000000, qi[1]);
234 iomemtype = cpu_register_io_memory(0, sp804_readfn, 234 iomemtype = cpu_register_io_memory(0, sp804_readfn,
235 sp804_writefn, s); 235 sp804_writefn, s);
236 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 236 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
237 /* ??? Save/restore. */ 237 /* ??? Save/restore. */
238 } 238 }
239 239
@@ -301,7 +301,7 @@ void icp_pit_init(uint32_t base, qemu_irq *pic, int irq) @@ -301,7 +301,7 @@ void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
301 301
302 iomemtype = cpu_register_io_memory(0, icp_pit_readfn, 302 iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
303 icp_pit_writefn, s); 303 icp_pit_writefn, s);
304 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 304 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
305 /* ??? Save/restore. */ 305 /* ??? Save/restore. */
306 } 306 }
307 307
hw/integratorcp.c
  View file @187337f
@@ -257,7 +257,7 @@ static void integratorcm_init(int memsz, uint32_t flash_offset) @@ -257,7 +257,7 @@ static void integratorcm_init(int memsz, uint32_t flash_offset)
257 257
258 iomemtype = cpu_register_io_memory(0, integratorcm_readfn, 258 iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
259 integratorcm_writefn, s); 259 integratorcm_writefn, s);
260 - cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype); 260 + cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype);
261 integratorcm_do_remap(s, 1); 261 integratorcm_do_remap(s, 1);
262 /* ??? Save/restore. */ 262 /* ??? Save/restore. */
263 } 263 }
@@ -390,7 +390,7 @@ static qemu_irq *icp_pic_init(uint32_t base, @@ -390,7 +390,7 @@ static qemu_irq *icp_pic_init(uint32_t base,
390 s->parent_fiq = parent_fiq; 390 s->parent_fiq = parent_fiq;
391 iomemtype = cpu_register_io_memory(0, icp_pic_readfn, 391 iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
392 icp_pic_writefn, s); 392 icp_pic_writefn, s);
393 - cpu_register_physical_memory(base, 0x007fffff, iomemtype); 393 + cpu_register_physical_memory(base, 0x00800000, iomemtype);
394 /* ??? Save/restore. */ 394 /* ??? Save/restore. */
395 return qi; 395 return qi;
396 } 396 }
@@ -454,7 +454,7 @@ static void icp_control_init(uint32_t base) @@ -454,7 +454,7 @@ static void icp_control_init(uint32_t base)
454 s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state)); 454 s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
455 iomemtype = cpu_register_io_memory(0, icp_control_readfn, 455 iomemtype = cpu_register_io_memory(0, icp_control_readfn,
456 icp_control_writefn, s); 456 icp_control_writefn, s);
457 - cpu_register_physical_memory(base, 0x007fffff, iomemtype); 457 + cpu_register_physical_memory(base, 0x00800000, iomemtype);
458 s->base = base; 458 s->base = base;
459 /* ??? Save/restore. */ 459 /* ??? Save/restore. */
460 } 460 }
hw/pl011.c
  View file @187337f
@@ -232,7 +232,7 @@ void pl011_init(uint32_t base, qemu_irq irq, @@ -232,7 +232,7 @@ void pl011_init(uint32_t base, qemu_irq irq,
232 s = (pl011_state *)qemu_mallocz(sizeof(pl011_state)); 232 s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
233 iomemtype = cpu_register_io_memory(0, pl011_readfn, 233 iomemtype = cpu_register_io_memory(0, pl011_readfn,
234 pl011_writefn, s); 234 pl011_writefn, s);
235 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 235 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
236 s->base = base; 236 s->base = base;
237 s->irq = irq; 237 s->irq = irq;
238 s->chr = chr; 238 s->chr = chr;
hw/pl050.c
  View file @187337f
@@ -131,7 +131,7 @@ void pl050_init(uint32_t base, qemu_irq irq, int is_mouse) @@ -131,7 +131,7 @@ void pl050_init(uint32_t base, qemu_irq irq, int is_mouse)
131 s = (pl050_state *)qemu_mallocz(sizeof(pl050_state)); 131 s = (pl050_state *)qemu_mallocz(sizeof(pl050_state));
132 iomemtype = cpu_register_io_memory(0, pl050_readfn, 132 iomemtype = cpu_register_io_memory(0, pl050_readfn,
133 pl050_writefn, s); 133 pl050_writefn, s);
134 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 134 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
135 s->base = base; 135 s->base = base;
136 s->irq = irq; 136 s->irq = irq;
137 s->is_mouse = is_mouse; 137 s->is_mouse = is_mouse;
hw/pl080.c
  View file @187337f
@@ -332,7 +332,7 @@ void *pl080_init(uint32_t base, qemu_irq irq, int nchannels) @@ -332,7 +332,7 @@ void *pl080_init(uint32_t base, qemu_irq irq, int nchannels)
332 s = (pl080_state *)qemu_mallocz(sizeof(pl080_state)); 332 s = (pl080_state *)qemu_mallocz(sizeof(pl080_state));
333 iomemtype = cpu_register_io_memory(0, pl080_readfn, 333 iomemtype = cpu_register_io_memory(0, pl080_readfn,
334 pl080_writefn, s); 334 pl080_writefn, s);
335 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 335 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
336 s->base = base; 336 s->base = base;
337 s->irq = irq; 337 s->irq = irq;
338 s->nchannels = nchannels; 338 s->nchannels = nchannels;
hw/pl110.c
  View file @187337f
@@ -407,7 +407,7 @@ void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, @@ -407,7 +407,7 @@ void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
407 s = (pl110_state *)qemu_mallocz(sizeof(pl110_state)); 407 s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
408 iomemtype = cpu_register_io_memory(0, pl110_readfn, 408 iomemtype = cpu_register_io_memory(0, pl110_readfn,
409 pl110_writefn, s); 409 pl110_writefn, s);
410 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 410 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
411 s->base = base; 411 s->base = base;
412 s->ds = ds; 412 s->ds = ds;
413 s->versatile = versatile; 413 s->versatile = versatile;
hw/pl181.c
  View file @187337f
@@ -432,7 +432,7 @@ void pl181_init(uint32_t base, BlockDriverState *bd, @@ -432,7 +432,7 @@ void pl181_init(uint32_t base, BlockDriverState *bd,
432 s = (pl181_state *)qemu_mallocz(sizeof(pl181_state)); 432 s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
433 iomemtype = cpu_register_io_memory(0, pl181_readfn, 433 iomemtype = cpu_register_io_memory(0, pl181_readfn,
434 pl181_writefn, s); 434 pl181_writefn, s);
435 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 435 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
436 s->base = base; 436 s->base = base;
437 s->card = sd_init(bd); 437 s->card = sd_init(bd);
438 s->irq[0] = irq0; 438 s->irq[0] = irq0;
hw/pl190.c
  View file @187337f
@@ -239,7 +239,7 @@ qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq) @@ -239,7 +239,7 @@ qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq)
239 s = (pl190_state *)qemu_mallocz(sizeof(pl190_state)); 239 s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
240 iomemtype = cpu_register_io_memory(0, pl190_readfn, 240 iomemtype = cpu_register_io_memory(0, pl190_readfn,
241 pl190_writefn, s); 241 pl190_writefn, s);
242 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 242 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
243 qi = qemu_allocate_irqs(pl190_set_irq, s, 32); 243 qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
244 s->base = base; 244 s->base = base;
245 s->irq = irq; 245 s->irq = irq;
hw/pxa2xx.c
  View file @187337f
@@ -1725,7 +1725,7 @@ static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base, @@ -1725,7 +1725,7 @@ static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1725 1725
1726 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn, 1726 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1727 pxa2xx_i2s_writefn, s); 1727 pxa2xx_i2s_writefn, s);
1728 - cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype); 1728 + cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
1729 1729
1730 register_savevm("pxa2xx_i2s", base, 0, 1730 register_savevm("pxa2xx_i2s", base, 0,
1731 pxa2xx_i2s_save, pxa2xx_i2s_load, s); 1731 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
@@ -1988,7 +1988,7 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, @@ -1988,7 +1988,7 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1988 1988
1989 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn, 1989 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1990 pxa2xx_fir_writefn, s); 1990 pxa2xx_fir_writefn, s);
1991 - cpu_register_physical_memory(s->base, 0xfff, iomemtype); 1991 + cpu_register_physical_memory(s->base, 0x1000, iomemtype);
1992 1992
1993 if (chr) 1993 if (chr)
1994 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, 1994 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
@@ -2061,7 +2061,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, @@ -2061,7 +2061,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2061 s->clkcfg = 0x00000009; /* Turbo mode active */ 2061 s->clkcfg = 0x00000009; /* Turbo mode active */
2062 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, 2062 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2063 pxa2xx_cm_writefn, s); 2063 pxa2xx_cm_writefn, s);
2064 - cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); 2064 + cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2065 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); 2065 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2066 2066
2067 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); 2067 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@@ -2072,13 +2072,13 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, @@ -2072,13 +2072,13 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2072 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2072 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2073 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, 2073 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2074 pxa2xx_mm_writefn, s); 2074 pxa2xx_mm_writefn, s);
2075 - cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); 2075 + cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2076 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); 2076 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2077 2077
2078 s->pm_base = 0x40f00000; 2078 s->pm_base = 0x40f00000;
2079 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, 2079 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2080 pxa2xx_pm_writefn, s); 2080 pxa2xx_pm_writefn, s);
2081 - cpu_register_physical_memory(s->pm_base, 0xff, iomemtype); 2081 + cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2082 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); 2082 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2083 2083
2084 for (i = 0; pxa27x_ssp[i].io_base; i ++); 2084 for (i = 0; pxa27x_ssp[i].io_base; i ++);
@@ -2093,7 +2093,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, @@ -2093,7 +2093,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2093 2093
2094 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, 2094 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2095 pxa2xx_ssp_writefn, &ssp[i]); 2095 pxa2xx_ssp_writefn, &ssp[i]);
2096 - cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); 2096 + cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2097 register_savevm("pxa2xx_ssp", i, 0, 2097 register_savevm("pxa2xx_ssp", i, 0,
2098 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 2098 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2099 } 2099 }
@@ -2108,7 +2108,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, @@ -2108,7 +2108,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2108 s->rtc_base = 0x40900000; 2108 s->rtc_base = 0x40900000;
2109 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, 2109 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2110 pxa2xx_rtc_writefn, s); 2110 pxa2xx_rtc_writefn, s);
2111 - cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); 2111 + cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2112 pxa2xx_rtc_init(s); 2112 pxa2xx_rtc_init(s);
2113 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s); 2113 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2114 2114
@@ -2170,7 +2170,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, @@ -2170,7 +2170,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2170 s->clkcfg = 0x00000009; /* Turbo mode active */ 2170 s->clkcfg = 0x00000009; /* Turbo mode active */
2171 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, 2171 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2172 pxa2xx_cm_writefn, s); 2172 pxa2xx_cm_writefn, s);
2173 - cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); 2173 + cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2174 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); 2174 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2175 2175
2176 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); 2176 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
@@ -2181,13 +2181,13 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, @@ -2181,13 +2181,13 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2181 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ 2181 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2182 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, 2182 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2183 pxa2xx_mm_writefn, s); 2183 pxa2xx_mm_writefn, s);
2184 - cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); 2184 + cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2185 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); 2185 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2186 2186
2187 s->pm_base = 0x40f00000; 2187 s->pm_base = 0x40f00000;
2188 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, 2188 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2189 pxa2xx_pm_writefn, s); 2189 pxa2xx_pm_writefn, s);
2190 - cpu_register_physical_memory(s->pm_base, 0xff, iomemtype); 2190 + cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2191 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); 2191 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2192 2192
2193 for (i = 0; pxa255_ssp[i].io_base; i ++); 2193 for (i = 0; pxa255_ssp[i].io_base; i ++);
@@ -2202,7 +2202,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, @@ -2202,7 +2202,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2202 2202
2203 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, 2203 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2204 pxa2xx_ssp_writefn, &ssp[i]); 2204 pxa2xx_ssp_writefn, &ssp[i]);
2205 - cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); 2205 + cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2206 register_savevm("pxa2xx_ssp", i, 0, 2206 register_savevm("pxa2xx_ssp", i, 0,
2207 pxa2xx_ssp_save, pxa2xx_ssp_load, s); 2207 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2208 } 2208 }
@@ -2217,7 +2217,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, @@ -2217,7 +2217,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2217 s->rtc_base = 0x40900000; 2217 s->rtc_base = 0x40900000;
2218 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, 2218 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2219 pxa2xx_rtc_writefn, s); 2219 pxa2xx_rtc_writefn, s);
2220 - cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); 2220 + cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2221 pxa2xx_rtc_init(s); 2221 pxa2xx_rtc_init(s);
2222 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s); 2222 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2223 2223
hw/pxa2xx_dma.c
  View file @187337f
@@ -508,7 +508,7 @@ static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base, @@ -508,7 +508,7 @@ static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base,
508 508
509 iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn, 509 iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn,
510 pxa2xx_dma_writefn, s); 510 pxa2xx_dma_writefn, s);
511 - cpu_register_physical_memory(base, 0x0000ffff, iomemtype); 511 + cpu_register_physical_memory(base, 0x00010000, iomemtype);
512 512
513 register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); 513 register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
514 514
hw/pxa2xx_gpio.c
  View file @187337f
@@ -308,7 +308,7 @@ struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, @@ -308,7 +308,7 @@ struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
308 308
309 iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn, 309 iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
310 pxa2xx_gpio_writefn, s); 310 pxa2xx_gpio_writefn, s);
311 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 311 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
312 312
313 register_savevm("pxa2xx_gpio", 0, 0, 313 register_savevm("pxa2xx_gpio", 0, 0,
314 pxa2xx_gpio_save, pxa2xx_gpio_load, s); 314 pxa2xx_gpio_save, pxa2xx_gpio_load, s);
hw/pxa2xx_lcd.c
  View file @187337f
@@ -1026,7 +1026,7 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq, @@ -1026,7 +1026,7 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
1026 1026
1027 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn, 1027 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
1028 pxa2xx_lcdc_writefn, s); 1028 pxa2xx_lcdc_writefn, s);
1029 - cpu_register_physical_memory(base, 0x000fffff, iomemtype); 1029 + cpu_register_physical_memory(base, 0x00100000, iomemtype);
1030 1030
1031 graphic_console_init(ds, pxa2xx_update_display, 1031 graphic_console_init(ds, pxa2xx_update_display,
1032 pxa2xx_invalidate_display, pxa2xx_screen_dump, s); 1032 pxa2xx_invalidate_display, pxa2xx_screen_dump, s);
hw/pxa2xx_mmci.c
  View file @187337f
@@ -534,7 +534,7 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, @@ -534,7 +534,7 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
534 534
535 iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn, 535 iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
536 pxa2xx_mmci_writefn, s); 536 pxa2xx_mmci_writefn, s);
537 - cpu_register_physical_memory(base, 0x000fffff, iomemtype); 537 + cpu_register_physical_memory(base, 0x00100000, iomemtype);
538 538
539 /* Instantiate the actual storage */ 539 /* Instantiate the actual storage */
540 s->card = sd_init(sd_bdrv); 540 s->card = sd_init(sd_bdrv);
hw/pxa2xx_pcmcia.c
  View file @187337f
@@ -149,7 +149,7 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base) @@ -149,7 +149,7 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base)
149 s->io_base = base | 0x00000000; 149 s->io_base = base | 0x00000000;
150 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn, 150 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn,
151 pxa2xx_pcmcia_io_writefn, s); 151 pxa2xx_pcmcia_io_writefn, s);
152 - cpu_register_physical_memory(s->io_base, 0x03ffffff, iomemtype); 152 + cpu_register_physical_memory(s->io_base, 0x04000000, iomemtype);
153 153
154 /* Then next 64 MB is reserved */ 154 /* Then next 64 MB is reserved */
155 155
@@ -157,13 +157,13 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base) @@ -157,13 +157,13 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base)
157 s->attr_base = base | 0x08000000; 157 s->attr_base = base | 0x08000000;
158 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn, 158 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn,
159 pxa2xx_pcmcia_attr_writefn, s); 159 pxa2xx_pcmcia_attr_writefn, s);
160 - cpu_register_physical_memory(s->attr_base, 0x03ffffff, iomemtype); 160 + cpu_register_physical_memory(s->attr_base, 0x04000000, iomemtype);
161 161
162 /* Socket Common Memory Space */ 162 /* Socket Common Memory Space */
163 s->common_base = base | 0x0c000000; 163 s->common_base = base | 0x0c000000;
164 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn, 164 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn,
165 pxa2xx_pcmcia_common_writefn, s); 165 pxa2xx_pcmcia_common_writefn, s);
166 - cpu_register_physical_memory(s->common_base, 0x03ffffff, iomemtype); 166 + cpu_register_physical_memory(s->common_base, 0x04000000, iomemtype);
167 167
168 if (base == 0x30000000) 168 if (base == 0x30000000)
169 s->slot.slot_string = "PXA PC Card Socket 1"; 169 s->slot.slot_string = "PXA PC Card Socket 1";
hw/pxa2xx_pic.c
  View file @187337f
@@ -306,7 +306,7 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) @@ -306,7 +306,7 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
306 /* Enable IC memory-mapped registers access. */ 306 /* Enable IC memory-mapped registers access. */
307 iomemtype = cpu_register_io_memory(0, pxa2xx_pic_readfn, 307 iomemtype = cpu_register_io_memory(0, pxa2xx_pic_readfn,
308 pxa2xx_pic_writefn, s); 308 pxa2xx_pic_writefn, s);
309 - cpu_register_physical_memory(base, 0x000fffff, iomemtype); 309 + cpu_register_physical_memory(base, 0x00100000, iomemtype);
310 310
311 /* Enable IC coprocessor access. */ 311 /* Enable IC coprocessor access. */
312 cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); 312 cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
hw/pxa2xx_timer.c
  View file @187337f
@@ -458,7 +458,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, @@ -458,7 +458,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
458 458
459 iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn, 459 iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
460 pxa2xx_timer_writefn, s); 460 pxa2xx_timer_writefn, s);
461 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 461 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
462 462
463 register_savevm("pxa2xx_timer", 0, 0, 463 register_savevm("pxa2xx_timer", 0, 0,
464 pxa2xx_timer_save, pxa2xx_timer_load, s); 464 pxa2xx_timer_save, pxa2xx_timer_load, s);
hw/spitz.c
  View file @187337f
@@ -705,7 +705,7 @@ static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu, @@ -705,7 +705,7 @@ static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
705 705
706 iomemtype = cpu_register_io_memory(0, scoop_readfn, 706 iomemtype = cpu_register_io_memory(0, scoop_readfn,
707 scoop_writefn, &s[0]); 707 scoop_writefn, &s[0]);
708 - cpu_register_physical_memory(s[0].target_base, 0xfff, iomemtype); 708 + cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
709 register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]); 709 register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
710 710
711 if (count < 2) 711 if (count < 2)
@@ -713,7 +713,7 @@ static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu, @@ -713,7 +713,7 @@ static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
713 713
714 iomemtype = cpu_register_io_memory(0, scoop_readfn, 714 iomemtype = cpu_register_io_memory(0, scoop_readfn,
715 scoop_writefn, &s[1]); 715 scoop_writefn, &s[1]);
716 - cpu_register_physical_memory(s[1].target_base, 0xfff, iomemtype); 716 + cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
717 register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]); 717 register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
718 718
719 return s; 719 return s;
hw/usb-ohci.c
  View file @187337f
@@ -1345,5 +1345,5 @@ void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, @@ -1345,5 +1345,5 @@ void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
1345 OHCI_TYPE_PXA, "OHCI USB"); 1345 OHCI_TYPE_PXA, "OHCI USB");
1346 ohci->mem_base = base; 1346 ohci->mem_base = base;
1347 1347
1348 - cpu_register_physical_memory(ohci->mem_base, 0xfff, ohci->mem); 1348 + cpu_register_physical_memory(ohci->mem_base, 0x1000, ohci->mem);
1349 } 1349 }
hw/versatilepb.c
  View file @187337f
@@ -140,7 +140,7 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq) @@ -140,7 +140,7 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
140 s->irq = irq; 140 s->irq = irq;
141 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn, 141 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
142 vpb_sic_writefn, s); 142 vpb_sic_writefn, s);
143 - cpu_register_physical_memory(base, 0x00000fff, iomemtype); 143 + cpu_register_physical_memory(base, 0x00001000, iomemtype);
144 /* ??? Save/restore. */ 144 /* ??? Save/restore. */
145 return qi; 145 return qi;
146 } 146 }