gwj / at91sam9263 · Commits

Commit 171b31e7c7b771dc9e20fcb8305fc330ee59c7a6

Authored by ths
1 parent 80c27194

Don't use T2 for INS, it conflicts with branch delay slot handling. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2674 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 6 additions and 6 deletions
target-mips/op.c
  View file @171b31e
@@ -2234,7 +2234,7 @@ void op_ins(void) @@ -2234,7 +2234,7 @@ void op_ins(void)
2234 unsigned int size = PARAM2; 2234 unsigned int size = PARAM2;
2235 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; 2235 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2236 2236
2237 - T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask); 2237 + T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
2238 RETURN(); 2238 RETURN();
2239 } 2239 }
2240 2240
@@ -2260,7 +2260,7 @@ void op_dins(void) @@ -2260,7 +2260,7 @@ void op_dins(void)
2260 unsigned int size = PARAM2; 2260 unsigned int size = PARAM2;
2261 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; 2261 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2262 2262
2263 - T0 = (T2 & ~mask) | ((T1 << pos) & mask); 2263 + T0 = (T0 & ~mask) | ((T1 << pos) & mask);
2264 RETURN(); 2264 RETURN();
2265 } 2265 }
2266 2266
target-mips/translate.c
  View file @171b31e
@@ -1722,25 +1722,25 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, @@ -1722,25 +1722,25 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
1722 case OPC_INS: 1722 case OPC_INS:
1723 if (lsb > msb) 1723 if (lsb > msb)
1724 goto fail; 1724 goto fail;
1725 - GEN_LOAD_REG_TN(T2, rt); 1725 + GEN_LOAD_REG_TN(T0, rt);
1726 gen_op_ins(lsb, msb - lsb + 1); 1726 gen_op_ins(lsb, msb - lsb + 1);
1727 break; 1727 break;
1728 case OPC_DINSM: 1728 case OPC_DINSM:
1729 if (lsb > msb) 1729 if (lsb > msb)
1730 goto fail; 1730 goto fail;
1731 - GEN_LOAD_REG_TN(T2, rt); 1731 + GEN_LOAD_REG_TN(T0, rt);
1732 gen_op_ins(lsb, msb - lsb + 1 + 32); 1732 gen_op_ins(lsb, msb - lsb + 1 + 32);
1733 break; 1733 break;
1734 case OPC_DINSU: 1734 case OPC_DINSU:
1735 if (lsb > msb) 1735 if (lsb > msb)
1736 goto fail; 1736 goto fail;
1737 - GEN_LOAD_REG_TN(T2, rt); 1737 + GEN_LOAD_REG_TN(T0, rt);
1738 gen_op_ins(lsb + 32, msb - lsb + 1); 1738 gen_op_ins(lsb + 32, msb - lsb + 1);
1739 break; 1739 break;
1740 case OPC_DINS: 1740 case OPC_DINS:
1741 if (lsb > msb) 1741 if (lsb > msb)
1742 goto fail; 1742 goto fail;
1743 - GEN_LOAD_REG_TN(T2, rt); 1743 + GEN_LOAD_REG_TN(T0, rt);
1744 gen_op_ins(lsb, msb - lsb + 1); 1744 gen_op_ins(lsb, msb - lsb + 1);
1745 break; 1745 break;
1746 default: 1746 default: