Commit 17044c06b846e84191534a8a8f8bdc56a2b2e619
1 parent
7bfd934a
Allow emulation of 32bit targets in the MIPS64 capable qemu version.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3007 c046a42c-6fe2-441c-8c8c-71466251a162
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2 deletions
target-mips/translate_init.c
| @@ -77,7 +77,6 @@ struct mips_def_t { | @@ -77,7 +77,6 @@ struct mips_def_t { | ||
| 77 | /* MIPS CPU definitions */ | 77 | /* MIPS CPU definitions */ |
| 78 | static mips_def_t mips_defs[] = | 78 | static mips_def_t mips_defs[] = |
| 79 | { | 79 | { |
| 80 | -#ifndef TARGET_MIPS64 | ||
| 81 | { | 80 | { |
| 82 | .name = "4Kc", | 81 | .name = "4Kc", |
| 83 | .CP0_PRid = 0x00018000, | 82 | .CP0_PRid = 0x00018000, |
| @@ -135,7 +134,7 @@ static mips_def_t mips_defs[] = | @@ -135,7 +134,7 @@ static mips_def_t mips_defs[] = | ||
| 135 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | | 134 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 136 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), | 135 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 137 | }, | 136 | }, |
| 138 | -#else | 137 | +#ifdef TARGET_MIPS64 |
| 139 | { | 138 | { |
| 140 | .name = "R4000", | 139 | .name = "R4000", |
| 141 | .CP0_PRid = 0x00000400, | 140 | .CP0_PRid = 0x00000400, |