Commit 16f62432c4985fa732c0c7dd63761b06f076a48f
1 parent
8b1f24b0
DMA API change
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@646 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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23 additions
and
33 deletions
hw/dma.c
| ... | ... | @@ -39,7 +39,6 @@ |
| 39 | 39 | #define ldebug(...) |
| 40 | 40 | #endif |
| 41 | 41 | |
| 42 | -#define MEM_REAL(addr) ((addr)+(uint32_t)(phys_ram_base)) | |
| 43 | 42 | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
| 44 | 43 | |
| 45 | 44 | struct dma_regs { |
| ... | ... | @@ -49,8 +48,8 @@ struct dma_regs { |
| 49 | 48 | uint8_t page; |
| 50 | 49 | uint8_t dack; |
| 51 | 50 | uint8_t eop; |
| 52 | - DMA_read_handler read_handler; | |
| 53 | - DMA_misc_handler misc_handler; | |
| 51 | + DMA_transfer_handler transfer_handler; | |
| 52 | + void *opaque; | |
| 54 | 53 | }; |
| 55 | 54 | |
| 56 | 55 | #define ADDR 0 |
| ... | ... | @@ -284,40 +283,27 @@ static void channel_run (int ncont, int ichan) |
| 284 | 283 | { |
| 285 | 284 | struct dma_regs *r; |
| 286 | 285 | int n; |
| 287 | - int irq; | |
| 288 | - uint32_t addr; | |
| 286 | + target_ulong addr; | |
| 289 | 287 | /* int ai, dir; */ |
| 290 | 288 | |
| 291 | 289 | r = dma_controllers[ncont].regs + ichan; |
| 292 | 290 | /* ai = r->mode & 16; */ |
| 293 | 291 | /* dir = r->mode & 32 ? -1 : 1; */ |
| 294 | 292 | |
| 295 | - addr = MEM_REAL ((r->page << 16) | r->now[ADDR]); | |
| 296 | - | |
| 297 | - irq = -1; | |
| 298 | - n = r->read_handler (addr, (r->base[COUNT] << ncont) + (1 << ncont), &irq); | |
| 293 | + addr = (r->page << 16) | r->now[ADDR]; | |
| 294 | + n = r->transfer_handler (r->opaque, addr, | |
| 295 | + (r->base[COUNT] << ncont) + (1 << ncont)); | |
| 299 | 296 | r->now[COUNT] = n; |
| 300 | 297 | |
| 301 | - ldebug ("dma_pos %d irq %d size %d\n", | |
| 302 | - n, irq, (r->base[1] << ncont) + (1 << ncont)); | |
| 303 | - | |
| 304 | - if (-1 != irq) { | |
| 305 | - pic_set_irq (irq, 1); | |
| 306 | - } | |
| 298 | + ldebug ("dma_pos %d size %d\n", | |
| 299 | + n, (r->base[1] << ncont) + (1 << ncont)); | |
| 307 | 300 | } |
| 308 | 301 | |
| 309 | 302 | void DMA_run (void) |
| 310 | 303 | { |
| 311 | - static int in_dma; | |
| 312 | 304 | struct dma_cont *d; |
| 313 | 305 | int icont, ichan; |
| 314 | 306 | |
| 315 | - if (in_dma) { | |
| 316 | - log ("attempt to re-enter dma\n"); | |
| 317 | - return; | |
| 318 | - } | |
| 319 | - | |
| 320 | - in_dma = 1; | |
| 321 | 307 | d = dma_controllers; |
| 322 | 308 | |
| 323 | 309 | for (icont = 0; icont < 2; icont++, d++) { |
| ... | ... | @@ -330,12 +316,11 @@ void DMA_run (void) |
| 330 | 316 | channel_run (icont, ichan); |
| 331 | 317 | } |
| 332 | 318 | } |
| 333 | - in_dma = 0; | |
| 334 | 319 | } |
| 335 | 320 | |
| 336 | 321 | void DMA_register_channel (int nchan, |
| 337 | - DMA_read_handler read_handler, | |
| 338 | - DMA_misc_handler misc_handler) | |
| 322 | + DMA_transfer_handler transfer_handler, | |
| 323 | + void *opaque) | |
| 339 | 324 | { |
| 340 | 325 | struct dma_regs *r; |
| 341 | 326 | int ichan, ncont; |
| ... | ... | @@ -344,8 +329,14 @@ void DMA_register_channel (int nchan, |
| 344 | 329 | ichan = nchan & 3; |
| 345 | 330 | |
| 346 | 331 | r = dma_controllers[ncont].regs + ichan; |
| 347 | - r->read_handler = read_handler; | |
| 348 | - r->misc_handler = misc_handler; | |
| 332 | + r->transfer_handler = transfer_handler; | |
| 333 | + r->opaque = opaque; | |
| 334 | +} | |
| 335 | + | |
| 336 | +/* request the emulator to transfer a new DMA memory block ASAP */ | |
| 337 | +void DMA_schedule(int nchan) | |
| 338 | +{ | |
| 339 | + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); | |
| 349 | 340 | } |
| 350 | 341 | |
| 351 | 342 | void DMA_init (void) | ... | ... |
vl.h
| ... | ... | @@ -24,8 +24,9 @@ |
| 24 | 24 | #ifndef VL_H |
| 25 | 25 | #define VL_H |
| 26 | 26 | |
| 27 | +#include "cpu.h" | |
| 28 | + | |
| 27 | 29 | /* vl.c */ |
| 28 | -struct CPUState; | |
| 29 | 30 | extern int reset_requested; |
| 30 | 31 | extern int64_t ticks_per_sec; |
| 31 | 32 | |
| ... | ... | @@ -128,17 +129,15 @@ int AUD_get_buffer_size (void); |
| 128 | 129 | void AUD_init (void); |
| 129 | 130 | |
| 130 | 131 | /* dma.c */ |
| 131 | -typedef int (*DMA_read_handler) (uint32_t addr, int size, int *irq); | |
| 132 | -typedef int (*DMA_misc_handler) (int); | |
| 133 | - | |
| 132 | +typedef int (*DMA_transfer_handler) (void *opaque, target_ulong addr, int size); | |
| 134 | 133 | int DMA_get_channel_mode (int nchan); |
| 135 | 134 | void DMA_hold_DREQ (int nchan); |
| 136 | 135 | void DMA_release_DREQ (int nchan); |
| 136 | +void DMA_schedule(int nchan); | |
| 137 | 137 | void DMA_run (void); |
| 138 | 138 | void DMA_init (void); |
| 139 | 139 | void DMA_register_channel (int nchan, |
| 140 | - DMA_read_handler read_handler, | |
| 141 | - DMA_misc_handler misc_handler); | |
| 140 | + DMA_transfer_handler transfer_handler, void *opaque); | |
| 142 | 141 | |
| 143 | 142 | /* sb16.c */ |
| 144 | 143 | void SB16_run (void); | ... | ... |