Commit 1569fc29ef60fa1972115860b420fb40d238fac5

Authored by blueswir1
1 parent 36cbaae5

Fix Slavio interrupt controller debugging output


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3112 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 4 additions and 4 deletions
hw/slavio_intctl.c
@@ -84,7 +84,7 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) @@ -84,7 +84,7 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
84 ret = 0; 84 ret = 0;
85 break; 85 break;
86 } 86 }
87 - DPRINTF("read cpu %d reg 0x%x = %x\n", addr, ret); 87 + DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
88 88
89 return ret; 89 return ret;
90 } 90 }
@@ -97,7 +97,7 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint @@ -97,7 +97,7 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
97 97
98 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; 98 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
99 saddr = (addr & INTCTL_MAXADDR) >> 2; 99 saddr = (addr & INTCTL_MAXADDR) >> 2;
100 - DPRINTF("write cpu %d reg 0x%x = %x\n", cpu, addr, val); 100 + DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
101 switch (saddr) { 101 switch (saddr) {
102 case 1: // clear pending softints 102 case 1: // clear pending softints
103 if (val & 0x4000) 103 if (val & 0x4000)
@@ -151,7 +151,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) @@ -151,7 +151,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
151 ret = 0; 151 ret = 0;
152 break; 152 break;
153 } 153 }
154 - DPRINTF("read system reg 0x%x = %x\n", addr, ret); 154 + DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
155 155
156 return ret; 156 return ret;
157 } 157 }
@@ -162,7 +162,7 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin @@ -162,7 +162,7 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
162 uint32_t saddr; 162 uint32_t saddr;
163 163
164 saddr = (addr & INTCTLM_MASK) >> 2; 164 saddr = (addr & INTCTLM_MASK) >> 2;
165 - DPRINTF("write system reg 0x%x = %x\n", addr, val); 165 + DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
166 switch (saddr) { 166 switch (saddr) {
167 case 2: // clear (enable) 167 case 2: // clear (enable)
168 // Force clear unused bits 168 // Force clear unused bits