Commit 1304ca878a4e091c193bd4ae273e0b5cb6142237
1 parent
f49e58dc
target-alpha: Fix ret instruction
Hopefully pine doesn't corrupt this patch, I've had problems recently.
For an alpha "ret" instruction, of the type
ret $26
The return was being ignored. This is because in translate.c
register $26 (the return address) was being over-written with the current
PC before it could be jumped to. Thus the ret was ignored.
This patch just re-orders things so the return address is processed before
it is over-written with the current PC.
(Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5638 c046a42c-6fe2-441c-8c8c-71466251a162
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2 additions
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2 deletions
target-alpha/translate.c
| ... | ... | @@ -1634,12 +1634,12 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
| 1634 | 1634 | break; |
| 1635 | 1635 | #endif |
| 1636 | 1636 | case 0x1A: |
| 1637 | - if (ra != 31) | |
| 1638 | - tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); | |
| 1639 | 1637 | if (rb != 31) |
| 1640 | 1638 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3); |
| 1641 | 1639 | else |
| 1642 | 1640 | tcg_gen_movi_i64(cpu_pc, 0); |
| 1641 | + if (ra != 31) | |
| 1642 | + tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); | |
| 1643 | 1643 | /* Those four jumps only differ by the branch prediction hint */ |
| 1644 | 1644 | switch (fn2) { |
| 1645 | 1645 | case 0x0: | ... | ... |