gwj / at91sam9263 · Commits

Commit 11e0fc3fd0be860f54c543c7ac1a9a7242a7ba26

Authored by balrog
1 parent 982f3ab6

Use pointers to channels rather than channel numbers in the DMA. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3789 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 390 additions and 363 deletions
hw/omap.c
  View file @11e0fc3
@@ -446,6 +446,9 @@ struct omap_dma_channel_s { @@ -446,6 +446,9 @@ struct omap_dma_channel_s {
446 /* compatibility */ 446 /* compatibility */
447 int omap_3_1_compatible_disable; 447 int omap_3_1_compatible_disable;
448 448
  449 + qemu_irq irq;
  450 + struct omap_dma_channel_s *sibling;
  451 +
449 struct omap_dma_reg_set_s { 452 struct omap_dma_reg_set_s {
450 target_phys_addr_t src, dest; 453 target_phys_addr_t src, dest;
451 int frame; 454 int frame;
@@ -463,7 +466,6 @@ struct omap_dma_channel_s { @@ -463,7 +466,6 @@ struct omap_dma_channel_s {
463 }; 466 };
464 467
465 struct omap_dma_s { 468 struct omap_dma_s {
466 - qemu_irq irqs[16];  
467 QEMUTimer *tm; 469 QEMUTimer *tm;
468 struct omap_mpu_state_s *mpu; 470 struct omap_mpu_state_s *mpu;
469 target_phys_addr_t base; 471 target_phys_addr_t base;
@@ -490,96 +492,81 @@ struct omap_dma_s { @@ -490,96 +492,81 @@ struct omap_dma_s {
490 #define END_BLOCK_INTR (1 << 5) 492 #define END_BLOCK_INTR (1 << 5)
491 #define SYNC (1 << 6) 493 #define SYNC (1 << 6)
492 494
493 -static int omap_dma_get_sibling_channel(struct omap_dma_s *s, int channel)  
494 -{  
495 - if (s->omap_3_1_mapping_disabled)  
496 - return -1;  
497 - switch (channel) {  
498 - case 0 ... 2:  
499 - return channel + 6;  
500 - case 6 ... 8:  
501 - return channel % 6;  
502 - }  
503 - return -1;  
504 -}  
505 -  
506 static void omap_dma_interrupts_update(struct omap_dma_s *s) 495 static void omap_dma_interrupts_update(struct omap_dma_s *s)
507 { 496 {
508 - int i, sibiling, raise; 497 + struct omap_dma_channel_s *ch = s->ch;
  498 + int i;
509 499
510 if (s->omap_3_1_mapping_disabled) { 500 if (s->omap_3_1_mapping_disabled) {
511 - for (i = 0; i < s->chans; i ++) {  
512 - if (s->ch[i].status)  
513 - qemu_irq_raise(s->irqs[i]);  
514 - } 501 + for (i = 0; i < s->chans; i ++, ch ++)
  502 + if (ch->status)
  503 + qemu_irq_raise(ch->irq);
515 } else { 504 } else {
516 /* First three interrupts are shared between two channels each. */ 505 /* First three interrupts are shared between two channels each. */
517 - for (i = 0; i < 6; i ++) {  
518 - raise = s->ch[i].status;  
519 - sibiling = omap_dma_get_sibling_channel(s, i);  
520 - if (sibiling != -1)  
521 - raise |= s->ch[sibiling].status;  
522 - if (raise)  
523 - qemu_irq_raise(s->irqs[i]); 506 + for (i = 0; i < 6; i ++, ch ++) {
  507 + if (ch->status || (ch->sibling && ch->sibling->status))
  508 + qemu_irq_raise(ch->irq);
524 } 509 }
525 } 510 }
526 } 511 }
527 512
528 -static void omap_dma_channel_load(struct omap_dma_s *s, int ch) 513 +static void omap_dma_channel_load(struct omap_dma_s *s,
  514 + struct omap_dma_channel_s *ch)
529 { 515 {
530 - struct omap_dma_reg_set_s *a = &s->ch[ch].active_set; 516 + struct omap_dma_reg_set_s *a = &ch->active_set;
531 int i; 517 int i;
532 - int omap_3_1 = !s->ch[ch].omap_3_1_compatible_disable; 518 + int omap_3_1 = !ch->omap_3_1_compatible_disable;
533 519
534 /* 520 /*
535 * TODO: verify address ranges and alignment 521 * TODO: verify address ranges and alignment
536 * TODO: port endianness 522 * TODO: port endianness
537 */ 523 */
538 524
539 - a->src = s->ch[ch].addr[0];  
540 - a->dest = s->ch[ch].addr[1];  
541 - a->frames = s->ch[ch].frames;  
542 - a->elements = s->ch[ch].elements; 525 + a->src = ch->addr[0];
  526 + a->dest = ch->addr[1];
  527 + a->frames = ch->frames;
  528 + a->elements = ch->elements;
543 a->frame = 0; 529 a->frame = 0;
544 a->element = 0; 530 a->element = 0;
545 531
546 - if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) { 532 + if (unlikely(!ch->elements || !ch->frames)) {
547 printf("%s: bad DMA request\n", __FUNCTION__); 533 printf("%s: bad DMA request\n", __FUNCTION__);
548 return; 534 return;
549 } 535 }
550 536
551 for (i = 0; i < 2; i ++) 537 for (i = 0; i < 2; i ++)
552 - switch (s->ch[ch].mode[i]) { 538 + switch (ch->mode[i]) {
553 case constant: 539 case constant:
554 a->elem_delta[i] = 0; 540 a->elem_delta[i] = 0;
555 a->frame_delta[i] = 0; 541 a->frame_delta[i] = 0;
556 break; 542 break;
557 case post_incremented: 543 case post_incremented:
558 - a->elem_delta[i] = s->ch[ch].data_type; 544 + a->elem_delta[i] = ch->data_type;
559 a->frame_delta[i] = 0; 545 a->frame_delta[i] = 0;
560 break; 546 break;
561 case single_index: 547 case single_index:
562 - a->elem_delta[i] = s->ch[ch].data_type +  
563 - s->ch[ch].element_index[omap_3_1 ? 0 : i] - 1; 548 + a->elem_delta[i] = ch->data_type +
  549 + ch->element_index[omap_3_1 ? 0 : i] - 1;
564 a->frame_delta[i] = 0; 550 a->frame_delta[i] = 0;
565 break; 551 break;
566 case double_index: 552 case double_index:
567 - a->elem_delta[i] = s->ch[ch].data_type +  
568 - s->ch[ch].element_index[omap_3_1 ? 0 : i] - 1;  
569 - a->frame_delta[i] = s->ch[ch].frame_index[omap_3_1 ? 0 : i] -  
570 - s->ch[ch].element_index[omap_3_1 ? 0 : i]; 553 + a->elem_delta[i] = ch->data_type +
  554 + ch->element_index[omap_3_1 ? 0 : i] - 1;
  555 + a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
  556 + ch->element_index[omap_3_1 ? 0 : i];
571 break; 557 break;
572 default: 558 default:
573 break; 559 break;
574 } 560 }
575 } 561 }
576 562
577 -static void omap_dma_activate_channel(struct omap_dma_s *s, int channel) 563 +static void omap_dma_activate_channel(struct omap_dma_s *s,
  564 + struct omap_dma_channel_s *ch)
578 { 565 {
579 - if (!s->ch[channel].active) {  
580 - s->ch[channel].active = 1;  
581 - if (s->ch[channel].sync)  
582 - s->ch[channel].status |= SYNC; 566 + if (!ch->active) {
  567 + ch->active = 1;
  568 + if (ch->sync)
  569 + ch->status |= SYNC;
583 s->run_count ++; 570 s->run_count ++;
584 } 571 }
585 572
@@ -587,26 +574,26 @@ static void omap_dma_activate_channel(struct omap_dma_s *s, int channel) @@ -587,26 +574,26 @@ static void omap_dma_activate_channel(struct omap_dma_s *s, int channel)
587 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); 574 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
588 } 575 }
589 576
590 -static void omap_dma_deactivate_channel(struct omap_dma_s *s, int channel) 577 +static void omap_dma_deactivate_channel(struct omap_dma_s *s,
  578 + struct omap_dma_channel_s *ch)
591 { 579 {
592 /* Update cpc */ 580 /* Update cpc */
593 - s->ch[channel].cpc = s->ch[channel].active_set.dest & 0xffff; 581 + ch->cpc = ch->active_set.dest & 0xffff;
594 582
595 - if (s->ch[channel].pending_request &&  
596 - !s->ch[channel].waiting_end_prog) { 583 + if (ch->pending_request && !ch->waiting_end_prog) {
597 /* Don't deactivate the channel */ 584 /* Don't deactivate the channel */
598 - s->ch[channel].pending_request = 0; 585 + ch->pending_request = 0;
599 return; 586 return;
600 } 587 }
601 588
602 /* Don't deactive the channel if it is synchronized and the DMA request is 589 /* Don't deactive the channel if it is synchronized and the DMA request is
603 active */ 590 active */
604 - if (s->ch[channel].sync && (s->drq & (1 << s->ch[channel].sync))) 591 + if (ch->sync && (s->drq & (1 << ch->sync)))
605 return; 592 return;
606 593
607 - if (s->ch[channel].active) {  
608 - s->ch[channel].active = 0;  
609 - s->ch[channel].status &= ~SYNC; 594 + if (ch->active) {
  595 + ch->active = 0;
  596 + ch->status &= ~SYNC;
610 s->run_count --; 597 s->run_count --;
611 } 598 }
612 599
@@ -614,34 +601,37 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s, int channel) @@ -614,34 +601,37 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s, int channel)
614 qemu_del_timer(s->tm); 601 qemu_del_timer(s->tm);
615 } 602 }
616 603
617 -static void omap_dma_enable_channel(struct omap_dma_s *s, int channel) 604 +static void omap_dma_enable_channel(struct omap_dma_s *s,
  605 + struct omap_dma_channel_s *ch)
618 { 606 {
619 - if (!s->ch[channel].enable) {  
620 - s->ch[channel].enable = 1;  
621 - s->ch[channel].waiting_end_prog = 0;  
622 - omap_dma_channel_load(s, channel);  
623 - if ((!s->ch[channel].sync) || (s->drq & (1 << s->ch[channel].sync)))  
624 - omap_dma_activate_channel(s, channel); 607 + if (!ch->enable) {
  608 + ch->enable = 1;
  609 + ch->waiting_end_prog = 0;
  610 + omap_dma_channel_load(s, ch);
  611 + if ((!ch->sync) || (s->drq & (1 << ch->sync)))
  612 + omap_dma_activate_channel(s, ch);
625 } 613 }
626 } 614 }
627 615
628 -static void omap_dma_disable_channel(struct omap_dma_s *s, int channel) 616 +static void omap_dma_disable_channel(struct omap_dma_s *s,
  617 + struct omap_dma_channel_s *ch)
629 { 618 {
630 - if (s->ch[channel].enable) {  
631 - s->ch[channel].enable = 0; 619 + if (ch->enable) {
  620 + ch->enable = 0;
632 /* Discard any pending request */ 621 /* Discard any pending request */
633 - s->ch[channel].pending_request = 0;  
634 - omap_dma_deactivate_channel(s, channel); 622 + ch->pending_request = 0;
  623 + omap_dma_deactivate_channel(s, ch);
635 } 624 }
636 } 625 }
637 626
638 -static void omap_dma_channel_end_prog(struct omap_dma_s *s, int channel) 627 +static void omap_dma_channel_end_prog(struct omap_dma_s *s,
  628 + struct omap_dma_channel_s *ch)
639 { 629 {
640 - if (s->ch[channel].waiting_end_prog) {  
641 - s->ch[channel].waiting_end_prog = 0;  
642 - if (!s->ch[channel].sync || s->ch[channel].pending_request) {  
643 - s->ch[channel].pending_request = 0;  
644 - omap_dma_activate_channel(s, channel); 630 + if (ch->waiting_end_prog) {
  631 + ch->waiting_end_prog = 0;
  632 + if (!ch->sync || ch->pending_request) {
  633 + ch->pending_request = 0;
  634 + omap_dma_activate_channel(s, ch);
645 } 635 }
646 } 636 }
647 } 637 }
@@ -662,17 +652,18 @@ static void omap_dma_process_request(struct omap_dma_s *s, int request) @@ -662,17 +652,18 @@ static void omap_dma_process_request(struct omap_dma_s *s, int request)
662 { 652 {
663 int channel; 653 int channel;
664 int drop_event = 0; 654 int drop_event = 0;
665 -  
666 - for (channel = 0; channel < s->chans; channel ++) {  
667 - if (s->ch[channel].enable && s->ch[channel].sync == request) {  
668 - if (!s->ch[channel].active)  
669 - omap_dma_activate_channel(s, channel);  
670 - else if (!s->ch[channel].pending_request)  
671 - s->ch[channel].pending_request = 1; 655 + struct omap_dma_channel_s *ch = s->ch;
  656 +
  657 + for (channel = 0; channel < s->chans; channel ++, ch ++) {
  658 + if (ch->enable && ch->sync == request) {
  659 + if (!ch->active)
  660 + omap_dma_activate_channel(s, ch);
  661 + else if (!ch->pending_request)
  662 + ch->pending_request = 1;
672 else { 663 else {
673 /* Request collision */ 664 /* Request collision */
674 /* Second request received while processing other request */ 665 /* Second request received while processing other request */
675 - s->ch[channel].status |= EVENT_DROP_INTR; 666 + ch->status |= EVENT_DROP_INTR;
676 drop_event = 1; 667 drop_event = 1;
677 } 668 }
678 } 669 }
@@ -684,63 +675,65 @@ static void omap_dma_process_request(struct omap_dma_s *s, int request) @@ -684,63 +675,65 @@ static void omap_dma_process_request(struct omap_dma_s *s, int request)
684 675
685 static void omap_dma_channel_run(struct omap_dma_s *s) 676 static void omap_dma_channel_run(struct omap_dma_s *s)
686 { 677 {
687 - int ch; 678 + int n = s->chans;
688 uint16_t status; 679 uint16_t status;
689 uint8_t value[4]; 680 uint8_t value[4];
690 struct omap_dma_port_if_s *src_p, *dest_p; 681 struct omap_dma_port_if_s *src_p, *dest_p;
691 struct omap_dma_reg_set_s *a; 682 struct omap_dma_reg_set_s *a;
  683 + struct omap_dma_channel_s *ch;
692 684
693 - for (ch = 0; ch < s->chans; ch ++) {  
694 - if (!s->ch[ch].active) 685 + for (ch = s->ch; n; n --, ch ++) {
  686 + if (!ch->active)
695 continue; 687 continue;
696 688
697 - a = &s->ch[ch].active_set; 689 + a = &ch->active_set;
698 690
699 - src_p = &s->mpu->port[s->ch[ch].port[0]];  
700 - dest_p = &s->mpu->port[s->ch[ch].port[1]];  
701 - if ((!s->ch[ch].constant_fill && !src_p->addr_valid(s->mpu, a->src)) || 691 + src_p = &s->mpu->port[ch->port[0]];
  692 + dest_p = &s->mpu->port[ch->port[1]];
  693 + if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
702 (!dest_p->addr_valid(s->mpu, a->dest))) { 694 (!dest_p->addr_valid(s->mpu, a->dest))) {
703 #if 0 695 #if 0
704 /* Bus time-out */ 696 /* Bus time-out */
705 - if (s->ch[ch].interrupts & TIMEOUT_INTR)  
706 - s->ch[ch].status |= TIMEOUT_INTR; 697 + if (ch->interrupts & TIMEOUT_INTR)
  698 + ch->status |= TIMEOUT_INTR;
707 omap_dma_deactivate_channel(s, ch); 699 omap_dma_deactivate_channel(s, ch);
708 continue; 700 continue;
709 #endif 701 #endif
710 - printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch); 702 + printf("%s: Bus time-out in DMA%i operation\n",
  703 + __FUNCTION__, s->chans - n);
711 } 704 }
712 705
713 - status = s->ch[ch].status;  
714 - while (status == s->ch[ch].status && s->ch[ch].active) { 706 + status = ch->status;
  707 + while (status == ch->status && ch->active) {
715 /* Transfer a single element */ 708 /* Transfer a single element */
716 /* FIXME: check the endianness */ 709 /* FIXME: check the endianness */
717 - if (!s->ch[ch].constant_fill)  
718 - cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); 710 + if (!ch->constant_fill)
  711 + cpu_physical_memory_read(a->src, value, ch->data_type);
719 else 712 else
720 - *(uint32_t *) value = s->ch[ch].color; 713 + *(uint32_t *) value = ch->color;
721 714
722 - if (!s->ch[ch].transparent_copy ||  
723 - *(uint32_t *) value != s->ch[ch].color)  
724 - cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); 715 + if (!ch->transparent_copy ||
  716 + *(uint32_t *) value != ch->color)
  717 + cpu_physical_memory_write(a->dest, value, ch->data_type);
725 718
726 a->src += a->elem_delta[0]; 719 a->src += a->elem_delta[0];
727 a->dest += a->elem_delta[1]; 720 a->dest += a->elem_delta[1];
728 a->element ++; 721 a->element ++;
729 722
730 /* If the channel is element synchronized, deactivate it */ 723 /* If the channel is element synchronized, deactivate it */
731 - if (s->ch[ch].sync && !s->ch[ch].fs && !s->ch[ch].bs) 724 + if (ch->sync && !ch->fs && !ch->bs)
732 omap_dma_deactivate_channel(s, ch); 725 omap_dma_deactivate_channel(s, ch);
733 726
734 /* If it is the last frame, set the LAST_FRAME interrupt */ 727 /* If it is the last frame, set the LAST_FRAME interrupt */
735 if (a->element == 1 && a->frame == a->frames - 1) 728 if (a->element == 1 && a->frame == a->frames - 1)
736 - if (s->ch[ch].interrupts & LAST_FRAME_INTR)  
737 - s->ch[ch].status |= LAST_FRAME_INTR; 729 + if (ch->interrupts & LAST_FRAME_INTR)
  730 + ch->status |= LAST_FRAME_INTR;
738 731
739 /* If the half of the frame was reached, set the HALF_FRAME 732 /* If the half of the frame was reached, set the HALF_FRAME
740 interrupt */ 733 interrupt */
741 if (a->element == (a->elements >> 1)) 734 if (a->element == (a->elements >> 1))
742 - if (s->ch[ch].interrupts & HALF_FRAME_INTR)  
743 - s->ch[ch].status |= HALF_FRAME_INTR; 735 + if (ch->interrupts & HALF_FRAME_INTR)
  736 + ch->status |= HALF_FRAME_INTR;
744 737
745 if (a->element == a->elements) { 738 if (a->element == a->elements) {
746 /* End of Frame */ 739 /* End of Frame */
@@ -750,38 +743,39 @@ static void omap_dma_channel_run(struct omap_dma_s *s) @@ -750,38 +743,39 @@ static void omap_dma_channel_run(struct omap_dma_s *s)
750 a->frame ++; 743 a->frame ++;
751 744
752 /* If the channel is frame synchronized, deactivate it */ 745 /* If the channel is frame synchronized, deactivate it */
753 - if (s->ch[ch].sync && s->ch[ch].fs) 746 + if (ch->sync && ch->fs)
754 omap_dma_deactivate_channel(s, ch); 747 omap_dma_deactivate_channel(s, ch);
755 748
756 /* If the channel is async, update cpc */ 749 /* If the channel is async, update cpc */
757 - if (!s->ch[ch].sync)  
758 - s->ch[ch].cpc = a->dest & 0xffff; 750 + if (!ch->sync)
  751 + ch->cpc = a->dest & 0xffff;
759 752
760 /* Set the END_FRAME interrupt */ 753 /* Set the END_FRAME interrupt */
761 - if (s->ch[ch].interrupts & END_FRAME_INTR)  
762 - s->ch[ch].status |= END_FRAME_INTR; 754 + if (ch->interrupts & END_FRAME_INTR)
  755 + ch->status |= END_FRAME_INTR;
763 756
764 if (a->frame == a->frames) { 757 if (a->frame == a->frames) {
765 /* End of Block */ 758 /* End of Block */
766 /* Disable the channel */ 759 /* Disable the channel */
767 760
768 - if (s->ch[ch].omap_3_1_compatible_disable) { 761 + if (ch->omap_3_1_compatible_disable) {
769 omap_dma_disable_channel(s, ch); 762 omap_dma_disable_channel(s, ch);
770 - if (s->ch[ch].link_enabled)  
771 - omap_dma_enable_channel(s, s->ch[ch].link_next_ch); 763 + if (ch->link_enabled)
  764 + omap_dma_enable_channel(s,
  765 + &s->ch[ch->link_next_ch]);
772 } else { 766 } else {
773 - if (!s->ch[ch].auto_init) 767 + if (!ch->auto_init)
774 omap_dma_disable_channel(s, ch); 768 omap_dma_disable_channel(s, ch);
775 - else if (s->ch[ch].repeat || s->ch[ch].end_prog) 769 + else if (ch->repeat || ch->end_prog)
776 omap_dma_channel_load(s, ch); 770 omap_dma_channel_load(s, ch);
777 else { 771 else {
778 - s->ch[ch].waiting_end_prog = 1; 772 + ch->waiting_end_prog = 1;
779 omap_dma_deactivate_channel(s, ch); 773 omap_dma_deactivate_channel(s, ch);
780 } 774 }
781 } 775 }
782 776
783 - if (s->ch[ch].interrupts & END_BLOCK_INTR)  
784 - s->ch[ch].status |= END_BLOCK_INTR; 777 + if (ch->interrupts & END_BLOCK_INTR)
  778 + ch->status |= END_BLOCK_INTR;
785 } 779 }
786 } 780 }
787 } 781 }
@@ -805,134 +799,161 @@ static void omap_dma_reset(struct omap_dma_s *s) @@ -805,134 +799,161 @@ static void omap_dma_reset(struct omap_dma_s *s)
805 s->lcd_ch.interrupts = 0; 799 s->lcd_ch.interrupts = 0;
806 s->lcd_ch.dual = 0; 800 s->lcd_ch.dual = 0;
807 omap_dma_enable_3_1_mapping(s); 801 omap_dma_enable_3_1_mapping(s);
808 - memset(s->ch, 0, sizeof(s->ch));  
809 - for (i = 0; i < s->chans; i ++) 802 + for (i = 0; i < s->chans; i ++) {
  803 + memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
  804 + memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
  805 + memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
  806 + memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements));
  807 + memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames));
  808 + memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
  809 + memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
  810 + memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type));
  811 + memset(&s->ch[i].transparent_copy, 0,
  812 + sizeof(s->ch[i].transparent_copy));
  813 + memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill));
  814 + memset(&s->ch[i].color, 0, sizeof(s->ch[i].color));
  815 + memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog));
  816 + memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat));
  817 + memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init));
  818 + memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled));
  819 + memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch));
810 s->ch[i].interrupts = 0x0003; 820 s->ch[i].interrupts = 0x0003;
  821 + memset(&s->ch[i].status, 0, sizeof(s->ch[i].status));
  822 + memset(&s->ch[i].active, 0, sizeof(s->ch[i].active));
  823 + memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable));
  824 + memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync));
  825 + memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request));
  826 + memset(&s->ch[i].waiting_end_prog, 0,
  827 + sizeof(s->ch[i].waiting_end_prog));
  828 + memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc));
  829 + memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs));
  830 + memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs));
  831 + memset(&s->ch[i].omap_3_1_compatible_disable, 0,
  832 + sizeof(s->ch[i].omap_3_1_compatible_disable));
  833 + memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
  834 + memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority));
  835 + memset(&s->ch[i].interleave_disabled, 0,
  836 + sizeof(s->ch[i].interleave_disabled));
  837 + memset(&s->ch[i].type, 0, sizeof(s->ch[i].type));
  838 + }
811 } 839 }
812 840
813 -static int omap_dma_ch_reg_read(struct omap_dma_s *s, int ch, int reg,  
814 - uint16_t *value) 841 +static int omap_dma_ch_reg_read(struct omap_dma_s *s,
  842 + struct omap_dma_channel_s *ch, int reg, uint16_t *value)
815 { 843 {
816 - int sibling;  
817 -  
818 switch (reg) { 844 switch (reg) {
819 case 0x00: /* SYS_DMA_CSDP_CH0 */ 845 case 0x00: /* SYS_DMA_CSDP_CH0 */
820 - *value = (s->ch[ch].burst[1] << 14) |  
821 - (s->ch[ch].pack[1] << 13) |  
822 - (s->ch[ch].port[1] << 9) |  
823 - (s->ch[ch].burst[0] << 7) |  
824 - (s->ch[ch].pack[0] << 6) |  
825 - (s->ch[ch].port[0] << 2) |  
826 - (s->ch[ch].data_type >> 1); 846 + *value = (ch->burst[1] << 14) |
  847 + (ch->pack[1] << 13) |
  848 + (ch->port[1] << 9) |
  849 + (ch->burst[0] << 7) |
  850 + (ch->pack[0] << 6) |
  851 + (ch->port[0] << 2) |
  852 + (ch->data_type >> 1);
827 break; 853 break;
828 854
829 case 0x02: /* SYS_DMA_CCR_CH0 */ 855 case 0x02: /* SYS_DMA_CCR_CH0 */
830 if (s->model == omap_dma_3_1) 856 if (s->model == omap_dma_3_1)
831 - *value = 0 << 10; /* FIFO_FLUSH bit */ 857 + *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
832 else 858 else
833 - *value = s->ch[ch].omap_3_1_compatible_disable << 10;  
834 - *value |= (s->ch[ch].mode[1] << 14) |  
835 - (s->ch[ch].mode[0] << 12) |  
836 - (s->ch[ch].end_prog << 11) |  
837 - (s->ch[ch].repeat << 9) |  
838 - (s->ch[ch].auto_init << 8) |  
839 - (s->ch[ch].enable << 7) |  
840 - (s->ch[ch].priority << 6) |  
841 - (s->ch[ch].fs << 5) | s->ch[ch].sync; 859 + *value = ch->omap_3_1_compatible_disable << 10;
  860 + *value |= (ch->mode[1] << 14) |
  861 + (ch->mode[0] << 12) |
  862 + (ch->end_prog << 11) |
  863 + (ch->repeat << 9) |
  864 + (ch->auto_init << 8) |
  865 + (ch->enable << 7) |
  866 + (ch->priority << 6) |
  867 + (ch->fs << 5) | ch->sync;
842 break; 868 break;
843 869
844 case 0x04: /* SYS_DMA_CICR_CH0 */ 870 case 0x04: /* SYS_DMA_CICR_CH0 */
845 - *value = s->ch[ch].interrupts; 871 + *value = ch->interrupts;
846 break; 872 break;
847 873
848 case 0x06: /* SYS_DMA_CSR_CH0 */ 874 case 0x06: /* SYS_DMA_CSR_CH0 */
849 - sibling = omap_dma_get_sibling_channel(s, ch);  
850 - *value = s->ch[ch].status;  
851 - s->ch[ch].status &= SYNC;  
852 - if (sibling != -1) {  
853 - *value |= (s->ch[sibling].status & 0x3f) << 6;  
854 - s->ch[sibling].status &= SYNC;  
855 - if (sibling < ch) {  
856 - qemu_irq_lower(s->irqs[sibling]);  
857 - break;  
858 - } 875 + *value = ch->status;
  876 + ch->status &= SYNC;
  877 + if (!ch->omap_3_1_compatible_disable && ch->sibling) {
  878 + *value |= (ch->sibling->status & 0x3f) << 6;
  879 + ch->sibling->status &= SYNC;
859 } 880 }
860 - qemu_irq_lower(s->irqs[ch]); 881 + qemu_irq_lower(ch->irq);
861 break; 882 break;
862 883
863 case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 884 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
864 - *value = s->ch[ch].addr[0] & 0x0000ffff; 885 + *value = ch->addr[0] & 0x0000ffff;
865 break; 886 break;
866 887
867 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 888 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
868 - *value = s->ch[ch].addr[0] >> 16; 889 + *value = ch->addr[0] >> 16;
869 break; 890 break;
870 891
871 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 892 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
872 - *value = s->ch[ch].addr[1] & 0x0000ffff; 893 + *value = ch->addr[1] & 0x0000ffff;
873 break; 894 break;
874 895
875 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 896 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
876 - *value = s->ch[ch].addr[1] >> 16; 897 + *value = ch->addr[1] >> 16;
877 break; 898 break;
878 899
879 case 0x10: /* SYS_DMA_CEN_CH0 */ 900 case 0x10: /* SYS_DMA_CEN_CH0 */
880 - *value = s->ch[ch].elements; 901 + *value = ch->elements;
881 break; 902 break;
882 903
883 case 0x12: /* SYS_DMA_CFN_CH0 */ 904 case 0x12: /* SYS_DMA_CFN_CH0 */
884 - *value = s->ch[ch].frames; 905 + *value = ch->frames;
885 break; 906 break;
886 907
887 case 0x14: /* SYS_DMA_CFI_CH0 */ 908 case 0x14: /* SYS_DMA_CFI_CH0 */
888 - *value = s->ch[ch].frame_index[0]; 909 + *value = ch->frame_index[0];
889 break; 910 break;
890 911
891 case 0x16: /* SYS_DMA_CEI_CH0 */ 912 case 0x16: /* SYS_DMA_CEI_CH0 */
892 - *value = s->ch[ch].element_index[0]; 913 + *value = ch->element_index[0];
893 break; 914 break;
894 915
895 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 916 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
896 - if (s->ch[ch].omap_3_1_compatible_disable)  
897 - *value = s->ch[ch].active_set.src & 0xffff; /* CSAC */ 917 + if (ch->omap_3_1_compatible_disable)
  918 + *value = ch->active_set.src & 0xffff; /* CSAC */
898 else 919 else
899 - *value = s->ch[ch].cpc; 920 + *value = ch->cpc;
900 break; 921 break;
901 922
902 case 0x1a: /* DMA_CDAC */ 923 case 0x1a: /* DMA_CDAC */
903 - *value = s->ch[ch].active_set.dest & 0xffff; /* CDAC */ 924 + *value = ch->active_set.dest & 0xffff; /* CDAC */
904 break; 925 break;
905 926
906 case 0x1c: /* DMA_CDEI */ 927 case 0x1c: /* DMA_CDEI */
907 - *value = s->ch[ch].element_index[1]; 928 + *value = ch->element_index[1];
908 break; 929 break;
909 930
910 case 0x1e: /* DMA_CDFI */ 931 case 0x1e: /* DMA_CDFI */
911 - *value = s->ch[ch].frame_index[1]; 932 + *value = ch->frame_index[1];
912 break; 933 break;
913 934
914 case 0x20: /* DMA_COLOR_L */ 935 case 0x20: /* DMA_COLOR_L */
915 - *value = s->ch[ch].color & 0xffff; 936 + *value = ch->color & 0xffff;
916 break; 937 break;
917 938
918 case 0x22: /* DMA_COLOR_U */ 939 case 0x22: /* DMA_COLOR_U */
919 - *value = s->ch[ch].color >> 16; 940 + *value = ch->color >> 16;
920 break; 941 break;
921 942
922 case 0x24: /* DMA_CCR2 */ 943 case 0x24: /* DMA_CCR2 */
923 - *value = (s->ch[ch].bs << 2) |  
924 - (s->ch[ch].transparent_copy << 1) |  
925 - s->ch[ch].constant_fill; 944 + *value = (ch->bs << 2) |
  945 + (ch->transparent_copy << 1) |
  946 + ch->constant_fill;
926 break; 947 break;
927 948
928 case 0x28: /* DMA_CLNK_CTRL */ 949 case 0x28: /* DMA_CLNK_CTRL */
929 - *value = (s->ch[ch].link_enabled << 15) |  
930 - (s->ch[ch].link_next_ch & 0xf); 950 + *value = (ch->link_enabled << 15) |
  951 + (ch->link_next_ch & 0xf);
931 break; 952 break;
932 953
933 case 0x2a: /* DMA_LCH_CTRL */ 954 case 0x2a: /* DMA_LCH_CTRL */
934 - *value = (s->ch[ch].interleave_disabled << 15) |  
935 - s->ch[ch].type; 955 + *value = (ch->interleave_disabled << 15) |
  956 + ch->type;
936 break; 957 break;
937 958
938 default: 959 default:
@@ -942,90 +963,91 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, int ch, int reg, @@ -942,90 +963,91 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, int ch, int reg,
942 } 963 }
943 964
944 static int omap_dma_ch_reg_write(struct omap_dma_s *s, 965 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
945 - int ch, int reg, uint16_t value) 966 + struct omap_dma_channel_s *ch, int reg, uint16_t value)
946 { 967 {
947 switch (reg) { 968 switch (reg) {
948 case 0x00: /* SYS_DMA_CSDP_CH0 */ 969 case 0x00: /* SYS_DMA_CSDP_CH0 */
949 - s->ch[ch].burst[1] = (value & 0xc000) >> 14;  
950 - s->ch[ch].pack[1] = (value & 0x2000) >> 13;  
951 - s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);  
952 - s->ch[ch].burst[0] = (value & 0x0180) >> 7;  
953 - s->ch[ch].pack[0] = (value & 0x0040) >> 6;  
954 - s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);  
955 - s->ch[ch].data_type = (1 << (value & 3));  
956 - if (s->ch[ch].port[0] >= omap_dma_port_last) 970 + ch->burst[1] = (value & 0xc000) >> 14;
  971 + ch->pack[1] = (value & 0x2000) >> 13;
  972 + ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
  973 + ch->burst[0] = (value & 0x0180) >> 7;
  974 + ch->pack[0] = (value & 0x0040) >> 6;
  975 + ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
  976 + ch->data_type = (1 << (value & 3));
  977 + if (ch->port[0] >= omap_dma_port_last)
957 printf("%s: invalid DMA port %i\n", __FUNCTION__, 978 printf("%s: invalid DMA port %i\n", __FUNCTION__,
958 - s->ch[ch].port[0]);  
959 - if (s->ch[ch].port[1] >= omap_dma_port_last) 979 + ch->port[0]);
  980 + if (ch->port[1] >= omap_dma_port_last)
960 printf("%s: invalid DMA port %i\n", __FUNCTION__, 981 printf("%s: invalid DMA port %i\n", __FUNCTION__,
961 - s->ch[ch].port[1]); 982 + ch->port[1]);
962 if ((value & 3) == 3) 983 if ((value & 3) == 3)
963 - printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch); 984 + printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
964 break; 985 break;
965 986
966 case 0x02: /* SYS_DMA_CCR_CH0 */ 987 case 0x02: /* SYS_DMA_CCR_CH0 */
967 - s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);  
968 - s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);  
969 - s->ch[ch].end_prog = (value & 0x0800) >> 11; 988 + ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
  989 + ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
  990 + ch->end_prog = (value & 0x0800) >> 11;
970 if (s->model > omap_dma_3_1) 991 if (s->model > omap_dma_3_1)
971 - s->ch[ch].omap_3_1_compatible_disable = (value >> 10) & 0x1;  
972 - s->ch[ch].repeat = (value & 0x0200) >> 9;  
973 - s->ch[ch].auto_init = (value & 0x0100) >> 8;  
974 - s->ch[ch].priority = (value & 0x0040) >> 6;  
975 - s->ch[ch].fs = (value & 0x0020) >> 5;  
976 - s->ch[ch].sync = value & 0x001f; 992 + ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
  993 + ch->repeat = (value & 0x0200) >> 9;
  994 + ch->auto_init = (value & 0x0100) >> 8;
  995 + ch->priority = (value & 0x0040) >> 6;
  996 + ch->fs = (value & 0x0020) >> 5;
  997 + ch->sync = value & 0x001f;
977 998
978 if (value & 0x0080) 999 if (value & 0x0080)
979 omap_dma_enable_channel(s, ch); 1000 omap_dma_enable_channel(s, ch);
980 else 1001 else
981 omap_dma_disable_channel(s, ch); 1002 omap_dma_disable_channel(s, ch);
982 1003
983 - if (s->ch[ch].end_prog) 1004 + if (ch->end_prog)
984 omap_dma_channel_end_prog(s, ch); 1005 omap_dma_channel_end_prog(s, ch);
985 1006
986 break; 1007 break;
987 1008
988 case 0x04: /* SYS_DMA_CICR_CH0 */ 1009 case 0x04: /* SYS_DMA_CICR_CH0 */
989 - s->ch[ch].interrupts = value; 1010 + ch->interrupts = value;
990 break; 1011 break;
991 1012
992 case 0x06: /* SYS_DMA_CSR_CH0 */ 1013 case 0x06: /* SYS_DMA_CSR_CH0 */
993 - return 1; 1014 + OMAP_RO_REG((target_phys_addr_t) reg);
  1015 + break;
994 1016
995 case 0x08: /* SYS_DMA_CSSA_L_CH0 */ 1017 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
996 - s->ch[ch].addr[0] &= 0xffff0000;  
997 - s->ch[ch].addr[0] |= value; 1018 + ch->addr[0] &= 0xffff0000;
  1019 + ch->addr[0] |= value;
998 break; 1020 break;
999 1021
1000 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ 1022 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
1001 - s->ch[ch].addr[0] &= 0x0000ffff;  
1002 - s->ch[ch].addr[0] |= (uint32_t) value << 16; 1023 + ch->addr[0] &= 0x0000ffff;
  1024 + ch->addr[0] |= (uint32_t) value << 16;
1003 break; 1025 break;
1004 1026
1005 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ 1027 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
1006 - s->ch[ch].addr[1] &= 0xffff0000;  
1007 - s->ch[ch].addr[1] |= value; 1028 + ch->addr[1] &= 0xffff0000;
  1029 + ch->addr[1] |= value;
1008 break; 1030 break;
1009 1031
1010 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ 1032 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
1011 - s->ch[ch].addr[1] &= 0x0000ffff;  
1012 - s->ch[ch].addr[1] |= (uint32_t) value << 16; 1033 + ch->addr[1] &= 0x0000ffff;
  1034 + ch->addr[1] |= (uint32_t) value << 16;
1013 break; 1035 break;
1014 1036
1015 case 0x10: /* SYS_DMA_CEN_CH0 */ 1037 case 0x10: /* SYS_DMA_CEN_CH0 */
1016 - s->ch[ch].elements = value; 1038 + ch->elements = value;
1017 break; 1039 break;
1018 1040
1019 case 0x12: /* SYS_DMA_CFN_CH0 */ 1041 case 0x12: /* SYS_DMA_CFN_CH0 */
1020 - s->ch[ch].frames = value; 1042 + ch->frames = value;
1021 break; 1043 break;
1022 1044
1023 case 0x14: /* SYS_DMA_CFI_CH0 */ 1045 case 0x14: /* SYS_DMA_CFI_CH0 */
1024 - s->ch[ch].frame_index[0] = (int16_t) value; 1046 + ch->frame_index[0] = (int16_t) value;
1025 break; 1047 break;
1026 1048
1027 case 0x16: /* SYS_DMA_CEI_CH0 */ 1049 case 0x16: /* SYS_DMA_CEI_CH0 */
1028 - s->ch[ch].element_index[0] = (int16_t) value; 1050 + ch->element_index[0] = (int16_t) value;
1029 break; 1051 break;
1030 1052
1031 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ 1053 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
@@ -1033,41 +1055,41 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, @@ -1033,41 +1055,41 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
1033 break; 1055 break;
1034 1056
1035 case 0x1c: /* DMA_CDEI */ 1057 case 0x1c: /* DMA_CDEI */
1036 - s->ch[ch].element_index[1] = (int16_t) value; 1058 + ch->element_index[1] = (int16_t) value;
1037 break; 1059 break;
1038 1060
1039 case 0x1e: /* DMA_CDFI */ 1061 case 0x1e: /* DMA_CDFI */
1040 - s->ch[ch].frame_index[1] = (int16_t) value; 1062 + ch->frame_index[1] = (int16_t) value;
1041 break; 1063 break;
1042 1064
1043 case 0x20: /* DMA_COLOR_L */ 1065 case 0x20: /* DMA_COLOR_L */
1044 - s->ch[ch].color &= 0xffff0000;  
1045 - s->ch[ch].color |= value; 1066 + ch->color &= 0xffff0000;
  1067 + ch->color |= value;
1046 break; 1068 break;
1047 1069
1048 case 0x22: /* DMA_COLOR_U */ 1070 case 0x22: /* DMA_COLOR_U */
1049 - s->ch[ch].color &= 0xffff;  
1050 - s->ch[ch].color |= value << 16; 1071 + ch->color &= 0xffff;
  1072 + ch->color |= value << 16;
1051 break; 1073 break;
1052 1074
1053 case 0x24: /* DMA_CCR2 */ 1075 case 0x24: /* DMA_CCR2 */
1054 - s->ch[ch].bs = (value >> 2) & 0x1;  
1055 - s->ch[ch].transparent_copy = (value >> 1) & 0x1;  
1056 - s->ch[ch].constant_fill = value & 0x1; 1076 + ch->bs = (value >> 2) & 0x1;
  1077 + ch->transparent_copy = (value >> 1) & 0x1;
  1078 + ch->constant_fill = value & 0x1;
1057 break; 1079 break;
1058 1080
1059 case 0x28: /* DMA_CLNK_CTRL */ 1081 case 0x28: /* DMA_CLNK_CTRL */
1060 - s->ch[ch].link_enabled = (value >> 15) & 0x1; 1082 + ch->link_enabled = (value >> 15) & 0x1;
1061 if (value & (1 << 14)) { /* Stop_Lnk */ 1083 if (value & (1 << 14)) { /* Stop_Lnk */
1062 - s->ch[ch].link_enabled = 0; 1084 + ch->link_enabled = 0;
1063 omap_dma_disable_channel(s, ch); 1085 omap_dma_disable_channel(s, ch);
1064 } 1086 }
1065 - s->ch[ch].link_next_ch = value & 0x1f; 1087 + ch->link_next_ch = value & 0x1f;
1066 break; 1088 break;
1067 1089
1068 case 0x2a: /* DMA_LCH_CTRL */ 1090 case 0x2a: /* DMA_LCH_CTRL */
1069 - s->ch[ch].interleave_disabled = (value >> 15) & 0x1;  
1070 - s->ch[ch].type = value & 0xf; 1091 + ch->interleave_disabled = (value >> 15) & 0x1;
  1092 + ch->type = value & 0xf;
1071 break; 1093 break;
1072 1094
1073 default: 1095 default:
@@ -1076,126 +1098,126 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, @@ -1076,126 +1098,126 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
1076 return 0; 1098 return 0;
1077 } 1099 }
1078 1100
1079 -static int omap_dma_3_2_lcd_write(struct omap_dma_s *s, int offset, 1101 +static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1080 uint16_t value) 1102 uint16_t value)
1081 { 1103 {
1082 switch (offset) { 1104 switch (offset) {
1083 case 0xbc0: /* DMA_LCD_CSDP */ 1105 case 0xbc0: /* DMA_LCD_CSDP */
1084 - s->lcd_ch.brust_f2 = (value >> 14) & 0x3;  
1085 - s->lcd_ch.pack_f2 = (value >> 13) & 0x1;  
1086 - s->lcd_ch.data_type_f2 = (1 << ((value >> 11) & 0x3));  
1087 - s->lcd_ch.brust_f1 = (value >> 7) & 0x3;  
1088 - s->lcd_ch.pack_f1 = (value >> 6) & 0x1;  
1089 - s->lcd_ch.data_type_f1 = (1 << ((value >> 0) & 0x3)); 1106 + s->brust_f2 = (value >> 14) & 0x3;
  1107 + s->pack_f2 = (value >> 13) & 0x1;
  1108 + s->data_type_f2 = (1 << ((value >> 11) & 0x3));
  1109 + s->brust_f1 = (value >> 7) & 0x3;
  1110 + s->pack_f1 = (value >> 6) & 0x1;
  1111 + s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1090 break; 1112 break;
1091 1113
1092 case 0xbc2: /* DMA_LCD_CCR */ 1114 case 0xbc2: /* DMA_LCD_CCR */
1093 - s->lcd_ch.mode_f2 = (value >> 14) & 0x3;  
1094 - s->lcd_ch.mode_f1 = (value >> 12) & 0x3;  
1095 - s->lcd_ch.end_prog = (value >> 11) & 0x1;  
1096 - s->lcd_ch.omap_3_1_compatible_disable = (value >> 10) & 0x1;  
1097 - s->lcd_ch.repeat = (value >> 9) & 0x1;  
1098 - s->lcd_ch.auto_init = (value >> 8) & 0x1;  
1099 - s->lcd_ch.running = (value >> 7) & 0x1;  
1100 - s->lcd_ch.priority = (value >> 6) & 0x1;  
1101 - s->lcd_ch.bs = (value >> 4) & 0x1; 1115 + s->mode_f2 = (value >> 14) & 0x3;
  1116 + s->mode_f1 = (value >> 12) & 0x3;
  1117 + s->end_prog = (value >> 11) & 0x1;
  1118 + s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
  1119 + s->repeat = (value >> 9) & 0x1;
  1120 + s->auto_init = (value >> 8) & 0x1;
  1121 + s->running = (value >> 7) & 0x1;
  1122 + s->priority = (value >> 6) & 0x1;
  1123 + s->bs = (value >> 4) & 0x1;
1102 break; 1124 break;
1103 1125
1104 case 0xbc4: /* DMA_LCD_CTRL */ 1126 case 0xbc4: /* DMA_LCD_CTRL */
1105 - s->lcd_ch.dst = (value >> 8) & 0x1;  
1106 - s->lcd_ch.src = ((value >> 6) & 0x3) << 1;  
1107 - s->lcd_ch.condition = 0; 1127 + s->dst = (value >> 8) & 0x1;
  1128 + s->src = ((value >> 6) & 0x3) << 1;
  1129 + s->condition = 0;
1108 /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1130 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1109 - s->lcd_ch.interrupts = (value >> 1) & 1;  
1110 - s->lcd_ch.dual = value & 1; 1131 + s->interrupts = (value >> 1) & 1;
  1132 + s->dual = value & 1;
1111 break; 1133 break;
1112 1134
1113 case 0xbc8: /* TOP_B1_L */ 1135 case 0xbc8: /* TOP_B1_L */
1114 - s->lcd_ch.src_f1_top &= 0xffff0000;  
1115 - s->lcd_ch.src_f1_top |= 0x0000ffff & value; 1136 + s->src_f1_top &= 0xffff0000;
  1137 + s->src_f1_top |= 0x0000ffff & value;
1116 break; 1138 break;
1117 1139
1118 case 0xbca: /* TOP_B1_U */ 1140 case 0xbca: /* TOP_B1_U */
1119 - s->lcd_ch.src_f1_top &= 0x0000ffff;  
1120 - s->lcd_ch.src_f1_top |= value << 16; 1141 + s->src_f1_top &= 0x0000ffff;
  1142 + s->src_f1_top |= value << 16;
1121 break; 1143 break;
1122 1144
1123 case 0xbcc: /* BOT_B1_L */ 1145 case 0xbcc: /* BOT_B1_L */
1124 - s->lcd_ch.src_f1_bottom &= 0xffff0000;  
1125 - s->lcd_ch.src_f1_bottom |= 0x0000ffff & value; 1146 + s->src_f1_bottom &= 0xffff0000;
  1147 + s->src_f1_bottom |= 0x0000ffff & value;
1126 break; 1148 break;
1127 1149
1128 case 0xbce: /* BOT_B1_U */ 1150 case 0xbce: /* BOT_B1_U */
1129 - s->lcd_ch.src_f1_bottom &= 0x0000ffff;  
1130 - s->lcd_ch.src_f1_bottom |= (uint32_t) value << 16; 1151 + s->src_f1_bottom &= 0x0000ffff;
  1152 + s->src_f1_bottom |= (uint32_t) value << 16;
1131 break; 1153 break;
1132 1154
1133 case 0xbd0: /* TOP_B2_L */ 1155 case 0xbd0: /* TOP_B2_L */
1134 - s->lcd_ch.src_f2_top &= 0xffff0000;  
1135 - s->lcd_ch.src_f2_top |= 0x0000ffff & value; 1156 + s->src_f2_top &= 0xffff0000;
  1157 + s->src_f2_top |= 0x0000ffff & value;
1136 break; 1158 break;
1137 1159
1138 case 0xbd2: /* TOP_B2_U */ 1160 case 0xbd2: /* TOP_B2_U */
1139 - s->lcd_ch.src_f2_top &= 0x0000ffff;  
1140 - s->lcd_ch.src_f2_top |= (uint32_t) value << 16; 1161 + s->src_f2_top &= 0x0000ffff;
  1162 + s->src_f2_top |= (uint32_t) value << 16;
1141 break; 1163 break;
1142 1164
1143 case 0xbd4: /* BOT_B2_L */ 1165 case 0xbd4: /* BOT_B2_L */
1144 - s->lcd_ch.src_f2_bottom &= 0xffff0000;  
1145 - s->lcd_ch.src_f2_bottom |= 0x0000ffff & value; 1166 + s->src_f2_bottom &= 0xffff0000;
  1167 + s->src_f2_bottom |= 0x0000ffff & value;
1146 break; 1168 break;
1147 1169
1148 case 0xbd6: /* BOT_B2_U */ 1170 case 0xbd6: /* BOT_B2_U */
1149 - s->lcd_ch.src_f2_bottom &= 0x0000ffff;  
1150 - s->lcd_ch.src_f2_bottom |= (uint32_t) value << 16; 1171 + s->src_f2_bottom &= 0x0000ffff;
  1172 + s->src_f2_bottom |= (uint32_t) value << 16;
1151 break; 1173 break;
1152 1174
1153 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1175 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1154 - s->lcd_ch.element_index_f1 = value; 1176 + s->element_index_f1 = value;
1155 break; 1177 break;
1156 1178
1157 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1179 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1158 - s->lcd_ch.frame_index_f1 &= 0xffff0000;  
1159 - s->lcd_ch.frame_index_f1 |= 0x0000ffff & value; 1180 + s->frame_index_f1 &= 0xffff0000;
  1181 + s->frame_index_f1 |= 0x0000ffff & value;
1160 break; 1182 break;
1161 1183
1162 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1184 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1163 - s->lcd_ch.frame_index_f1 &= 0x0000ffff;  
1164 - s->lcd_ch.frame_index_f1 |= (uint32_t) value << 16; 1185 + s->frame_index_f1 &= 0x0000ffff;
  1186 + s->frame_index_f1 |= (uint32_t) value << 16;
1165 break; 1187 break;
1166 1188
1167 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1189 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1168 - s->lcd_ch.element_index_f2 = value; 1190 + s->element_index_f2 = value;
1169 break; 1191 break;
1170 1192
1171 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1193 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1172 - s->lcd_ch.frame_index_f2 &= 0xffff0000;  
1173 - s->lcd_ch.frame_index_f2 |= 0x0000ffff & value; 1194 + s->frame_index_f2 &= 0xffff0000;
  1195 + s->frame_index_f2 |= 0x0000ffff & value;
1174 break; 1196 break;
1175 1197
1176 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1198 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1177 - s->lcd_ch.frame_index_f2 &= 0x0000ffff;  
1178 - s->lcd_ch.frame_index_f2 |= (uint32_t) value << 16; 1199 + s->frame_index_f2 &= 0x0000ffff;
  1200 + s->frame_index_f2 |= (uint32_t) value << 16;
1179 break; 1201 break;
1180 1202
1181 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1203 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1182 - s->lcd_ch.elements_f1 = value; 1204 + s->elements_f1 = value;
1183 break; 1205 break;
1184 1206
1185 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1207 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1186 - s->lcd_ch.frames_f1 = value; 1208 + s->frames_f1 = value;
1187 break; 1209 break;
1188 1210
1189 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1211 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1190 - s->lcd_ch.elements_f2 = value; 1212 + s->elements_f2 = value;
1191 break; 1213 break;
1192 1214
1193 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1215 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1194 - s->lcd_ch.frames_f2 = value; 1216 + s->frames_f2 = value;
1195 break; 1217 break;
1196 1218
1197 case 0xbea: /* DMA_LCD_LCH_CTRL */ 1219 case 0xbea: /* DMA_LCD_LCH_CTRL */
1198 - s->lcd_ch.lch_type = value & 0xf; 1220 + s->lch_type = value & 0xf;
1199 break; 1221 break;
1200 1222
1201 default: 1223 default:
@@ -1204,114 +1226,114 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_s *s, int offset, @@ -1204,114 +1226,114 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_s *s, int offset,
1204 return 0; 1226 return 0;
1205 } 1227 }
1206 1228
1207 -static int omap_dma_3_2_lcd_read(struct omap_dma_s *s, int offset, 1229 +static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1208 uint16_t *ret) 1230 uint16_t *ret)
1209 { 1231 {
1210 switch (offset) { 1232 switch (offset) {
1211 case 0xbc0: /* DMA_LCD_CSDP */ 1233 case 0xbc0: /* DMA_LCD_CSDP */
1212 - *ret = (s->lcd_ch.brust_f2 << 14) |  
1213 - (s->lcd_ch.pack_f2 << 13) |  
1214 - ((s->lcd_ch.data_type_f2 >> 1) << 11) |  
1215 - (s->lcd_ch.brust_f1 << 7) |  
1216 - (s->lcd_ch.pack_f1 << 6) |  
1217 - ((s->lcd_ch.data_type_f1 >> 1) << 0); 1234 + *ret = (s->brust_f2 << 14) |
  1235 + (s->pack_f2 << 13) |
  1236 + ((s->data_type_f2 >> 1) << 11) |
  1237 + (s->brust_f1 << 7) |
  1238 + (s->pack_f1 << 6) |
  1239 + ((s->data_type_f1 >> 1) << 0);
1218 break; 1240 break;
1219 1241
1220 case 0xbc2: /* DMA_LCD_CCR */ 1242 case 0xbc2: /* DMA_LCD_CCR */
1221 - *ret = (s->lcd_ch.mode_f2 << 14) |  
1222 - (s->lcd_ch.mode_f1 << 12) |  
1223 - (s->lcd_ch.end_prog << 11) |  
1224 - (s->lcd_ch.omap_3_1_compatible_disable << 10) |  
1225 - (s->lcd_ch.repeat << 9) |  
1226 - (s->lcd_ch.auto_init << 8) |  
1227 - (s->lcd_ch.running << 7) |  
1228 - (s->lcd_ch.priority << 6) |  
1229 - (s->lcd_ch.bs << 4); 1243 + *ret = (s->mode_f2 << 14) |
  1244 + (s->mode_f1 << 12) |
  1245 + (s->end_prog << 11) |
  1246 + (s->omap_3_1_compatible_disable << 10) |
  1247 + (s->repeat << 9) |
  1248 + (s->auto_init << 8) |
  1249 + (s->running << 7) |
  1250 + (s->priority << 6) |
  1251 + (s->bs << 4);
1230 break; 1252 break;
1231 1253
1232 case 0xbc4: /* DMA_LCD_CTRL */ 1254 case 0xbc4: /* DMA_LCD_CTRL */
1233 - qemu_irq_lower(s->lcd_ch.irq);  
1234 - *ret = (s->lcd_ch.dst << 8) |  
1235 - ((s->lcd_ch.src & 0x6) << 5) |  
1236 - (s->lcd_ch.condition << 3) |  
1237 - (s->lcd_ch.interrupts << 1) |  
1238 - s->lcd_ch.dual; 1255 + qemu_irq_lower(s->irq);
  1256 + *ret = (s->dst << 8) |
  1257 + ((s->src & 0x6) << 5) |
  1258 + (s->condition << 3) |
  1259 + (s->interrupts << 1) |
  1260 + s->dual;
1239 break; 1261 break;
1240 1262
1241 case 0xbc8: /* TOP_B1_L */ 1263 case 0xbc8: /* TOP_B1_L */
1242 - *ret = s->lcd_ch.src_f1_top & 0xffff; 1264 + *ret = s->src_f1_top & 0xffff;
1243 break; 1265 break;
1244 1266
1245 case 0xbca: /* TOP_B1_U */ 1267 case 0xbca: /* TOP_B1_U */
1246 - *ret = s->lcd_ch.src_f1_top >> 16; 1268 + *ret = s->src_f1_top >> 16;
1247 break; 1269 break;
1248 1270
1249 case 0xbcc: /* BOT_B1_L */ 1271 case 0xbcc: /* BOT_B1_L */
1250 - *ret = s->lcd_ch.src_f1_bottom & 0xffff; 1272 + *ret = s->src_f1_bottom & 0xffff;
1251 break; 1273 break;
1252 1274
1253 case 0xbce: /* BOT_B1_U */ 1275 case 0xbce: /* BOT_B1_U */
1254 - *ret = s->lcd_ch.src_f1_bottom >> 16; 1276 + *ret = s->src_f1_bottom >> 16;
1255 break; 1277 break;
1256 1278
1257 case 0xbd0: /* TOP_B2_L */ 1279 case 0xbd0: /* TOP_B2_L */
1258 - *ret = s->lcd_ch.src_f2_top & 0xffff; 1280 + *ret = s->src_f2_top & 0xffff;
1259 break; 1281 break;
1260 1282
1261 case 0xbd2: /* TOP_B2_U */ 1283 case 0xbd2: /* TOP_B2_U */
1262 - *ret = s->lcd_ch.src_f2_top >> 16; 1284 + *ret = s->src_f2_top >> 16;
1263 break; 1285 break;
1264 1286
1265 case 0xbd4: /* BOT_B2_L */ 1287 case 0xbd4: /* BOT_B2_L */
1266 - *ret = s->lcd_ch.src_f2_bottom & 0xffff; 1288 + *ret = s->src_f2_bottom & 0xffff;
1267 break; 1289 break;
1268 1290
1269 case 0xbd6: /* BOT_B2_U */ 1291 case 0xbd6: /* BOT_B2_U */
1270 - *ret = s->lcd_ch.src_f2_bottom >> 16; 1292 + *ret = s->src_f2_bottom >> 16;
1271 break; 1293 break;
1272 1294
1273 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ 1295 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1274 - *ret = s->lcd_ch.element_index_f1; 1296 + *ret = s->element_index_f1;
1275 break; 1297 break;
1276 1298
1277 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ 1299 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1278 - *ret = s->lcd_ch.frame_index_f1 & 0xffff; 1300 + *ret = s->frame_index_f1 & 0xffff;
1279 break; 1301 break;
1280 1302
1281 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ 1303 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1282 - *ret = s->lcd_ch.frame_index_f1 >> 16; 1304 + *ret = s->frame_index_f1 >> 16;
1283 break; 1305 break;
1284 1306
1285 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ 1307 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1286 - *ret = s->lcd_ch.element_index_f2; 1308 + *ret = s->element_index_f2;
1287 break; 1309 break;
1288 1310
1289 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ 1311 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1290 - *ret = s->lcd_ch.frame_index_f2 & 0xffff; 1312 + *ret = s->frame_index_f2 & 0xffff;
1291 break; 1313 break;
1292 1314
1293 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ 1315 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1294 - *ret = s->lcd_ch.frame_index_f2 >> 16; 1316 + *ret = s->frame_index_f2 >> 16;
1295 break; 1317 break;
1296 1318
1297 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ 1319 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1298 - *ret = s->lcd_ch.elements_f1; 1320 + *ret = s->elements_f1;
1299 break; 1321 break;
1300 1322
1301 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ 1323 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1302 - *ret = s->lcd_ch.frames_f1; 1324 + *ret = s->frames_f1;
1303 break; 1325 break;
1304 1326
1305 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ 1327 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1306 - *ret = s->lcd_ch.elements_f2; 1328 + *ret = s->elements_f2;
1307 break; 1329 break;
1308 1330
1309 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ 1331 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1310 - *ret = s->lcd_ch.frames_f2; 1332 + *ret = s->frames_f2;
1311 break; 1333 break;
1312 1334
1313 case 0xbea: /* DMA_LCD_LCH_CTRL */ 1335 case 0xbea: /* DMA_LCD_LCH_CTRL */
1314 - *ret = s->lcd_ch.lch_type; 1336 + *ret = s->lch_type;
1315 break; 1337 break;
1316 1338
1317 default: 1339 default:
@@ -1320,56 +1342,56 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_s *s, int offset, @@ -1320,56 +1342,56 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_s *s, int offset,
1320 return 0; 1342 return 0;
1321 } 1343 }
1322 1344
1323 -static int omap_dma_3_1_lcd_write(struct omap_dma_s *s, int offset, 1345 +static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1324 uint16_t value) 1346 uint16_t value)
1325 { 1347 {
1326 switch (offset) { 1348 switch (offset) {
1327 case 0x300: /* SYS_DMA_LCD_CTRL */ 1349 case 0x300: /* SYS_DMA_LCD_CTRL */
1328 - s->lcd_ch.src = (value & 0x40) ? imif : emiff;  
1329 - s->lcd_ch.condition = 0; 1350 + s->src = (value & 0x40) ? imif : emiff;
  1351 + s->condition = 0;
1330 /* Assume no bus errors and thus no BUS_ERROR irq bits. */ 1352 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1331 - s->lcd_ch.interrupts = (value >> 1) & 1;  
1332 - s->lcd_ch.dual = value & 1; 1353 + s->interrupts = (value >> 1) & 1;
  1354 + s->dual = value & 1;
1333 break; 1355 break;
1334 1356
1335 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1357 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1336 - s->lcd_ch.src_f1_top &= 0xffff0000;  
1337 - s->lcd_ch.src_f1_top |= 0x0000ffff & value; 1358 + s->src_f1_top &= 0xffff0000;
  1359 + s->src_f1_top |= 0x0000ffff & value;
1338 break; 1360 break;
1339 1361
1340 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1362 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1341 - s->lcd_ch.src_f1_top &= 0x0000ffff;  
1342 - s->lcd_ch.src_f1_top |= value << 16; 1363 + s->src_f1_top &= 0x0000ffff;
  1364 + s->src_f1_top |= value << 16;
1343 break; 1365 break;
1344 1366
1345 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1367 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1346 - s->lcd_ch.src_f1_bottom &= 0xffff0000;  
1347 - s->lcd_ch.src_f1_bottom |= 0x0000ffff & value; 1368 + s->src_f1_bottom &= 0xffff0000;
  1369 + s->src_f1_bottom |= 0x0000ffff & value;
1348 break; 1370 break;
1349 1371
1350 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1372 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1351 - s->lcd_ch.src_f1_bottom &= 0x0000ffff;  
1352 - s->lcd_ch.src_f1_bottom |= value << 16; 1373 + s->src_f1_bottom &= 0x0000ffff;
  1374 + s->src_f1_bottom |= value << 16;
1353 break; 1375 break;
1354 1376
1355 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1377 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1356 - s->lcd_ch.src_f2_top &= 0xffff0000;  
1357 - s->lcd_ch.src_f2_top |= 0x0000ffff & value; 1378 + s->src_f2_top &= 0xffff0000;
  1379 + s->src_f2_top |= 0x0000ffff & value;
1358 break; 1380 break;
1359 1381
1360 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1382 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1361 - s->lcd_ch.src_f2_top &= 0x0000ffff;  
1362 - s->lcd_ch.src_f2_top |= value << 16; 1383 + s->src_f2_top &= 0x0000ffff;
  1384 + s->src_f2_top |= value << 16;
1363 break; 1385 break;
1364 1386
1365 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1387 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1366 - s->lcd_ch.src_f2_bottom &= 0xffff0000;  
1367 - s->lcd_ch.src_f2_bottom |= 0x0000ffff & value; 1388 + s->src_f2_bottom &= 0xffff0000;
  1389 + s->src_f2_bottom |= 0x0000ffff & value;
1368 break; 1390 break;
1369 1391
1370 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1392 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1371 - s->lcd_ch.src_f2_bottom &= 0x0000ffff;  
1372 - s->lcd_ch.src_f2_bottom |= value << 16; 1393 + s->src_f2_bottom &= 0x0000ffff;
  1394 + s->src_f2_bottom |= value << 16;
1373 break; 1395 break;
1374 1396
1375 default: 1397 default:
@@ -1378,50 +1400,50 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_s *s, int offset, @@ -1378,50 +1400,50 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_s *s, int offset,
1378 return 0; 1400 return 0;
1379 } 1401 }
1380 1402
1381 -static int omap_dma_3_1_lcd_read(struct omap_dma_s *s, int offset, 1403 +static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1382 uint16_t *ret) 1404 uint16_t *ret)
1383 { 1405 {
1384 int i; 1406 int i;
1385 1407
1386 switch (offset) { 1408 switch (offset) {
1387 case 0x300: /* SYS_DMA_LCD_CTRL */ 1409 case 0x300: /* SYS_DMA_LCD_CTRL */
1388 - i = s->lcd_ch.condition;  
1389 - s->lcd_ch.condition = 0;  
1390 - qemu_irq_lower(s->lcd_ch.irq);  
1391 - *ret = ((s->lcd_ch.src == imif) << 6) | (i << 3) |  
1392 - (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual; 1410 + i = s->condition;
  1411 + s->condition = 0;
  1412 + qemu_irq_lower(s->irq);
  1413 + *ret = ((s->src == imif) << 6) | (i << 3) |
  1414 + (s->interrupts << 1) | s->dual;
1393 break; 1415 break;
1394 1416
1395 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ 1417 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1396 - *ret = s->lcd_ch.src_f1_top & 0xffff; 1418 + *ret = s->src_f1_top & 0xffff;
1397 break; 1419 break;
1398 1420
1399 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ 1421 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1400 - *ret = s->lcd_ch.src_f1_top >> 16; 1422 + *ret = s->src_f1_top >> 16;
1401 break; 1423 break;
1402 1424
1403 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ 1425 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1404 - *ret = s->lcd_ch.src_f1_bottom & 0xffff; 1426 + *ret = s->src_f1_bottom & 0xffff;
1405 break; 1427 break;
1406 1428
1407 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ 1429 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1408 - *ret = s->lcd_ch.src_f1_bottom >> 16; 1430 + *ret = s->src_f1_bottom >> 16;
1409 break; 1431 break;
1410 1432
1411 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ 1433 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1412 - *ret = s->lcd_ch.src_f2_top & 0xffff; 1434 + *ret = s->src_f2_top & 0xffff;
1413 break; 1435 break;
1414 1436
1415 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ 1437 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1416 - *ret = s->lcd_ch.src_f2_top >> 16; 1438 + *ret = s->src_f2_top >> 16;
1417 break; 1439 break;
1418 1440
1419 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ 1441 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1420 - *ret = s->lcd_ch.src_f2_bottom & 0xffff; 1442 + *ret = s->src_f2_bottom & 0xffff;
1421 break; 1443 break;
1422 1444
1423 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ 1445 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1424 - *ret = s->lcd_ch.src_f2_bottom >> 16; 1446 + *ret = s->src_f2_bottom >> 16;
1425 break; 1447 break;
1426 1448
1427 default: 1449 default:
@@ -1549,7 +1571,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) @@ -1549,7 +1571,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1549 switch (offset) { 1571 switch (offset) {
1550 case 0x300 ... 0x3fe: 1572 case 0x300 ... 0x3fe:
1551 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1573 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1552 - if (omap_dma_3_1_lcd_read(s, offset, &ret)) 1574 + if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
1553 break; 1575 break;
1554 return ret; 1576 return ret;
1555 } 1577 }
@@ -1557,7 +1579,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) @@ -1557,7 +1579,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1557 case 0x000 ... 0x2fe: 1579 case 0x000 ... 0x2fe:
1558 reg = offset & 0x3f; 1580 reg = offset & 0x3f;
1559 ch = (offset >> 6) & 0x0f; 1581 ch = (offset >> 6) & 0x0f;
1560 - if (omap_dma_ch_reg_read(s, ch, reg, &ret)) 1582 + if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1561 break; 1583 break;
1562 return ret; 1584 return ret;
1563 1585
@@ -1572,7 +1594,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) @@ -1572,7 +1594,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1572 1594
1573 case 0xb00 ... 0xbfe: 1595 case 0xb00 ... 0xbfe:
1574 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1596 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1575 - if (omap_dma_3_2_lcd_read(s, offset, &ret)) 1597 + if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
1576 break; 1598 break;
1577 return ret; 1599 return ret;
1578 } 1600 }
@@ -1592,7 +1614,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr, @@ -1592,7 +1614,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1592 switch (offset) { 1614 switch (offset) {
1593 case 0x300 ... 0x3fe: 1615 case 0x300 ... 0x3fe:
1594 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { 1616 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1595 - if (omap_dma_3_1_lcd_write(s, offset, value)) 1617 + if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
1596 break; 1618 break;
1597 return; 1619 return;
1598 } 1620 }
@@ -1600,7 +1622,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr, @@ -1600,7 +1622,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1600 case 0x000 ... 0x2fe: 1622 case 0x000 ... 0x2fe:
1601 reg = offset & 0x3f; 1623 reg = offset & 0x3f;
1602 ch = (offset >> 6) & 0x0f; 1624 ch = (offset >> 6) & 0x0f;
1603 - if (omap_dma_ch_reg_write(s, ch, reg, value)) 1625 + if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1604 break; 1626 break;
1605 return; 1627 return;
1606 1628
@@ -1615,7 +1637,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr, @@ -1615,7 +1637,7 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1615 1637
1616 case 0xb00 ... 0xbfe: 1638 case 0xb00 ... 0xbfe:
1617 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { 1639 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1618 - if (omap_dma_3_2_lcd_write(s, offset, value)) 1640 + if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
1619 break; 1641 break;
1620 return; 1642 return;
1621 } 1643 }
@@ -1669,7 +1691,7 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, @@ -1669,7 +1691,7 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1669 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 1691 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1670 enum omap_dma_model model) 1692 enum omap_dma_model model)
1671 { 1693 {
1672 - int iomemtype, num_irqs, memsize; 1694 + int iomemtype, num_irqs, memsize, i;
1673 struct omap_dma_s *s = (struct omap_dma_s *) 1695 struct omap_dma_s *s = (struct omap_dma_s *)
1674 qemu_mallocz(sizeof(struct omap_dma_s)); 1696 qemu_mallocz(sizeof(struct omap_dma_s));
1675 1697
@@ -1680,13 +1702,18 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, @@ -1680,13 +1702,18 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1680 num_irqs = 16; 1702 num_irqs = 16;
1681 memsize = 0xc00; 1703 memsize = 0xc00;
1682 } 1704 }
1683 - memcpy(s->irqs, irqs, num_irqs * sizeof(qemu_irq));  
1684 s->base = base; 1705 s->base = base;
1685 s->model = model; 1706 s->model = model;
1686 s->mpu = mpu; 1707 s->mpu = mpu;
1687 s->clk = clk; 1708 s->clk = clk;
1688 s->lcd_ch.irq = lcd_irq; 1709 s->lcd_ch.irq = lcd_irq;
1689 s->lcd_ch.mpu = mpu; 1710 s->lcd_ch.mpu = mpu;
  1711 + while (num_irqs --)
  1712 + s->ch[num_irqs].irq = irqs[num_irqs];
  1713 + for (i = 0; i < 3; i ++) {
  1714 + s->ch[i].sibling = &s->ch[i + 6];
  1715 + s->ch[i + 6].sibling = &s->ch[i];
  1716 + }
1690 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); 1717 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1691 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); 1718 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1692 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32); 1719 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);