gwj / at91sam9263 · Commits

Commit 0fa85d43d47151e71e63754e419340bfcff97e80

Authored by bellard
1 parent b4ff5987

64 bit target support 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1195 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 10 changed files with 84 additions and 66 deletions
target-arm/translate.c
  View file @0fa85d4
... ... @@ -29,7 +29,7 @@
29 29  
30 30 /* internal defines */
31 31 typedef struct DisasContext {
32   - uint8_t *pc;
  32 + target_ulong pc;
33 33 int is_jmp;
34 34 struct TranslationBlock *tb;
35 35 } DisasContext;
... ... @@ -762,10 +762,10 @@ static inline int gen_intermediate_code_internal(CPUState *env,
762 762 DisasContext dc1, *dc = &dc1;
763 763 uint16_t *gen_opc_end;
764 764 int j, lj;
765   - uint8_t *pc_start;
  765 + target_ulong pc_start;
766 766  
767 767 /* generate intermediate code */
768   - pc_start = (uint8_t *)tb->pc;
  768 + pc_start = tb->pc;
769 769  
770 770 dc->tb = tb;
771 771  
... ... @@ -784,7 +784,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
784 784 while (lj < j)
785 785 gen_opc_instr_start[lj++] = 0;
786 786 }
787   - gen_opc_pc[lj] = (uint32_t)dc->pc;
  787 + gen_opc_pc[lj] = dc->pc;
788 788 gen_opc_instr_start[lj] = 1;
789 789 }
790 790 disas_arm_insn(dc);
... ... @@ -811,7 +811,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
811 811 if (loglevel & CPU_LOG_TB_IN_ASM) {
812 812 fprintf(logfile, "----------------\n");
813 813 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
814   - disas(logfile, pc_start, dc->pc - pc_start, 0, 0);
  814 + target_disas(logfile, pc_start, dc->pc - pc_start, 0);
815 815 fprintf(logfile, "\n");
816 816 if (loglevel & (CPU_LOG_TB_OP)) {
817 817 fprintf(logfile, "OP:\n");
... ...
target-ppc/exec.h
  View file @0fa85d4
... ... @@ -173,4 +173,7 @@ static inline void regs_to_env(void)
173 173 {
174 174 }
175 175  
  176 +int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
  177 + int is_user, int is_softmmu);
  178 +
176 179 #endif /* !defined (__PPC_H__) */
... ...
target-ppc/helper.c
  View file @0fa85d4
... ... @@ -29,8 +29,6 @@
29 29  
30 30 /*****************************************************************************/
31 31 /* PPC MMU emulation */
32   -int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
33   - int is_user, int is_softmmu);
34 32  
35 33 /* Perform BAT hit & translation */
36 34 static int get_bat (CPUState *env, uint32_t *real, int *prot,
... ... @@ -421,7 +419,7 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
421 419 NULL, it means that the function was called in C code (i.e. not
422 420 from generated code or from helper.c) */
423 421 /* XXX: fix it to restore all registers */
424   -void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
  422 +void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
425 423 {
426 424 TranslationBlock *tb;
427 425 CPUState *saved_env;
... ... @@ -782,7 +780,7 @@ void do_interrupt (CPUState *env)
782 780 /* Store exception cause */
783 781 /* Get rS/rD and rA from faulting opcode */
784 782 env->spr[DSISR] |=
785   - (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
  783 + (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
786 784 /* data location address has been stored
787 785 * when the fault has been detected
788 786 */
... ...
target-ppc/op_helper_mem.h
  View file @0fa85d4
... ... @@ -8,14 +8,14 @@ void glue(do_lsw, MEMSUFFIX) (int dst)
8 8 __func__, T0, T1, dst);
9 9 }
10 10 for (; T1 > 3; T1 -= 4, T0 += 4) {
11   - ugpr(dst++) = glue(ldl, MEMSUFFIX)((void *)T0);
  11 + ugpr(dst++) = glue(ldl, MEMSUFFIX)(T0);
12 12 if (dst == 32)
13 13 dst = 0;
14 14 }
15 15 if (T1 > 0) {
16 16 tmp = 0;
17 17 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
18   - tmp |= glue(ldub, MEMSUFFIX)((void *)T0) << sh;
  18 + tmp |= glue(ldub, MEMSUFFIX)(T0) << sh;
19 19 }
20 20 ugpr(dst) = tmp;
21 21 }
... ... @@ -30,13 +30,13 @@ void glue(do_stsw, MEMSUFFIX) (int src)
30 30 __func__, T0, T1, src);
31 31 }
32 32 for (; T1 > 3; T1 -= 4, T0 += 4) {
33   - glue(stl, MEMSUFFIX)((void *)T0, ugpr(src++));
  33 + glue(stl, MEMSUFFIX)(T0, ugpr(src++));
34 34 if (src == 32)
35 35 src = 0;
36 36 }
37 37 if (T1 > 0) {
38 38 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
39   - glue(stb, MEMSUFFIX)((void *)T0, (ugpr(src) >> sh) & 0xFF);
  39 + glue(stb, MEMSUFFIX)(T0, (ugpr(src) >> sh) & 0xFF);
40 40 }
41 41 }
42 42  
... ...
target-ppc/op_mem.h
  View file @0fa85d4
... ... @@ -2,26 +2,26 @@
2 2 void glue(do_lsw, MEMSUFFIX) (int dst);
3 3 void glue(do_stsw, MEMSUFFIX) (int src);
4 4  
5   -static inline uint16_t glue(ld16r, MEMSUFFIX) (void *EA)
  5 +static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA)
6 6 {
7 7 uint16_t tmp = glue(lduw, MEMSUFFIX)(EA);
8 8 return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
9 9 }
10 10  
11   -static inline uint32_t glue(ld32r, MEMSUFFIX) (void *EA)
  11 +static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA)
12 12 {
13 13 uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
14 14 return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
15 15 ((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
16 16 }
17 17  
18   -static inline void glue(st16r, MEMSUFFIX) (void *EA, uint16_t data)
  18 +static inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t data)
19 19 {
20 20 uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
21 21 glue(stw, MEMSUFFIX)(EA, tmp);
22 22 }
23 23  
24   -static inline void glue(st32r, MEMSUFFIX) (void *EA, uint32_t data)
  24 +static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data)
25 25 {
26 26 uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) |
27 27 ((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24);
... ... @@ -32,14 +32,14 @@ static inline void glue(st32r, MEMSUFFIX) (void *EA, uint32_t data)
32 32 #define PPC_LD_OP(name, op) \
33 33 PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
34 34 { \
35   - T1 = glue(op, MEMSUFFIX)((void *)T0); \
  35 + T1 = glue(op, MEMSUFFIX)(T0); \
36 36 RETURN(); \
37 37 }
38 38  
39 39 #define PPC_ST_OP(name, op) \
40 40 PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
41 41 { \
42   - glue(op, MEMSUFFIX)((void *)T0, T1); \
  42 + glue(op, MEMSUFFIX)(T0, T1); \
43 43 RETURN(); \
44 44 }
45 45  
... ... @@ -65,7 +65,7 @@ PPC_OP(glue(lmw, MEMSUFFIX))
65 65 int dst = PARAM(1);
66 66  
67 67 for (; dst < 32; dst++, T0 += 4) {
68   - ugpr(dst) = glue(ldl, MEMSUFFIX)((void *)T0);
  68 + ugpr(dst) = glue(ldl, MEMSUFFIX)(T0);
69 69 }
70 70 RETURN();
71 71 }
... ... @@ -75,7 +75,7 @@ PPC_OP(glue(stmw, MEMSUFFIX))
75 75 int src = PARAM(1);
76 76  
77 77 for (; src < 32; src++, T0 += 4) {
78   - glue(stl, MEMSUFFIX)((void *)T0, ugpr(src));
  78 + glue(stl, MEMSUFFIX)(T0, ugpr(src));
79 79 }
80 80 RETURN();
81 81 }
... ... @@ -115,7 +115,7 @@ PPC_OP(glue(stsw, MEMSUFFIX))
115 115 #define PPC_STF_OP(name, op) \
116 116 PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
117 117 { \
118   - glue(op, MEMSUFFIX)((void *)T0, FT1); \
  118 + glue(op, MEMSUFFIX)(T0, FT1); \
119 119 RETURN(); \
120 120 }
121 121  
... ... @@ -126,7 +126,7 @@ PPC_STF_OP(fs, stfl);
126 126 #define PPC_LDF_OP(name, op) \
127 127 PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
128 128 { \
129   - FT1 = glue(op, MEMSUFFIX)((void *)T0); \
  129 + FT1 = glue(op, MEMSUFFIX)(T0); \
130 130 RETURN(); \
131 131 }
132 132  
... ... @@ -139,7 +139,7 @@ PPC_OP(glue(lwarx, MEMSUFFIX))
139 139 if (T0 & 0x03) {
140 140 do_raise_exception(EXCP_ALIGN);
141 141 } else {
142   - T1 = glue(ldl, MEMSUFFIX)((void *)T0);
  142 + T1 = glue(ldl, MEMSUFFIX)(T0);
143 143 regs->reserve = T0;
144 144 }
145 145 RETURN();
... ... @@ -154,7 +154,7 @@ PPC_OP(glue(stwcx, MEMSUFFIX))
154 154 if (regs->reserve != T0) {
155 155 env->crf[0] = xer_ov;
156 156 } else {
157   - glue(stl, MEMSUFFIX)((void *)T0, T1);
  157 + glue(stl, MEMSUFFIX)(T0, T1);
158 158 env->crf[0] = xer_ov | 0x02;
159 159 }
160 160 }
... ... @@ -164,27 +164,27 @@ PPC_OP(glue(stwcx, MEMSUFFIX))
164 164  
165 165 PPC_OP(glue(dcbz, MEMSUFFIX))
166 166 {
167   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x00), 0);
168   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x04), 0);
169   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x08), 0);
170   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x0C), 0);
171   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x10), 0);
172   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x14), 0);
173   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x18), 0);
174   - glue(stl, MEMSUFFIX)((void *)(T0 + 0x1C), 0);
  167 + glue(stl, MEMSUFFIX)(T0 + 0x00, 0);
  168 + glue(stl, MEMSUFFIX)(T0 + 0x04, 0);
  169 + glue(stl, MEMSUFFIX)(T0 + 0x08, 0);
  170 + glue(stl, MEMSUFFIX)(T0 + 0x0C, 0);
  171 + glue(stl, MEMSUFFIX)(T0 + 0x10, 0);
  172 + glue(stl, MEMSUFFIX)(T0 + 0x14, 0);
  173 + glue(stl, MEMSUFFIX)(T0 + 0x18, 0);
  174 + glue(stl, MEMSUFFIX)(T0 + 0x1C, 0);
175 175 RETURN();
176 176 }
177 177  
178 178 /* External access */
179 179 PPC_OP(glue(eciwx, MEMSUFFIX))
180 180 {
181   - T1 = glue(ldl, MEMSUFFIX)((void *)T0);
  181 + T1 = glue(ldl, MEMSUFFIX)(T0);
182 182 RETURN();
183 183 }
184 184  
185 185 PPC_OP(glue(ecowx, MEMSUFFIX))
186 186 {
187   - glue(stl, MEMSUFFIX)((void *)T0, T1);
  187 + glue(stl, MEMSUFFIX)(T0, T1);
188 188 RETURN();
189 189 }
190 190  
... ...
target-ppc/translate.c
  View file @0fa85d4
... ... @@ -131,7 +131,7 @@ static uint8_t spr_access[1024 / 2];
131 131 /* internal defines */
132 132 typedef struct DisasContext {
133 133 struct TranslationBlock *tb;
134   - uint32_t nip;
  134 + target_ulong nip;
135 135 uint32_t opcode;
136 136 uint32_t exception;
137 137 /* Execution mode */
... ... @@ -3029,7 +3029,7 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3029 3029 {
3030 3030 DisasContext ctx, *ctxp = &ctx;
3031 3031 opc_handler_t **table, *handler;
3032   - uint32_t pc_start;
  3032 + target_ulong pc_start;
3033 3033 uint16_t *gen_opc_end;
3034 3034 int j, lj = -1;
3035 3035  
... ... @@ -3069,7 +3069,7 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3069 3069 ctx.nip, 1 - msr_pr, msr_ir);
3070 3070 }
3071 3071 #endif
3072   - ctx.opcode = ldl_code((void *)ctx.nip);
  3072 + ctx.opcode = ldl_code(ctx.nip);
3073 3073 #if defined PPC_DEBUG_DISAS
3074 3074 if (loglevel & CPU_LOG_TB_IN_ASM) {
3075 3075 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
... ... @@ -3174,8 +3174,8 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3174 3174 cpu_dump_state(env, logfile, fprintf, 0);
3175 3175 }
3176 3176 if (loglevel & CPU_LOG_TB_IN_ASM) {
3177   - fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3178   - disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
  3177 + fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
  3178 + target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
3179 3179 fprintf(logfile, "\n");
3180 3180 }
3181 3181 if (loglevel & CPU_LOG_TB_OP) {
... ...
target-sparc/helper.c
  View file @0fa85d4
... ... @@ -62,7 +62,7 @@ void cpu_unlock(void)
62 62 NULL, it means that the function was called in C code (i.e. not
63 63 from generated code or from helper.c) */
64 64 /* XXX: fix it to restore all registers */
65   -void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
  65 +void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
66 66 {
67 67 TranslationBlock *tb;
68 68 int ret;
... ... @@ -282,6 +282,15 @@ void set_cwp(int new_cwp)
282 282 env->regwptr = env->regbase + (new_cwp * 16);
283 283 }
284 284  
  285 +void cpu_set_cwp(CPUState *env1, int new_cwp)
  286 +{
  287 + CPUState *saved_env;
  288 + saved_env = env;
  289 + env = env1;
  290 + set_cwp(new_cwp);
  291 + env = saved_env;
  292 +}
  293 +
285 294 /*
286 295 * Begin execution of an interruption. is_int is TRUE if coming from
287 296 * the int instruction. next_eip is the EIP value AFTER the interrupt
... ... @@ -318,8 +327,7 @@ void do_interrupt(int intno, int is_int, int error_code,
318 327 #endif
319 328 #if !defined(CONFIG_USER_ONLY)
320 329 if (env->psret == 0) {
321   - fprintf(logfile, "Trap while interrupts disabled, Error state!\n");
322   - qemu_system_shutdown_request();
  330 + cpu_abort(cpu_single_env, "Trap while interrupts disabled, Error state");
323 331 return;
324 332 }
325 333 #endif
... ...
target-sparc/op_helper.c
  View file @0fa85d4
... ... @@ -108,7 +108,7 @@ void helper_ld_asi(int asi, int size, int sign)
108 108 if (size == 4)
109 109 bswap32s(&ret);
110 110 else if (size == 2)
111   - bswap16s(&ret);
  111 + bswap16s((uint16_t *)&ret);
112 112 break;
113 113 default:
114 114 ret = 0;
... ... @@ -198,7 +198,7 @@ void helper_st_asi(int asi, int size, int sign)
198 198 if (size == 4)
199 199 bswap32s(&temp);
200 200 else if (size == 2)
201   - bswap16s(&temp);
  201 + bswap16s((uint16_t *)&temp);
202 202  
203 203 cpu_physical_memory_write(T0, (void *) &temp, size);
204 204 }
... ...
target-sparc/op_mem.h
  View file @0fa85d4
... ... @@ -2,13 +2,13 @@
2 2 #define SPARC_LD_OP(name, qp) \
3 3 void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
4 4 { \
5   - T1 = glue(qp, MEMSUFFIX)((void *)T0); \
  5 + T1 = glue(qp, MEMSUFFIX)(T0); \
6 6 }
7 7  
8 8 #define SPARC_ST_OP(name, op) \
9 9 void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
10 10 { \
11   - glue(op, MEMSUFFIX)((void *)T0, T1); \
  11 + glue(op, MEMSUFFIX)(T0, T1); \
12 12 }
13 13  
14 14 SPARC_LD_OP(ld, ldl);
... ... @@ -24,48 +24,48 @@ SPARC_ST_OP(sth, stw);
24 24  
25 25 void OPPROTO glue(op_std, MEMSUFFIX)(void)
26 26 {
27   - glue(stl, MEMSUFFIX)((void *) T0, T1);
28   - glue(stl, MEMSUFFIX)((void *) (T0 + 4), T2);
  27 + glue(stl, MEMSUFFIX)(T0, T1);
  28 + glue(stl, MEMSUFFIX)((T0 + 4), T2);
29 29 }
30 30  
31 31 void OPPROTO glue(op_ldstub, MEMSUFFIX)(void)
32 32 {
33   - T1 = glue(ldub, MEMSUFFIX)((void *) T0);
34   - glue(stb, MEMSUFFIX)((void *) T0, 0xff); /* XXX: Should be Atomically */
  33 + T1 = glue(ldub, MEMSUFFIX)(T0);
  34 + glue(stb, MEMSUFFIX)(T0, 0xff); /* XXX: Should be Atomically */
35 35 }
36 36  
37 37 void OPPROTO glue(op_swap, MEMSUFFIX)(void)
38 38 {
39   - unsigned int tmp = glue(ldl, MEMSUFFIX)((void *) T0);
40   - glue(stl, MEMSUFFIX)((void *) T0, T1); /* XXX: Should be Atomically */
  39 + unsigned int tmp = glue(ldl, MEMSUFFIX)(T0);
  40 + glue(stl, MEMSUFFIX)(T0, T1); /* XXX: Should be Atomically */
41 41 T1 = tmp;
42 42 }
43 43  
44 44 void OPPROTO glue(op_ldd, MEMSUFFIX)(void)
45 45 {
46   - T1 = glue(ldl, MEMSUFFIX)((void *) T0);
47   - T0 = glue(ldl, MEMSUFFIX)((void *) (T0 + 4));
  46 + T1 = glue(ldl, MEMSUFFIX)(T0);
  47 + T0 = glue(ldl, MEMSUFFIX)((T0 + 4));
48 48 }
49 49  
50 50 /*** Floating-point store ***/
51 51 void OPPROTO glue(op_stf, MEMSUFFIX) (void)
52 52 {
53   - glue(stfl, MEMSUFFIX)((void *) T0, FT0);
  53 + glue(stfl, MEMSUFFIX)(T0, FT0);
54 54 }
55 55  
56 56 void OPPROTO glue(op_stdf, MEMSUFFIX) (void)
57 57 {
58   - glue(stfq, MEMSUFFIX)((void *) T0, DT0);
  58 + glue(stfq, MEMSUFFIX)(T0, DT0);
59 59 }
60 60  
61 61 /*** Floating-point load ***/
62 62 void OPPROTO glue(op_ldf, MEMSUFFIX) (void)
63 63 {
64   - FT0 = glue(ldfl, MEMSUFFIX)((void *) T0);
  64 + FT0 = glue(ldfl, MEMSUFFIX)(T0);
65 65 }
66 66  
67 67 void OPPROTO glue(op_lddf, MEMSUFFIX) (void)
68 68 {
69   - DT0 = glue(ldfq, MEMSUFFIX)((void *) T0);
  69 + DT0 = glue(ldfq, MEMSUFFIX)(T0);
70 70 }
71 71 #undef MEMSUFFIX
... ...
target-sparc/translate.c
  View file @0fa85d4
... ... @@ -291,10 +291,7 @@ GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
291 291  
292 292 #if defined(CONFIG_USER_ONLY)
293 293 #define gen_op_ldst(name) gen_op_##name##_raw()
294   -#define OP_LD_TABLE(width) \
295   -static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
296   -{ \
297   -}
  294 +#define OP_LD_TABLE(width)
298 295 #define supervisor(dc) 0
299 296 #else
300 297 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
... ... @@ -614,12 +611,14 @@ static void do_fbranch(DisasContext * dc, uint32_t target, uint32_t insn)
614 611 }
615 612 }
616 613  
  614 +#if 0
617 615 static void gen_debug(DisasContext *s, uint32_t pc)
618 616 {
619 617 gen_op_jmp_im(pc);
620 618 gen_op_debug();
621 619 s->is_br = 1;
622 620 }
  621 +#endif
623 622  
624 623 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
625 624  
... ... @@ -633,7 +632,7 @@ static void disas_sparc_insn(DisasContext * dc)
633 632 {
634 633 unsigned int insn, opc, rs1, rs2, rd;
635 634  
636   - insn = ldl_code((uint8_t *)dc->pc);
  635 + insn = ldl_code(dc->pc);
637 636 opc = GET_FIELD(insn, 0, 1);
638 637  
639 638 rd = GET_FIELD(insn, 2, 6);
... ... @@ -1290,6 +1289,12 @@ static void disas_sparc_insn(DisasContext * dc)
1290 1289 gen_movl_reg_T1(rd);
1291 1290 gen_op_swapa(insn, 1, 4, 0);
1292 1291 break;
  1292 +
  1293 + /* avoid warnings */
  1294 + (void) &gen_op_stfa;
  1295 + (void) &gen_op_stdfa;
  1296 + (void) &gen_op_ldfa;
  1297 + (void) &gen_op_lddfa;
1293 1298 #endif
1294 1299 default:
1295 1300 goto illegal_insn;
... ... @@ -1520,8 +1525,8 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
1520 1525 #ifdef DEBUG_DISAS
1521 1526 if (loglevel & CPU_LOG_TB_IN_ASM) {
1522 1527 fprintf(logfile, "--------------\n");
1523   - fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
1524   - disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0);
  1528 + fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
  1529 + target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
1525 1530 fprintf(logfile, "\n");
1526 1531 if (loglevel & CPU_LOG_TB_OP) {
1527 1532 fprintf(logfile, "OP:\n");
... ... @@ -1626,6 +1631,10 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1626 1631 }
1627 1632  
1628 1633 #else
  1634 +extern int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
  1635 + int *access_index, uint32_t address, int rw,
  1636 + int is_user);
  1637 +
1629 1638 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1630 1639 {
1631 1640 uint32_t phys_addr;
... ...