gwj / at91sam9263 · Commits

Commit 0fa7f157309dedfd715179241a70b43739a45fb1

Authored by ths
1 parent f00cb701

Fix code formatting, by Herve Poussineau. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2958 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 163 additions and 163 deletions
hw/parallel.c
  View file @0fa7f15
@@ -91,29 +91,29 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) @@ -91,29 +91,29 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
91 addr &= 7; 91 addr &= 7;
92 switch(addr) { 92 switch(addr) {
93 case PARA_REG_DATA: 93 case PARA_REG_DATA:
94 - s->dataw = val;  
95 - parallel_update_irq(s); 94 + s->dataw = val;
  95 + parallel_update_irq(s);
96 break; 96 break;
97 case PARA_REG_CTR: 97 case PARA_REG_CTR:
98 - if ((val & PARA_CTR_INIT) == 0 ) {  
99 - s->status = PARA_STS_BUSY;  
100 - s->status |= PARA_STS_ACK;  
101 - s->status |= PARA_STS_ONLINE;  
102 - s->status |= PARA_STS_ERROR;  
103 - }  
104 - else if (val & PARA_CTR_SELECT) {  
105 - if (val & PARA_CTR_STROBE) {  
106 - s->status &= ~PARA_STS_BUSY;  
107 - if ((s->control & PARA_CTR_STROBE) == 0)  
108 - qemu_chr_write(s->chr, &s->dataw, 1);  
109 - } else {  
110 - if (s->control & PARA_CTR_INTEN) {  
111 - s->irq_pending = 1;  
112 - }  
113 - }  
114 - }  
115 - parallel_update_irq(s);  
116 - s->control = val; 98 + if ((val & PARA_CTR_INIT) == 0 ) {
  99 + s->status = PARA_STS_BUSY;
  100 + s->status |= PARA_STS_ACK;
  101 + s->status |= PARA_STS_ONLINE;
  102 + s->status |= PARA_STS_ERROR;
  103 + }
  104 + else if (val & PARA_CTR_SELECT) {
  105 + if (val & PARA_CTR_STROBE) {
  106 + s->status &= ~PARA_STS_BUSY;
  107 + if ((s->control & PARA_CTR_STROBE) == 0)
  108 + qemu_chr_write(s->chr, &s->dataw, 1);
  109 + } else {
  110 + if (s->control & PARA_CTR_INTEN) {
  111 + s->irq_pending = 1;
  112 + }
  113 + }
  114 + }
  115 + parallel_update_irq(s);
  116 + s->control = val;
117 break; 117 break;
118 } 118 }
119 } 119 }
@@ -132,52 +132,52 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) @@ -132,52 +132,52 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
132 switch(addr) { 132 switch(addr) {
133 case PARA_REG_DATA: 133 case PARA_REG_DATA:
134 if (s->dataw == val) 134 if (s->dataw == val)
135 - return;  
136 - pdebug("wd%02x\n", val);  
137 - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);  
138 - s->dataw = val; 135 + return;
  136 + pdebug("wd%02x\n", val);
  137 + qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
  138 + s->dataw = val;
139 break; 139 break;
140 case PARA_REG_STS: 140 case PARA_REG_STS:
141 - pdebug("ws%02x\n", val);  
142 - if (val & PARA_STS_TMOUT)  
143 - s->epp_timeout = 0;  
144 - break; 141 + pdebug("ws%02x\n", val);
  142 + if (val & PARA_STS_TMOUT)
  143 + s->epp_timeout = 0;
  144 + break;
145 case PARA_REG_CTR: 145 case PARA_REG_CTR:
146 val |= 0xc0; 146 val |= 0xc0;
147 if (s->control == val) 147 if (s->control == val)
148 - return;  
149 - pdebug("wc%02x\n", val);  
150 - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);  
151 - s->control = val; 148 + return;
  149 + pdebug("wc%02x\n", val);
  150 + qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
  151 + s->control = val;
152 break; 152 break;
153 case PARA_REG_EPP_ADDR: 153 case PARA_REG_EPP_ADDR:
154 - if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)  
155 - /* Controls not correct for EPP address cycle, so do nothing */  
156 - pdebug("wa%02x s\n", val);  
157 - else {  
158 - struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };  
159 - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {  
160 - s->epp_timeout = 1;  
161 - pdebug("wa%02x t\n", val);  
162 - }  
163 - else  
164 - pdebug("wa%02x\n", val);  
165 - }  
166 - break; 154 + if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
  155 + /* Controls not correct for EPP address cycle, so do nothing */
  156 + pdebug("wa%02x s\n", val);
  157 + else {
  158 + struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
  159 + if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
  160 + s->epp_timeout = 1;
  161 + pdebug("wa%02x t\n", val);
  162 + }
  163 + else
  164 + pdebug("wa%02x\n", val);
  165 + }
  166 + break;
167 case PARA_REG_EPP_DATA: 167 case PARA_REG_EPP_DATA:
168 - if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)  
169 - /* Controls not correct for EPP data cycle, so do nothing */  
170 - pdebug("we%02x s\n", val);  
171 - else {  
172 - struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };  
173 - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {  
174 - s->epp_timeout = 1;  
175 - pdebug("we%02x t\n", val);  
176 - }  
177 - else  
178 - pdebug("we%02x\n", val);  
179 - }  
180 - break; 168 + if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
  169 + /* Controls not correct for EPP data cycle, so do nothing */
  170 + pdebug("we%02x s\n", val);
  171 + else {
  172 + struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
  173 + if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
  174 + s->epp_timeout = 1;
  175 + pdebug("we%02x t\n", val);
  176 + }
  177 + else
  178 + pdebug("we%02x\n", val);
  179 + }
  180 + break;
181 } 181 }
182 } 182 }
183 183
@@ -188,20 +188,20 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) @@ -188,20 +188,20 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
188 uint16_t eppdata = cpu_to_le16(val); 188 uint16_t eppdata = cpu_to_le16(val);
189 int err; 189 int err;
190 struct ParallelIOArg ioarg = { 190 struct ParallelIOArg ioarg = {
191 - .buffer = &eppdata, .count = sizeof(eppdata) 191 + .buffer = &eppdata, .count = sizeof(eppdata)
192 }; 192 };
193 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 193 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
194 - /* Controls not correct for EPP data cycle, so do nothing */  
195 - pdebug("we%04x s\n", val);  
196 - return; 194 + /* Controls not correct for EPP data cycle, so do nothing */
  195 + pdebug("we%04x s\n", val);
  196 + return;
197 } 197 }
198 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 198 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
199 if (err) { 199 if (err) {
200 - s->epp_timeout = 1;  
201 - pdebug("we%04x t\n", val); 200 + s->epp_timeout = 1;
  201 + pdebug("we%04x t\n", val);
202 } 202 }
203 else 203 else
204 - pdebug("we%04x\n", val); 204 + pdebug("we%04x\n", val);
205 } 205 }
206 206
207 static void 207 static void
@@ -211,20 +211,20 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) @@ -211,20 +211,20 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
211 uint32_t eppdata = cpu_to_le32(val); 211 uint32_t eppdata = cpu_to_le32(val);
212 int err; 212 int err;
213 struct ParallelIOArg ioarg = { 213 struct ParallelIOArg ioarg = {
214 - .buffer = &eppdata, .count = sizeof(eppdata) 214 + .buffer = &eppdata, .count = sizeof(eppdata)
215 }; 215 };
216 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 216 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
217 - /* Controls not correct for EPP data cycle, so do nothing */  
218 - pdebug("we%08x s\n", val);  
219 - return; 217 + /* Controls not correct for EPP data cycle, so do nothing */
  218 + pdebug("we%08x s\n", val);
  219 + return;
220 } 220 }
221 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 221 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
222 if (err) { 222 if (err) {
223 - s->epp_timeout = 1;  
224 - pdebug("we%08x t\n", val); 223 + s->epp_timeout = 1;
  224 + pdebug("we%08x t\n", val);
225 } 225 }
226 else 226 else
227 - pdebug("we%08x\n", val); 227 + pdebug("we%08x\n", val);
228 } 228 }
229 229
230 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 230 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
@@ -235,25 +235,25 @@ static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) @@ -235,25 +235,25 @@ static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
235 addr &= 7; 235 addr &= 7;
236 switch(addr) { 236 switch(addr) {
237 case PARA_REG_DATA: 237 case PARA_REG_DATA:
238 - if (s->control & PARA_CTR_DIR)  
239 - ret = s->datar;  
240 - else  
241 - ret = s->dataw; 238 + if (s->control & PARA_CTR_DIR)
  239 + ret = s->datar;
  240 + else
  241 + ret = s->dataw;
242 break; 242 break;
243 case PARA_REG_STS: 243 case PARA_REG_STS:
244 - ret = s->status;  
245 - s->irq_pending = 0;  
246 - if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {  
247 - /* XXX Fixme: wait 5 microseconds */  
248 - if (s->status & PARA_STS_ACK)  
249 - s->status &= ~PARA_STS_ACK;  
250 - else {  
251 - /* XXX Fixme: wait 5 microseconds */  
252 - s->status |= PARA_STS_ACK;  
253 - s->status |= PARA_STS_BUSY;  
254 - }  
255 - }  
256 - parallel_update_irq(s); 244 + ret = s->status;
  245 + s->irq_pending = 0;
  246 + if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
  247 + /* XXX Fixme: wait 5 microseconds */
  248 + if (s->status & PARA_STS_ACK)
  249 + s->status &= ~PARA_STS_ACK;
  250 + else {
  251 + /* XXX Fixme: wait 5 microseconds */
  252 + s->status |= PARA_STS_ACK;
  253 + s->status |= PARA_STS_BUSY;
  254 + }
  255 + }
  256 + parallel_update_irq(s);
257 break; 257 break;
258 case PARA_REG_CTR: 258 case PARA_REG_CTR:
259 ret = s->control; 259 ret = s->control;
@@ -270,63 +270,63 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) @@ -270,63 +270,63 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
270 addr &= 7; 270 addr &= 7;
271 switch(addr) { 271 switch(addr) {
272 case PARA_REG_DATA: 272 case PARA_REG_DATA:
273 - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);  
274 - if (s->last_read_offset != addr || s->datar != ret)  
275 - pdebug("rd%02x\n", ret); 273 + qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
  274 + if (s->last_read_offset != addr || s->datar != ret)
  275 + pdebug("rd%02x\n", ret);
276 s->datar = ret; 276 s->datar = ret;
277 break; 277 break;
278 case PARA_REG_STS: 278 case PARA_REG_STS:
279 - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);  
280 - ret &= ~PARA_STS_TMOUT;  
281 - if (s->epp_timeout)  
282 - ret |= PARA_STS_TMOUT;  
283 - if (s->last_read_offset != addr || s->status != ret)  
284 - pdebug("rs%02x\n", ret);  
285 - s->status = ret; 279 + qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
  280 + ret &= ~PARA_STS_TMOUT;
  281 + if (s->epp_timeout)
  282 + ret |= PARA_STS_TMOUT;
  283 + if (s->last_read_offset != addr || s->status != ret)
  284 + pdebug("rs%02x\n", ret);
  285 + s->status = ret;
286 break; 286 break;
287 case PARA_REG_CTR: 287 case PARA_REG_CTR:
288 /* s->control has some bits fixed to 1. It is zero only when 288 /* s->control has some bits fixed to 1. It is zero only when
289 - it has not been yet written to. */  
290 - if (s->control == 0) {  
291 - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);  
292 - if (s->last_read_offset != addr)  
293 - pdebug("rc%02x\n", ret);  
294 - s->control = ret;  
295 - }  
296 - else {  
297 - ret = s->control;  
298 - if (s->last_read_offset != addr)  
299 - pdebug("rc%02x\n", ret);  
300 - } 289 + it has not been yet written to. */
  290 + if (s->control == 0) {
  291 + qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
  292 + if (s->last_read_offset != addr)
  293 + pdebug("rc%02x\n", ret);
  294 + s->control = ret;
  295 + }
  296 + else {
  297 + ret = s->control;
  298 + if (s->last_read_offset != addr)
  299 + pdebug("rc%02x\n", ret);
  300 + }
301 break; 301 break;
302 case PARA_REG_EPP_ADDR: 302 case PARA_REG_EPP_ADDR:
303 - if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))  
304 - /* Controls not correct for EPP addr cycle, so do nothing */  
305 - pdebug("ra%02x s\n", ret);  
306 - else {  
307 - struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };  
308 - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {  
309 - s->epp_timeout = 1;  
310 - pdebug("ra%02x t\n", ret);  
311 - }  
312 - else  
313 - pdebug("ra%02x\n", ret);  
314 - }  
315 - break; 303 + if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
  304 + /* Controls not correct for EPP addr cycle, so do nothing */
  305 + pdebug("ra%02x s\n", ret);
  306 + else {
  307 + struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
  308 + if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
  309 + s->epp_timeout = 1;
  310 + pdebug("ra%02x t\n", ret);
  311 + }
  312 + else
  313 + pdebug("ra%02x\n", ret);
  314 + }
  315 + break;
316 case PARA_REG_EPP_DATA: 316 case PARA_REG_EPP_DATA:
317 - if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))  
318 - /* Controls not correct for EPP data cycle, so do nothing */  
319 - pdebug("re%02x s\n", ret);  
320 - else {  
321 - struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };  
322 - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {  
323 - s->epp_timeout = 1;  
324 - pdebug("re%02x t\n", ret);  
325 - }  
326 - else  
327 - pdebug("re%02x\n", ret);  
328 - }  
329 - break; 317 + if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
  318 + /* Controls not correct for EPP data cycle, so do nothing */
  319 + pdebug("re%02x s\n", ret);
  320 + else {
  321 + struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
  322 + if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
  323 + s->epp_timeout = 1;
  324 + pdebug("re%02x t\n", ret);
  325 + }
  326 + else
  327 + pdebug("re%02x\n", ret);
  328 + }
  329 + break;
330 } 330 }
331 s->last_read_offset = addr; 331 s->last_read_offset = addr;
332 return ret; 332 return ret;
@@ -340,22 +340,22 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) @@ -340,22 +340,22 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
340 uint16_t eppdata = ~0; 340 uint16_t eppdata = ~0;
341 int err; 341 int err;
342 struct ParallelIOArg ioarg = { 342 struct ParallelIOArg ioarg = {
343 - .buffer = &eppdata, .count = sizeof(eppdata) 343 + .buffer = &eppdata, .count = sizeof(eppdata)
344 }; 344 };
345 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 345 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
346 - /* Controls not correct for EPP data cycle, so do nothing */  
347 - pdebug("re%04x s\n", eppdata);  
348 - return eppdata; 346 + /* Controls not correct for EPP data cycle, so do nothing */
  347 + pdebug("re%04x s\n", eppdata);
  348 + return eppdata;
349 } 349 }
350 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 350 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
351 ret = le16_to_cpu(eppdata); 351 ret = le16_to_cpu(eppdata);
352 352
353 if (err) { 353 if (err) {
354 - s->epp_timeout = 1;  
355 - pdebug("re%04x t\n", ret); 354 + s->epp_timeout = 1;
  355 + pdebug("re%04x t\n", ret);
356 } 356 }
357 else 357 else
358 - pdebug("re%04x\n", ret); 358 + pdebug("re%04x\n", ret);
359 return ret; 359 return ret;
360 } 360 }
361 361
@@ -367,22 +367,22 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) @@ -367,22 +367,22 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
367 uint32_t eppdata = ~0U; 367 uint32_t eppdata = ~0U;
368 int err; 368 int err;
369 struct ParallelIOArg ioarg = { 369 struct ParallelIOArg ioarg = {
370 - .buffer = &eppdata, .count = sizeof(eppdata) 370 + .buffer = &eppdata, .count = sizeof(eppdata)
371 }; 371 };
372 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 372 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
373 - /* Controls not correct for EPP data cycle, so do nothing */  
374 - pdebug("re%08x s\n", eppdata);  
375 - return eppdata; 373 + /* Controls not correct for EPP data cycle, so do nothing */
  374 + pdebug("re%08x s\n", eppdata);
  375 + return eppdata;
376 } 376 }
377 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 377 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
378 ret = le32_to_cpu(eppdata); 378 ret = le32_to_cpu(eppdata);
379 379
380 if (err) { 380 if (err) {
381 - s->epp_timeout = 1;  
382 - pdebug("re%08x t\n", ret); 381 + s->epp_timeout = 1;
  382 + pdebug("re%08x t\n", ret);
383 } 383 }
384 else 384 else
385 - pdebug("re%08x\n", ret); 385 + pdebug("re%08x\n", ret);
386 return ret; 386 return ret;
387 } 387 }
388 388
@@ -426,22 +426,22 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr) @@ -426,22 +426,22 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
426 426
427 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 427 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
428 s->hw_driver = 1; 428 s->hw_driver = 1;
429 - s->status = dummy; 429 + s->status = dummy;
430 } 430 }
431 431
432 if (s->hw_driver) { 432 if (s->hw_driver) {
433 - register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);  
434 - register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);  
435 - register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);  
436 - register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);  
437 - register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);  
438 - register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);  
439 - register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);  
440 - register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); 433 + register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
  434 + register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
  435 + register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
  436 + register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
  437 + register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
  438 + register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
  439 + register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
  440 + register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
441 } 441 }
442 else { 442 else {
443 - register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);  
444 - register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); 443 + register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
  444 + register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
445 } 445 }
446 return s; 446 return s;
447 } 447 }