Detabify

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162

Detabify
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
blueswir1
1 parent 2e03286b
Showing 6 changed files with 2212 additions and 2212 deletions
target-sparc/cpu.h
target-sparc/helper.c
target-sparc/op.c
target-sparc/op_helper.c
target-sparc/op_mem.h
target-sparc/translate.c
@@ -22,9 +22,9 @@
 #define TARGET_HAS_ICE 1
 #if !defined(TARGET_SPARC64)
-#define ELF_MACHINE	EM_SPARC
+#define ELF_MACHINE     EM_SPARC
 #else
-#define ELF_MACHINE	EM_SPARCV9
+#define ELF_MACHINE     EM_SPARCV9
 #endif
 /*#define EXCP_INTERRUPT 0x100*/
@@ -143,8 +143,8 @@
 #define FSR_FCC0  (1<<10)
 /* MMU */
-#define MMU_E	  (1<<0)
-#define MMU_NF	  (1<<1)
+#define MMU_E     (1<<0)
+#define MMU_NF    (1<<1)
 #define PTE_ENTRYTYPE_MASK 3
 #define PTE_ACCESS_MASK    0x1c
@@ -152,8 +152,8 @@
 #define PTE_PPN_SHIFT      7
 #define PTE_ADDR_MASK      0xffffff00
-#define PG_ACCESSED_BIT	5
-#define PG_MODIFIED_BIT	6
+#define PG_ACCESSED_BIT 5
+#define PG_MODIFIED_BIT 6
 #define PG_CACHE_BIT    7
 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
@@ -221,7 +221,7 @@ typedef struct CPUSPARCState {
     uint64_t tnpc[MAXTL];
     uint64_t tstate[MAXTL];
     uint32_t tt[MAXTL];
-    uint32_t xcc;		/* Extended integer condition codes */
+    uint32_t xcc;               /* Extended integer condition codes */
     uint32_t asi;
     uint32_t pstate;
     uint32_t tl;
@@ -245,12 +245,12 @@ typedef struct CPUSPARCState {
 } CPUSPARCState;
 #if defined(TARGET_SPARC64)
 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
-#define PUT_FSR32(env, val) do { uint32_t _tmp = val;			\
-	env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);	\
+#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
+        env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
     } while (0)
 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
-#define PUT_FSR64(env, val) do { uint64_t _tmp = val;	\
-	env->fsr = _tmp & 0x3fcfc1c3ffULL;		\
+#define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
+        env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
     } while (0)
 #else
 #define GET_FSR32(env) (env->fsr)
@@ -268,31 +268,31 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
-		      (env->psref? PSR_EF : 0) |			\
-		      (env->psrpil << 8) |				\
-		      (env->psrs? PSR_S : 0) |				\
-		      (env->psrps? PSR_PS : 0) |			\
-		      (env->psret? PSR_ET : 0) | env->cwp)
+                      (env->psref? PSR_EF : 0) |                        \
+                      (env->psrpil << 8) |                              \
+                      (env->psrs? PSR_S : 0) |                          \
+                      (env->psrps? PSR_PS : 0) |                        \
+                      (env->psret? PSR_ET : 0) | env->cwp)
 #ifndef NO_CPU_IO_DEFS
 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 #endif
-#define PUT_PSR(env, val) do { int _tmp = val;				\
-	env->psr = _tmp & PSR_ICC;					\
-	env->psref = (_tmp & PSR_EF)? 1 : 0;				\
-	env->psrpil = (_tmp & PSR_PIL) >> 8;				\
-	env->psrs = (_tmp & PSR_S)? 1 : 0;				\
-	env->psrps = (_tmp & PSR_PS)? 1 : 0;				\
-	env->psret = (_tmp & PSR_ET)? 1 : 0;				\
+#define PUT_PSR(env, val) do { int _tmp = val;                          \
+        env->psr = _tmp & PSR_ICC;                                      \
+        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
+        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
+        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
+        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
+        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
         cpu_set_cwp(env, _tmp & PSR_CWP);                               \
     } while (0)
 #ifdef TARGET_SPARC64
 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
-#define PUT_CCR(env, val) do { int _tmp = val;				\
-	env->xcc = (_tmp >> 4) << 20;						\
-	env->psr = (_tmp & 0xf) << 20;					\
+#define PUT_CCR(env, val) do { int _tmp = val;                          \
+        env->xcc = (_tmp >> 4) << 20;                                           \
+        env->psr = (_tmp & 0xf) << 20;                                  \
     } while (0)
 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
 #define PUT_CWP64(env, val) \
@@ -99,8 +99,8 @@ static const int perm_table[2][8] = {
 };
 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
-			  int *access_index, target_ulong address, int rw,
-			  int is_user)
+                          int *access_index, target_ulong address, int rw,
+                          int is_user)
 {
     int access_perms = 0;
     target_phys_addr_t pde_ptr;
@@ -111,7 +111,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
     virt_addr = address & TARGET_PAGE_MASK;
     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
-	*physical = address;
+        *physical = address;
         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return 0;
     }
@@ -128,70 +128,70 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
     switch (pde & PTE_ENTRYTYPE_MASK) {
     default:
     case 0: /* Invalid */
-	return 1 << 2;
+        return 1 << 2;
     case 2: /* L0 PTE, maybe should not happen? */
     case 3: /* Reserved */
         return 4 << 2;
     case 1: /* L0 PDE */
-	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
+        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
         pde = ldl_phys(pde_ptr);
-	switch (pde & PTE_ENTRYTYPE_MASK) {
-	default:
-	case 0: /* Invalid */
-	    return (1 << 8) | (1 << 2);
-	case 3: /* Reserved */
-	    return (1 << 8) | (4 << 2);
-	case 1: /* L1 PDE */
-	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
+        switch (pde & PTE_ENTRYTYPE_MASK) {
+        default:
+        case 0: /* Invalid */
+            return (1 << 8) | (1 << 2);
+        case 3: /* Reserved */
+            return (1 << 8) | (4 << 2);
+        case 1: /* L1 PDE */
+            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
             pde = ldl_phys(pde_ptr);
-	    switch (pde & PTE_ENTRYTYPE_MASK) {
-	    default:
-	    case 0: /* Invalid */
-		return (2 << 8) | (1 << 2);
-	    case 3: /* Reserved */
-		return (2 << 8) | (4 << 2);
-	    case 1: /* L2 PDE */
-		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
+            switch (pde & PTE_ENTRYTYPE_MASK) {
+            default:
+            case 0: /* Invalid */
+                return (2 << 8) | (1 << 2);
+            case 3: /* Reserved */
+                return (2 << 8) | (4 << 2);
+            case 1: /* L2 PDE */
+                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                 pde = ldl_phys(pde_ptr);
-		switch (pde & PTE_ENTRYTYPE_MASK) {
-		default:
-		case 0: /* Invalid */
-		    return (3 << 8) | (1 << 2);
-		case 1: /* PDE, should not happen */
-		case 3: /* Reserved */
-		    return (3 << 8) | (4 << 2);
-		case 2: /* L3 PTE */
-		    virt_addr = address & TARGET_PAGE_MASK;
-		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
-		}
-		break;
-	    case 2: /* L2 PTE */
-		virt_addr = address & ~0x3ffff;
-		page_offset = address & 0x3ffff;
-	    }
-	    break;
-	case 2: /* L1 PTE */
-	    virt_addr = address & ~0xffffff;
-	    page_offset = address & 0xffffff;
-	}
+                switch (pde & PTE_ENTRYTYPE_MASK) {
+                default:
+                case 0: /* Invalid */
+                    return (3 << 8) | (1 << 2);
+                case 1: /* PDE, should not happen */
+                case 3: /* Reserved */
+                    return (3 << 8) | (4 << 2);
+                case 2: /* L3 PTE */
+                    virt_addr = address & TARGET_PAGE_MASK;
+                    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
+                }
+                break;
+            case 2: /* L2 PTE */
+                virt_addr = address & ~0x3ffff;
+                page_offset = address & 0x3ffff;
+            }
+            break;
+        case 2: /* L1 PTE */
+            virt_addr = address & ~0xffffff;
+            page_offset = address & 0xffffff;
+        }
     }
     /* update page modified and dirty bits */
     is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
     if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
-	pde |= PG_ACCESSED_MASK;
-	if (is_dirty)
-	    pde |= PG_MODIFIED_MASK;
+        pde |= PG_ACCESSED_MASK;
+        if (is_dirty)
+            pde |= PG_MODIFIED_MASK;
         stl_phys_notdirty(pde_ptr, pde);
     }
     /* check access */
     access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
     error_code = access_table[*access_index][access_perms];
     if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
-	return error_code;
+        return error_code;
     /* the page can be put in the TLB */
     *prot = perm_table[is_user][access_perms];
@@ -217,18 +217,18 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
     error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
     if (error_code == 0) {
-	vaddr = address & TARGET_PAGE_MASK;
-	paddr &= TARGET_PAGE_MASK;
+        vaddr = address & TARGET_PAGE_MASK;
+        paddr &= TARGET_PAGE_MASK;
 #ifdef DEBUG_MMU
-	printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
+        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
                TARGET_FMT_lx "\n", address, paddr, vaddr);
 #endif
-	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
-	return ret;
+        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+        return ret;
     }
     if (env->mmuregs[3]) /* Fault status register */
-	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
     env->mmuregs[3] |= (access_index << 5) | error_code | 2;
     env->mmuregs[4] = address; /* Fault address register */
@@ -237,10 +237,10 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
         // permissions. If no mapping is available, redirect accesses to
         // neverland. Fake/overridden mappings will be flushed when
         // switching to normal mode.
-	vaddr = address & TARGET_PAGE_MASK;
+        vaddr = address & TARGET_PAGE_MASK;
         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
-	return ret;
+        return ret;
     } else {
         if (rw & 2)
             env->exception_index = TT_TFAULT;
@@ -265,50 +265,50 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
     case 0: /* Invalid */
     case 2: /* PTE, maybe should not happen? */
     case 3: /* Reserved */
-	return 0;
+        return 0;
     case 1: /* L1 PDE */
-	if (mmulev == 3)
-	    return pde;
-	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
+        if (mmulev == 3)
+            return pde;
+        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
         pde = ldl_phys(pde_ptr);
-	switch (pde & PTE_ENTRYTYPE_MASK) {
-	default:
-	case 0: /* Invalid */
-	case 3: /* Reserved */
-	    return 0;
-	case 2: /* L1 PTE */
-	    return pde;
-	case 1: /* L2 PDE */
-	    if (mmulev == 2)
-		return pde;
-	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
+        switch (pde & PTE_ENTRYTYPE_MASK) {
+        default:
+        case 0: /* Invalid */
+        case 3: /* Reserved */
+            return 0;
+        case 2: /* L1 PTE */
+            return pde;
+        case 1: /* L2 PDE */
+            if (mmulev == 2)
+                return pde;
+            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
             pde = ldl_phys(pde_ptr);
-	    switch (pde & PTE_ENTRYTYPE_MASK) {
-	    default:
-	    case 0: /* Invalid */
-	    case 3: /* Reserved */
-		return 0;
-	    case 2: /* L2 PTE */
-		return pde;
-	    case 1: /* L3 PDE */
-		if (mmulev == 1)
-		    return pde;
-		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
+            switch (pde & PTE_ENTRYTYPE_MASK) {
+            default:
+            case 0: /* Invalid */
+            case 3: /* Reserved */
+                return 0;
+            case 2: /* L2 PTE */
+                return pde;
+            case 1: /* L3 PDE */
+                if (mmulev == 1)
+                    return pde;
+                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                 pde = ldl_phys(pde_ptr);
-		switch (pde & PTE_ENTRYTYPE_MASK) {
-		default:
-		case 0: /* Invalid */
-		case 1: /* PDE, should not happen */
-		case 3: /* Reserved */
-		    return 0;
-		case 2: /* L3 PTE */
-		    return pde;
-		}
-	    }
-	}
+                switch (pde & PTE_ENTRYTYPE_MASK) {
+                default:
+                case 0: /* Invalid */
+                case 1: /* PDE, should not happen */
+                case 3: /* Reserved */
+                    return 0;
+                case 2: /* L3 PTE */
+                    return pde;
+                }
+            }
+        }
     }
     return 0;
 }
@@ -327,29 +327,29 @@ void dump_mmu(CPUState *env)
     printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
            (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
     for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
-	pde = mmu_probe(env, va, 2);
-	if (pde) {
-	    pa = cpu_get_phys_page_debug(env, va);
- 	    printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
+        pde = mmu_probe(env, va, 2);
+        if (pde) {
+            pa = cpu_get_phys_page_debug(env, va);
+            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
                    " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
-	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
-		pde = mmu_probe(env, va1, 1);
-		if (pde) {
-		    pa = cpu_get_phys_page_debug(env, va1);
- 		    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
+            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
+                pde = mmu_probe(env, va1, 1);
+                if (pde) {
+                    pa = cpu_get_phys_page_debug(env, va1);
+                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
                            " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
-		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
-			pde = mmu_probe(env, va2, 0);
-			if (pde) {
-			    pa = cpu_get_phys_page_debug(env, va2);
- 			    printf("  VA: " TARGET_FMT_lx ", PA: "
+                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
+                        pde = mmu_probe(env, va2, 0);
+                        if (pde) {
+                            pa = cpu_get_phys_page_debug(env, va2);
+                            printf("  VA: " TARGET_FMT_lx ", PA: "
                                    TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
                                    va2, pa, pde);
-			}
-		    }
-		}
-	    }
-	}
+                        }
+                    }
+                }
+            }
+        }
     }
     printf("MMU dump ends\n");
 }
@@ -360,57 +360,57 @@ void dump_mmu(CPUState *env)
  * UltraSparc IIi I/DMMUs
  */
 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
-			  int *access_index, target_ulong address, int rw,
-			  int is_user)
+                          int *access_index, target_ulong address, int rw,
+                          int is_user)
 {
     target_ulong mask;
     unsigned int i;
     if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
-	*physical = address;
-	*prot = PAGE_READ | PAGE_WRITE;
+        *physical = address;
+        *prot = PAGE_READ | PAGE_WRITE;
         return 0;
     }
     for (i = 0; i < 64; i++) {
-	switch ((env->dtlb_tte[i] >> 61) & 3) {
-	default:
-	case 0x0: // 8k
-	    mask = 0xffffffffffffe000ULL;
-	    break;
-	case 0x1: // 64k
-	    mask = 0xffffffffffff0000ULL;
-	    break;
-	case 0x2: // 512k
-	    mask = 0xfffffffffff80000ULL;
-	    break;
-	case 0x3: // 4M
-	    mask = 0xffffffffffc00000ULL;
-	    break;
-	}
-	// ctx match, vaddr match?
-	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
-	    (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
-	    // valid, access ok?
-	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
-		((env->dtlb_tte[i] & 0x4) && is_user) ||
-		(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
-		if (env->dmmuregs[3]) /* Fault status register */
-		    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
-		env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
-		env->dmmuregs[4] = address; /* Fault address register */
-		env->exception_index = TT_DFAULT;
+        switch ((env->dtlb_tte[i] >> 61) & 3) {
+        default:
+        case 0x0: // 8k
+            mask = 0xffffffffffffe000ULL;
+            break;
+        case 0x1: // 64k
+            mask = 0xffffffffffff0000ULL;
+            break;
+        case 0x2: // 512k
+            mask = 0xfffffffffff80000ULL;
+            break;
+        case 0x3: // 4M
+            mask = 0xffffffffffc00000ULL;
+            break;
+        }
+        // ctx match, vaddr match?
+        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
+            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
+            // valid, access ok?
+            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+                ((env->dtlb_tte[i] & 0x4) && is_user) ||
+                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
+                if (env->dmmuregs[3]) /* Fault status register */
+                    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
+                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
+                env->dmmuregs[4] = address; /* Fault address register */
+                env->exception_index = TT_DFAULT;
 #ifdef DEBUG_MMU
-		printf("DFAULT at 0x%" PRIx64 "\n", address);
+                printf("DFAULT at 0x%" PRIx64 "\n", address);
 #endif
-		return 1;
-	    }
-	    *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
-	    *prot = PAGE_READ;
-	    if (env->dtlb_tte[i] & 0x2)
-		*prot |= PAGE_WRITE;
-	    return 0;
-	}
+                return 1;
+            }
+            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+            *prot = PAGE_READ;
+            if (env->dtlb_tte[i] & 0x2)
+                *prot |= PAGE_WRITE;
+            return 0;
+        }
     }
 #ifdef DEBUG_MMU
     printf("DMISS at 0x%" PRIx64 "\n", address);
@@ -420,53 +420,53 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
 }
 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
-			  int *access_index, target_ulong address, int rw,
-			  int is_user)
+                          int *access_index, target_ulong address, int rw,
+                          int is_user)
 {
     target_ulong mask;
     unsigned int i;
     if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
-	*physical = address;
-	*prot = PAGE_EXEC;
+        *physical = address;
+        *prot = PAGE_EXEC;
         return 0;
     }
     for (i = 0; i < 64; i++) {
-	switch ((env->itlb_tte[i] >> 61) & 3) {
-	default:
-	case 0x0: // 8k
-	    mask = 0xffffffffffffe000ULL;
-	    break;
-	case 0x1: // 64k
-	    mask = 0xffffffffffff0000ULL;
-	    break;
-	case 0x2: // 512k
-	    mask = 0xfffffffffff80000ULL;
-	    break;
-	case 0x3: // 4M
-	    mask = 0xffffffffffc00000ULL;
-		break;
-	}
-	// ctx match, vaddr match?
-	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
-	    (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
-	    // valid, access ok?
-	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
-		((env->itlb_tte[i] & 0x4) && is_user)) {
-		if (env->immuregs[3]) /* Fault status register */
-		    env->immuregs[3] = 2; /* overflow (not read before another fault) */
-		env->immuregs[3] |= (is_user << 3) | 1;
-		env->exception_index = TT_TFAULT;
+        switch ((env->itlb_tte[i] >> 61) & 3) {
+        default:
+        case 0x0: // 8k
+            mask = 0xffffffffffffe000ULL;
+            break;
+        case 0x1: // 64k
+            mask = 0xffffffffffff0000ULL;
+            break;
+        case 0x2: // 512k
+            mask = 0xfffffffffff80000ULL;
+            break;
+        case 0x3: // 4M
+            mask = 0xffffffffffc00000ULL;
+                break;
+        }
+        // ctx match, vaddr match?
+        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
+            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
+            // valid, access ok?
+            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+                ((env->itlb_tte[i] & 0x4) && is_user)) {
+                if (env->immuregs[3]) /* Fault status register */
+                    env->immuregs[3] = 2; /* overflow (not read before another fault) */
+                env->immuregs[3] |= (is_user << 3) | 1;
+                env->exception_index = TT_TFAULT;
 #ifdef DEBUG_MMU
-		printf("TFAULT at 0x%" PRIx64 "\n", address);
+                printf("TFAULT at 0x%" PRIx64 "\n", address);
 #endif
-		return 1;
-	    }
-	    *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
-	    *prot = PAGE_EXEC;
-	    return 0;
-	}
+                return 1;
+            }
+            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+            *prot = PAGE_EXEC;
+            return 0;
+        }
     }
 #ifdef DEBUG_MMU
     printf("TMISS at 0x%" PRIx64 "\n", address);
@@ -476,13 +476,13 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
 }
 int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
-			  int *access_index, target_ulong address, int rw,
-			  int is_user)
+                          int *access_index, target_ulong address, int rw,
+                          int is_user)
 {
     if (rw == 2)
-	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
+        return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
     else
-	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
+        return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
 }
 /* Perform address translation */
@@ -495,13 +495,13 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
     error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
     if (error_code == 0) {
-	virt_addr = address & TARGET_PAGE_MASK;
-	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
+        virt_addr = address & TARGET_PAGE_MASK;
+        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
 #ifdef DEBUG_MMU
-	printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
+        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
 #endif
-	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
-	return ret;
+        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+        return ret;
     }
     // XXX
     return 1;
@@ -515,67 +515,67 @@ void dump_mmu(CPUState *env)
     printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
     if ((env->lsu & DMMU_E) == 0) {
-	printf("DMMU disabled\n");
+        printf("DMMU disabled\n");
     } else {
-	printf("DMMU dump:\n");
-	for (i = 0; i < 64; i++) {
-	    switch ((env->dtlb_tte[i] >> 61) & 3) {
-	    default:
-	    case 0x0:
-		mask = "  8k";
-		break;
-	    case 0x1:
-		mask = " 64k";
-		break;
-	    case 0x2:
-		mask = "512k";
-		break;
-	    case 0x3:
-		mask = "  4M";
-		break;
-	    }
-	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
-		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
-		       env->dtlb_tag[i] & ~0x1fffULL,
-		       env->dtlb_tte[i] & 0x1ffffffe000ULL,
-		       mask,
-		       env->dtlb_tte[i] & 0x4? "priv": "user",
-		       env->dtlb_tte[i] & 0x2? "RW": "RO",
-		       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
-		       env->dtlb_tag[i] & 0x1fffULL);
-	    }
-	}
+        printf("DMMU dump:\n");
+        for (i = 0; i < 64; i++) {
+            switch ((env->dtlb_tte[i] >> 61) & 3) {
+            default:
+            case 0x0:
+                mask = "  8k";
+                break;
+            case 0x1:
+                mask = " 64k";
+                break;
+            case 0x2:
+                mask = "512k";
+                break;
+            case 0x3:
+                mask = "  4M";
+                break;
+            }
+            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
+                       env->dtlb_tag[i] & ~0x1fffULL,
+                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
+                       mask,
+                       env->dtlb_tte[i] & 0x4? "priv": "user",
+                       env->dtlb_tte[i] & 0x2? "RW": "RO",
+                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
+                       env->dtlb_tag[i] & 0x1fffULL);
+            }
+        }
     }
     if ((env->lsu & IMMU_E) == 0) {
-	printf("IMMU disabled\n");
+        printf("IMMU disabled\n");
     } else {
-	printf("IMMU dump:\n");
-	for (i = 0; i < 64; i++) {
-	    switch ((env->itlb_tte[i] >> 61) & 3) {
-	    default:
-	    case 0x0:
-		mask = "  8k";
-		break;
-	    case 0x1:
-		mask = " 64k";
-		break;
-	    case 0x2:
-		mask = "512k";
-		break;
-	    case 0x3:
-		mask = "  4M";
-		break;
-	    }
-	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
-		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
-		       env->itlb_tag[i] & ~0x1fffULL,
-		       env->itlb_tte[i] & 0x1ffffffe000ULL,
-		       mask,
-		       env->itlb_tte[i] & 0x4? "priv": "user",
-		       env->itlb_tte[i] & 0x40? "locked": "unlocked",
-		       env->itlb_tag[i] & 0x1fffULL);
-	    }
-	}
+        printf("IMMU dump:\n");
+        for (i = 0; i < 64; i++) {
+            switch ((env->itlb_tte[i] >> 61) & 3) {
+            default:
+            case 0x0:
+                mask = "  8k";
+                break;
+            case 0x1:
+                mask = " 64k";
+                break;
+            case 0x2:
+                mask = "512k";
+                break;
+            case 0x3:
+                mask = "  4M";
+                break;
+            }
+            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
+                       env->itlb_tag[i] & ~0x1fffULL,
+                       env->itlb_tte[i] & 0x1ffffffe000ULL,
+                       mask,
+                       env->itlb_tte[i] & 0x4? "priv": "user",
+                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
+                       env->itlb_tag[i] & 0x1fffULL);
+            }
+        }
     }
 }
 #endif /* DEBUG_MMU */
@@ -376,33 +376,33 @@ void OPPROTO op_add_T1_T0_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (T0 < src1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T0 < src1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -448,26 +448,26 @@ void OPPROTO op_addx_T1_T0_cc(void)
     }
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -481,37 +481,37 @@ void OPPROTO op_tadd_T1_T0_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     if ((src1 & 0x03) || (T1 & 0x03))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (T0 < src1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T0 < src1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     if ((src1 & 0x03) || (T1 & 0x03))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -528,7 +528,7 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
 #ifdef TARGET_SPARC64
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
         raise_exception(TT_TOVF);
 #else
     if ((src1 & 0x03) || (T1 & 0x03))
@@ -538,26 +538,26 @@ void OPPROTO op_tadd_T1_T0_ccTV(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (T0 < src1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T0 < src1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
 #endif
     FORCE_RET();
 }
@@ -576,33 +576,33 @@ void OPPROTO op_sub_T1_T0_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (src1 < T1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (src1 < T1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -648,26 +648,26 @@ void OPPROTO op_subx_T1_T0_cc(void)
     }
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -681,37 +681,37 @@ void OPPROTO op_tsub_T1_T0_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
-	env->psr |= PSR_OVF;
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+        env->psr |= PSR_OVF;
     if ((src1 & 0x03) || (T1 & 0x03))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (src1 < T1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
-	env->xcc |= PSR_OVF;
+        env->xcc |= PSR_OVF;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (src1 < T1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     if ((src1 & 0x03) || (T1 & 0x03))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -728,7 +728,7 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
 #ifdef TARGET_SPARC64
     if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
-	 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
         raise_exception(TT_TOVF);
 #else
     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
@@ -738,26 +738,26 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
     if (src1 < T1)
-	env->xcc |= PSR_CARRY;
+        env->xcc |= PSR_CARRY;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (src1 < T1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
 #endif
     FORCE_RET();
 }
@@ -833,13 +833,13 @@ void OPPROTO op_mulscc_T1_T0(void)
     T0 += T1;
     env->psr = 0;
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T0 < src1)
-	env->psr |= PSR_CARRY;
+        env->psr |= PSR_CARRY;
     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     env->y = (b2 << 31) | (env->y >> 1);
     FORCE_RET();
 }
@@ -858,11 +858,11 @@ void OPPROTO op_udiv_T1_T0(void)
     x0 = x0 / x1;
     if (x0 > 0xffffffff) {
-	T0 = 0xffffffff;
-	T1 = 1;
+        T0 = 0xffffffff;
+        T1 = 1;
     } else {
-	T0 = x0;
-	T1 = 0;
+        T0 = x0;
+        T1 = 0;
     }
     FORCE_RET();
 }
@@ -881,11 +881,11 @@ void OPPROTO op_sdiv_T1_T0(void)
     x0 = x0 / x1;
     if ((int32_t) x0 != x0) {
-	T0 = x0 < 0? 0x80000000: 0x7fffffff;
-	T1 = 1;
+        T0 = x0 < 0? 0x80000000: 0x7fffffff;
+        T1 = 1;
     } else {
-	T0 = x0;
-	T1 = 0;
+        T0 = x0;
+        T1 = 0;
     }
     FORCE_RET();
 }
@@ -895,24 +895,24 @@ void OPPROTO op_div_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T1)
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     if (T1)
-	env->psr |= PSR_OVF;
+        env->psr |= PSR_OVF;
 #endif
     FORCE_RET();
 }
@@ -939,9 +939,9 @@ void OPPROTO op_sdivx_T1_T0(void)
         raise_exception(TT_DIV_ZERO);
     }
     if (T0 == INT64_MIN && T1 == -1)
-	T0 = INT64_MIN;
+        T0 = INT64_MIN;
     else
-	T0 /= (target_long) T1;
+        T0 /= (target_long) T1;
     FORCE_RET();
 }
 #endif
@@ -951,20 +951,20 @@ void OPPROTO op_logic_T0_cc(void)
     env->psr = 0;
 #ifdef TARGET_SPARC64
     if (!(T0 & 0xffffffff))
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
     env->xcc = 0;
     if (!T0)
-	env->xcc |= PSR_ZERO;
+        env->xcc |= PSR_ZERO;
     if ((int64_t) T0 < 0)
-	env->xcc |= PSR_NEG;
+        env->xcc |= PSR_NEG;
 #else
     if (!T0)
-	env->psr |= PSR_ZERO;
+        env->psr |= PSR_ZERO;
     if ((int32_t) T0 < 0)
-	env->psr |= PSR_NEG;
+        env->psr |= PSR_NEG;
 #endif
     FORCE_RET();
 }
@@ -1200,17 +1200,17 @@ void OPPROTO op_save(void)
     cwp = (env->cwp - 1) & (NWINDOWS - 1);
     if (env->cansave == 0) {
         raise_exception(TT_SPILL | (env->otherwin != 0 ?
-				    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
-				    ((env->wstate & 0x7) << 2)));
+                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+                                    ((env->wstate & 0x7) << 2)));
     } else {
-	if (env->cleanwin - env->canrestore == 0) {
-	    // XXX Clean windows without trap
-	    raise_exception(TT_CLRWIN);
-	} else {
-	    env->cansave--;
-	    env->canrestore++;
-	    set_cwp(cwp);
-	}
+        if (env->cleanwin - env->canrestore == 0) {
+            // XXX Clean windows without trap
+            raise_exception(TT_CLRWIN);
+        } else {
+            env->cansave--;
+            env->canrestore++;
+            set_cwp(cwp);
+        }
     }
     FORCE_RET();
 }
@@ -1221,12 +1221,12 @@ void OPPROTO op_restore(void)
     cwp = (env->cwp + 1) & (NWINDOWS - 1);
     if (env->canrestore == 0) {
         raise_exception(TT_FILL | (env->otherwin != 0 ?
-				   (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
-				   ((env->wstate & 0x7) << 2)));
+                                   (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+                                   ((env->wstate & 0x7) << 2)));
     } else {
-	env->cansave++;
-	env->canrestore--;
-	set_cwp(cwp);
+        env->cansave++;
+        env->canrestore--;
+        set_cwp(cwp);
     }
     FORCE_RET();
 }
@@ -1576,15 +1576,15 @@ void OPPROTO op_clear_ieee_excp_and_FTT(void)
 #define F_BINOP(name)                                           \
     F_OP(name, s)                                               \
     {                                                           \
-	set_float_exception_flags(0, &env->fp_status);		\
+        set_float_exception_flags(0, &env->fp_status);          \
         FT0 = float32_ ## name (FT0, FT1, &env->fp_status);     \
-	check_ieee_exceptions();				\
+        check_ieee_exceptions();                                \
     }                                                           \
     F_OP(name, d)                                               \
     {                                                           \
-	set_float_exception_flags(0, &env->fp_status);		\
+        set_float_exception_flags(0, &env->fp_status);          \
         DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
-	check_ieee_exceptions();				\
+        check_ieee_exceptions();                                \
     }
 F_BINOP(add);
@@ -1784,27 +1784,27 @@ void OPPROTO op_fdtox(void)
 void OPPROTO op_fmovs_cc(void)
 {
     if (T2)
-	FT0 = FT1;
+        FT0 = FT1;
 }
 void OPPROTO op_fmovd_cc(void)
 {
     if (T2)
-	DT0 = DT1;
+        DT0 = DT1;
 }
 void OPPROTO op_mov_cc(void)
 {
     if (T2)
-	T0 = T1;
+        T0 = T1;
 }
 void OPPROTO op_flushw(void)
 {
     if (env->cansave != NWINDOWS - 2) {
         raise_exception(TT_SPILL | (env->otherwin != 0 ?
-				    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
-				    ((env->wstate & 0x7) << 2)));
+                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+                                    ((env->wstate & 0x7) << 2)));
     }
 }
@@ -1812,9 +1812,9 @@ void OPPROTO op_saved(void)
 {
     env->cansave++;
     if (env->otherwin == 0)
-	env->canrestore--;
+        env->canrestore--;
     else
-	env->otherwin--;
+        env->otherwin--;
     FORCE_RET();
 }
@@ -1822,11 +1822,11 @@ void OPPROTO op_restored(void)
 {
     env->canrestore++;
     if (env->cleanwin < NWINDOWS - 1)
-	env->cleanwin++;
+        env->cleanwin++;
     if (env->otherwin == 0)
-	env->cansave--;
+        env->cansave--;
     else
-	env->otherwin--;
+        env->otherwin--;
     FORCE_RET();
 }
@@ -16,29 +16,29 @@ void check_ieee_exceptions()
      T0 = get_float_exception_flags(&env->fp_status);
      if (T0)
      {
-	/* Copy IEEE 754 flags into FSR */
-	if (T0 & float_flag_invalid)
-	    env->fsr |= FSR_NVC;
-	if (T0 & float_flag_overflow)
-	    env->fsr |= FSR_OFC;
-	if (T0 & float_flag_underflow)
-	    env->fsr |= FSR_UFC;
-	if (T0 & float_flag_divbyzero)
-	    env->fsr |= FSR_DZC;
-	if (T0 & float_flag_inexact)
-	    env->fsr |= FSR_NXC;
-
-	if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
-	{
-	    /* Unmasked exception, generate a trap */
-	    env->fsr |= FSR_FTT_IEEE_EXCP;
-	    raise_exception(TT_FP_EXCP);
-	}
-	else
-	{
-	    /* Accumulate exceptions */
-	    env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
-	}
+        /* Copy IEEE 754 flags into FSR */
+        if (T0 & float_flag_invalid)
+            env->fsr |= FSR_NVC;
+        if (T0 & float_flag_overflow)
+            env->fsr |= FSR_OFC;
+        if (T0 & float_flag_underflow)
+            env->fsr |= FSR_UFC;
+        if (T0 & float_flag_divbyzero)
+            env->fsr |= FSR_DZC;
+        if (T0 & float_flag_inexact)
+            env->fsr |= FSR_NXC;
+
+        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
+        {
+            /* Unmasked exception, generate a trap */
+            env->fsr |= FSR_FTT_IEEE_EXCP;
+            raise_exception(TT_FP_EXCP);
+        }
+        else
+        {
+            /* Accumulate exceptions */
+            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
+        }
      }
 }
@@ -155,33 +155,33 @@ void helper_ld_asi(int asi, int size, int sign)
     case 2: /* SuperSparc MXCC registers */
         break;
     case 3: /* MMU probe */
-	{
-	    int mmulev;
-
-	    mmulev = (T0 >> 8) & 15;
-	    if (mmulev > 4)
-		ret = 0;
-	    else {
-		ret = mmu_probe(env, T0, mmulev);
-		//bswap32s(&ret);
-	    }
+        {
+            int mmulev;
+
+            mmulev = (T0 >> 8) & 15;
+            if (mmulev > 4)
+                ret = 0;
+            else {
+                ret = mmu_probe(env, T0, mmulev);
+                //bswap32s(&ret);
+            }
 #ifdef DEBUG_MMU
-	    printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
+            printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
 #endif
-	}
-	break;
+        }
+        break;
     case 4: /* read MMU regs */
-	{
-	    int reg = (T0 >> 8) & 0xf;
+        {
+            int reg = (T0 >> 8) & 0xf;
-	    ret = env->mmuregs[reg];
-	    if (reg == 3) /* Fault status cleared on read */
-		env->mmuregs[reg] = 0;
+            ret = env->mmuregs[reg];
+            if (reg == 3) /* Fault status cleared on read */
+                env->mmuregs[reg] = 0;
 #ifdef DEBUG_MMU
-	    printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
+            printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
 #endif
-	}
-	break;
+        }
+        break;
     case 9: /* Supervisor code access */
         switch(size) {
         case 1:
@@ -218,11 +218,11 @@ void helper_ld_asi(int asi, int size, int sign)
             ret = ldl_phys(T0 & ~3);
             break;
         case 8:
-	    ret = ldl_phys(T0 & ~3);
-	    T0 = ldl_phys((T0 + 4) & ~3);
-	    break;
+            ret = ldl_phys(T0 & ~3);
+            T0 = ldl_phys((T0 + 4) & ~3);
+            break;
         }
-	break;
+        break;
     case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
     case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
         switch(size) {
@@ -244,14 +244,14 @@ void helper_ld_asi(int asi, int size, int sign)
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
             T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
-	    break;
+            break;
         }
-	break;
+        break;
     case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
     default:
         do_unassigned_access(T0, 0, 0, 1);
-	ret = 0;
-	break;
+        ret = 0;
+        break;
     }
     T1 = ret;
 }
@@ -262,48 +262,48 @@ void helper_st_asi(int asi, int size, int sign)
     case 2: /* SuperSparc MXCC registers */
         break;
     case 3: /* MMU flush */
-	{
-	    int mmulev;
+        {
+            int mmulev;
-	    mmulev = (T0 >> 8) & 15;
+            mmulev = (T0 >> 8) & 15;
 #ifdef DEBUG_MMU
-	    printf("mmu flush level %d\n", mmulev);
+            printf("mmu flush level %d\n", mmulev);
 #endif
-	    switch (mmulev) {
-	    case 0: // flush page
-		tlb_flush_page(env, T0 & 0xfffff000);
-		break;
-	    case 1: // flush segment (256k)
-	    case 2: // flush region (16M)
-	    case 3: // flush context (4G)
-	    case 4: // flush entire
-		tlb_flush(env, 1);
-		break;
-	    default:
-		break;
-	    }
+            switch (mmulev) {
+            case 0: // flush page
+                tlb_flush_page(env, T0 & 0xfffff000);
+                break;
+            case 1: // flush segment (256k)
+            case 2: // flush region (16M)
+            case 3: // flush context (4G)
+            case 4: // flush entire
+                tlb_flush(env, 1);
+                break;
+            default:
+                break;
+            }
 #ifdef DEBUG_MMU
-	    dump_mmu(env);
+            dump_mmu(env);
 #endif
-	    return;
-	}
+            return;
+        }
     case 4: /* write MMU regs */
-	{
-	    int reg = (T0 >> 8) & 0xf;
-	    uint32_t oldreg;
+        {
+            int reg = (T0 >> 8) & 0xf;
+            uint32_t oldreg;
-	    oldreg = env->mmuregs[reg];
+            oldreg = env->mmuregs[reg];
             switch(reg) {
             case 0:
-		env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
-		env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
-		// Mappings generated during no-fault mode or MMU
-		// disabled mode are invalid in normal mode
+                env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
+                env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
+                // Mappings generated during no-fault mode or MMU
+                // disabled mode are invalid in normal mode
                 if (oldreg != env->mmuregs[reg])
                     tlb_flush(env, 1);
                 break;
             case 2:
-		env->mmuregs[reg] = T1;
+                env->mmuregs[reg] = T1;
                 if (oldreg != env->mmuregs[reg]) {
                     /* we flush when the MMU context changes because
                        QEMU has no MMU context support */
@@ -314,17 +314,17 @@ void helper_st_asi(int asi, int size, int sign)
             case 4:
                 break;
             default:
-		env->mmuregs[reg] = T1;
+                env->mmuregs[reg] = T1;
                 break;
             }
 #ifdef DEBUG_MMU
             if (oldreg != env->mmuregs[reg]) {
                 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
             }
-	    dump_mmu(env);
+            dump_mmu(env);
 #endif
-	    return;
-	}
+            return;
+        }
     case 0xc: /* I-cache tag */
     case 0xd: /* I-cache data */
     case 0xe: /* D-cache tag */
@@ -336,10 +336,10 @@ void helper_st_asi(int asi, int size, int sign)
     case 0x14: /* I/D-cache flush user */
         break;
     case 0x17: /* Block copy, sta access */
-	{
-	    // value (T1) = src
-	    // address (T0) = dst
-	    // copy 32 bytes
+        {
+            // value (T1) = src
+            // address (T0) = dst
+            // copy 32 bytes
             unsigned int i;
             uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
@@ -347,13 +347,13 @@ void helper_st_asi(int asi, int size, int sign)
                 temp = ldl_kernel(src);
                 stl_kernel(dst, temp);
             }
-	}
-	return;
+        }
+        return;
     case 0x1f: /* Block fill, stda access */
-	{
-	    // value (T1, T2)
-	    // address (T0) = dst
-	    // fill 32 bytes
+        {
+            // value (T1, T2)
+            // address (T0) = dst
+            // fill 32 bytes
             unsigned int i;
             uint32_t dst = T0 & 7;
             uint64_t val;
@@ -362,10 +362,10 @@ void helper_st_asi(int asi, int size, int sign)
             for (i = 0; i < 32; i += 8, dst += 8)
                 stq_kernel(dst, val);
-	}
-	return;
+        }
+        return;
     case 0x20: /* MMU passthrough */
-	{
+        {
             switch(size) {
             case 1:
                 stb_phys(T0, T1);
@@ -382,11 +382,11 @@ void helper_st_asi(int asi, int size, int sign)
                 stl_phys((T0 + 4) & ~3, T2);
                 break;
             }
-	}
-	return;
+        }
+        return;
     case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
     case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
-	{
+        {
             switch(size) {
             case 1:
                 stb_phys((target_phys_addr_t)T0
@@ -408,8 +408,8 @@ void helper_st_asi(int asi, int size, int sign)
                            | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
                 break;
             }
-	}
-	return;
+        }
+        return;
     case 0x31: /* Ross RT620 I-cache flush */
     case 0x36: /* I-cache flash clear */
     case 0x37: /* D-cache flash clear */
@@ -418,7 +418,7 @@ void helper_st_asi(int asi, int size, int sign)
     case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
     default:
         do_unassigned_access(T0, 1, 0, 1);
-	return;
+        return;
     }
 }
@@ -429,12 +429,12 @@ void helper_ld_asi(int asi, int size, int sign)
     uint64_t ret = 0;
     if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
-	raise_exception(TT_PRIV_ACT);
+        raise_exception(TT_PRIV_ACT);
     switch (asi) {
     case 0x14: // Bypass
     case 0x15: // Bypass, non-cacheable
-	{
+        {
             switch(size) {
             case 1:
                 ret = ldub_phys(T0);
@@ -450,8 +450,8 @@ void helper_ld_asi(int asi, int size, int sign)
                 ret = ldq_phys(T0 & ~7);
                 break;
             }
-	    break;
-	}
+            break;
+        }
     case 0x04: // Nucleus
     case 0x0c: // Nucleus Little Endian (LE)
     case 0x10: // As if user primary
@@ -469,58 +469,58 @@ void helper_ld_asi(int asi, int size, int sign)
     case 0x89: // Secondary LE
     case 0x8a: // Primary no-fault LE
     case 0x8b: // Secondary no-fault LE
-	// XXX
-	break;
+        // XXX
+        break;
     case 0x45: // LSU
-	ret = env->lsu;
-	break;
+        ret = env->lsu;
+        break;
     case 0x50: // I-MMU regs
-	{
-	    int reg = (T0 >> 3) & 0xf;
+        {
+            int reg = (T0 >> 3) & 0xf;
-	    ret = env->immuregs[reg];
-	    break;
-	}
+            ret = env->immuregs[reg];
+            break;
+        }
     case 0x51: // I-MMU 8k TSB pointer
     case 0x52: // I-MMU 64k TSB pointer
     case 0x55: // I-MMU data access
-	// XXX
-	break;
+        // XXX
+        break;
     case 0x56: // I-MMU tag read
-	{
-	    unsigned int i;
-
-	    for (i = 0; i < 64; i++) {
-		// Valid, ctx match, vaddr match
-		if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
-		    env->itlb_tag[i] == T0) {
-		    ret = env->itlb_tag[i];
-		    break;
-		}
-	    }
-	    break;
-	}
+        {
+            unsigned int i;
+
+            for (i = 0; i < 64; i++) {
+                // Valid, ctx match, vaddr match
+                if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
+                    env->itlb_tag[i] == T0) {
+                    ret = env->itlb_tag[i];
+                    break;
+                }
+            }
+            break;
+        }
     case 0x58: // D-MMU regs
-	{
-	    int reg = (T0 >> 3) & 0xf;
+        {
+            int reg = (T0 >> 3) & 0xf;
-	    ret = env->dmmuregs[reg];
-	    break;
-	}
+            ret = env->dmmuregs[reg];
+            break;
+        }
     case 0x5e: // D-MMU tag read
-	{
-	    unsigned int i;
-
-	    for (i = 0; i < 64; i++) {
-		// Valid, ctx match, vaddr match
-		if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
-		    env->dtlb_tag[i] == T0) {
-		    ret = env->dtlb_tag[i];
-		    break;
-		}
-	    }
-	    break;
-	}
+        {
+            unsigned int i;
+
+            for (i = 0; i < 64; i++) {
+                // Valid, ctx match, vaddr match
+                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
+                    env->dtlb_tag[i] == T0) {
+                    ret = env->dtlb_tag[i];
+                    break;
+                }
+            }
+            break;
+        }
     case 0x59: // D-MMU 8k TSB pointer
     case 0x5a: // D-MMU 64k TSB pointer
     case 0x5b: // D-MMU data pointer
@@ -528,8 +528,8 @@ void helper_ld_asi(int asi, int size, int sign)
     case 0x48: // Interrupt dispatch, RO
     case 0x49: // Interrupt data receive
     case 0x7f: // Incoming interrupt vector, RO
-	// XXX
-	break;
+        // XXX
+        break;
     case 0x54: // I-MMU data in, WO
     case 0x57: // I-MMU demap, WO
     case 0x5c: // D-MMU data in, WO
@@ -537,8 +537,8 @@ void helper_ld_asi(int asi, int size, int sign)
     case 0x77: // Interrupt vector, WO
     default:
         do_unassigned_access(T0, 0, 0, 1);
-	ret = 0;
-	break;
+        ret = 0;
+        break;
     }
     T1 = ret;
 }
@@ -546,12 +546,12 @@ void helper_ld_asi(int asi, int size, int sign)
 void helper_st_asi(int asi, int size, int sign)
 {
     if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
-	raise_exception(TT_PRIV_ACT);
+        raise_exception(TT_PRIV_ACT);
     switch(asi) {
     case 0x14: // Bypass
     case 0x15: // Bypass, non-cacheable
-	{
+        {
             switch(size) {
             case 1:
                 stb_phys(T0, T1);
@@ -567,8 +567,8 @@ void helper_st_asi(int asi, int size, int sign)
                 stq_phys(T0 & ~7, T1);
                 break;
             }
-	}
-	return;
+        }
+        return;
     case 0x04: // Nucleus
     case 0x0c: // Nucleus Little Endian (LE)
     case 0x10: // As if user primary
@@ -582,31 +582,31 @@ void helper_st_asi(int asi, int size, int sign)
     case 0x4a: // UPA config
     case 0x88: // Primary LE
     case 0x89: // Secondary LE
-	// XXX
-	return;
+        // XXX
+        return;
     case 0x45: // LSU
-	{
-	    uint64_t oldreg;
-
-	    oldreg = env->lsu;
-	    env->lsu = T1 & (DMMU_E | IMMU_E);
-	    // Mappings generated during D/I MMU disabled mode are
-	    // invalid in normal mode
-	    if (oldreg != env->lsu) {
+        {
+            uint64_t oldreg;
+
+            oldreg = env->lsu;
+            env->lsu = T1 & (DMMU_E | IMMU_E);
+            // Mappings generated during D/I MMU disabled mode are
+            // invalid in normal mode
+            if (oldreg != env->lsu) {
 #ifdef DEBUG_MMU
                 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
-		dump_mmu(env);
+                dump_mmu(env);
 #endif
-		tlb_flush(env, 1);
-	    }
-	    return;
-	}
+                tlb_flush(env, 1);
+            }
+            return;
+        }
     case 0x50: // I-MMU regs
-	{
-	    int reg = (T0 >> 3) & 0xf;
-	    uint64_t oldreg;
+        {
+            int reg = (T0 >> 3) & 0xf;
+            uint64_t oldreg;
-	    oldreg = env->immuregs[reg];
+            oldreg = env->immuregs[reg];
             switch(reg) {
             case 0: // RO
             case 4:
@@ -617,73 +617,73 @@ void helper_st_asi(int asi, int size, int sign)
             case 8:
                 return;
             case 3: // SFSR
-		if ((T1 & 1) == 0)
-		    T1 = 0; // Clear SFSR
+                if ((T1 & 1) == 0)
+                    T1 = 0; // Clear SFSR
                 break;
             case 5: // TSB access
             case 6: // Tag access
             default:
                 break;
             }
-	    env->immuregs[reg] = T1;
+            env->immuregs[reg] = T1;
 #ifdef DEBUG_MMU
             if (oldreg != env->immuregs[reg]) {
                 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
             }
-	    dump_mmu(env);
+            dump_mmu(env);
 #endif
-	    return;
-	}
+            return;
+        }
     case 0x54: // I-MMU data in
-	{
-	    unsigned int i;
-
-	    // Try finding an invalid entry
-	    for (i = 0; i < 64; i++) {
-		if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
-		    env->itlb_tag[i] = env->immuregs[6];
-		    env->itlb_tte[i] = T1;
-		    return;
-		}
-	    }
-	    // Try finding an unlocked entry
-	    for (i = 0; i < 64; i++) {
-		if ((env->itlb_tte[i] & 0x40) == 0) {
-		    env->itlb_tag[i] = env->immuregs[6];
-		    env->itlb_tte[i] = T1;
-		    return;
-		}
-	    }
-	    // error state?
-	    return;
-	}
+        {
+            unsigned int i;
+
+            // Try finding an invalid entry
+            for (i = 0; i < 64; i++) {
+                if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
+                    env->itlb_tag[i] = env->immuregs[6];
+                    env->itlb_tte[i] = T1;
+                    return;
+                }
+            }
+            // Try finding an unlocked entry
+            for (i = 0; i < 64; i++) {
+                if ((env->itlb_tte[i] & 0x40) == 0) {
+                    env->itlb_tag[i] = env->immuregs[6];
+                    env->itlb_tte[i] = T1;
+                    return;
+                }
+            }
+            // error state?
+            return;
+        }
     case 0x55: // I-MMU data access
-	{
-	    unsigned int i = (T0 >> 3) & 0x3f;
+        {
+            unsigned int i = (T0 >> 3) & 0x3f;
-	    env->itlb_tag[i] = env->immuregs[6];
-	    env->itlb_tte[i] = T1;
-	    return;
-	}
+            env->itlb_tag[i] = env->immuregs[6];
+            env->itlb_tte[i] = T1;
+            return;
+        }
     case 0x57: // I-MMU demap
-	// XXX
-	return;
+        // XXX
+        return;
     case 0x58: // D-MMU regs
-	{
-	    int reg = (T0 >> 3) & 0xf;
-	    uint64_t oldreg;
+        {
+            int reg = (T0 >> 3) & 0xf;
+            uint64_t oldreg;
-	    oldreg = env->dmmuregs[reg];
+            oldreg = env->dmmuregs[reg];
             switch(reg) {
             case 0: // RO
             case 4:
                 return;
             case 3: // SFSR
-		if ((T1 & 1) == 0) {
-		    T1 = 0; // Clear SFSR, Fault address
-		    env->dmmuregs[4] = 0;
-		}
-		env->dmmuregs[reg] = T1;
+                if ((T1 & 1) == 0) {
+                    T1 = 0; // Clear SFSR, Fault address
+                    env->dmmuregs[4] = 0;
+                }
+                env->dmmuregs[reg] = T1;
                 break;
             case 1: // Primary context
             case 2: // Secondary context
@@ -694,50 +694,50 @@ void helper_st_asi(int asi, int size, int sign)
             default:
                 break;
             }
-	    env->dmmuregs[reg] = T1;
+            env->dmmuregs[reg] = T1;
 #ifdef DEBUG_MMU
             if (oldreg != env->dmmuregs[reg]) {
                 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
             }
-	    dump_mmu(env);
+            dump_mmu(env);
 #endif
-	    return;
-	}
+            return;
+        }
     case 0x5c: // D-MMU data in
-	{
-	    unsigned int i;
-
-	    // Try finding an invalid entry
-	    for (i = 0; i < 64; i++) {
-		if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
-		    env->dtlb_tag[i] = env->dmmuregs[6];
-		    env->dtlb_tte[i] = T1;
-		    return;
-		}
-	    }
-	    // Try finding an unlocked entry
-	    for (i = 0; i < 64; i++) {
-		if ((env->dtlb_tte[i] & 0x40) == 0) {
-		    env->dtlb_tag[i] = env->dmmuregs[6];
-		    env->dtlb_tte[i] = T1;
-		    return;
-		}
-	    }
-	    // error state?
-	    return;
-	}
+        {
+            unsigned int i;
+
+            // Try finding an invalid entry
+            for (i = 0; i < 64; i++) {
+                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
+                    env->dtlb_tag[i] = env->dmmuregs[6];
+                    env->dtlb_tte[i] = T1;
+                    return;
+                }
+            }
+            // Try finding an unlocked entry
+            for (i = 0; i < 64; i++) {
+                if ((env->dtlb_tte[i] & 0x40) == 0) {
+                    env->dtlb_tag[i] = env->dmmuregs[6];
+                    env->dtlb_tte[i] = T1;
+                    return;
+                }
+            }
+            // error state?
+            return;
+        }
     case 0x5d: // D-MMU data access
-	{
-	    unsigned int i = (T0 >> 3) & 0x3f;
+        {
+            unsigned int i = (T0 >> 3) & 0x3f;
-	    env->dtlb_tag[i] = env->dmmuregs[6];
-	    env->dtlb_tte[i] = T1;
-	    return;
-	}
+            env->dtlb_tag[i] = env->dmmuregs[6];
+            env->dtlb_tte[i] = T1;
+            return;
+        }
     case 0x5f: // D-MMU demap
     case 0x49: // Interrupt data receive
-	// XXX
-	return;
+        // XXX
+        return;
     case 0x51: // I-MMU 8k TSB pointer, RO
     case 0x52: // I-MMU 64k TSB pointer, RO
     case 0x56: // I-MMU tag read, RO
@@ -753,7 +753,7 @@ void helper_st_asi(int asi, int size, int sign)
     case 0x8b: // Secondary no-fault LE, RO
     default:
         do_unassigned_access(T0, 1, 0, 1);
-	return;
+        return;
     }
 }
 #endif
@@ -783,17 +783,17 @@ void helper_ldfsr(void)
     switch (env->fsr & FSR_RD_MASK) {
     case FSR_RD_NEAREST:
         rnd_mode = float_round_nearest_even;
-	break;
+        break;
     default:
     case FSR_RD_ZERO:
         rnd_mode = float_round_to_zero;
-	break;
+        break;
     case FSR_RD_POS:
         rnd_mode = float_round_up;
-	break;
+        break;
     case FSR_RD_NEG:
         rnd_mode = float_round_down;
-	break;
+        break;
     }
     set_float_rounding_mode(rnd_mode, &env->fp_status);
 }
@@ -835,13 +835,13 @@ static inline uint64_t *get_gregset(uint64_t pstate)
     switch (pstate) {
     default:
     case 0:
-	return env->bgregs;
+        return env->bgregs;
     case PS_AG:
-	return env->agregs;
+        return env->agregs;
     case PS_MG:
-	return env->mgregs;
+        return env->mgregs;
     case PS_IG:
-	return env->igregs;
+        return env->igregs;
     }
 }
@@ -853,11 +853,11 @@ static inline void change_pstate(uint64_t new_pstate)
     pstate_regs = env->pstate & 0xc01;
     new_pstate_regs = new_pstate & 0xc01;
     if (new_pstate_regs != pstate_regs) {
-	// Switch global register bank
-	src = get_gregset(new_pstate_regs);
-	dst = get_gregset(pstate_regs);
-	memcpy32(dst, env->gregs);
-	memcpy32(env->gregs, src);
+        // Switch global register bank
+        src = get_gregset(new_pstate_regs);
+        dst = get_gregset(pstate_regs);
+        memcpy32(dst, env->gregs);
+        memcpy32(env->gregs, src);
     }
     env->pstate = new_pstate;
 }
@@ -927,36 +927,36 @@ void do_interrupt(int intno)
 {
 #ifdef DEBUG_PCALL
     if (loglevel & CPU_LOG_INT) {
-	static int count;
-	fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
+        static int count;
+        fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
                 count, intno,
                 env->pc,
                 env->npc, env->regwptr[6]);
-	cpu_dump_state(env, logfile, fprintf, 0);
+        cpu_dump_state(env, logfile, fprintf, 0);
 #if 0
-	{
-	    int i;
-	    uint8_t *ptr;
-
-	    fprintf(logfile, "       code=");
-	    ptr = (uint8_t *)env->pc;
-	    for(i = 0; i < 16; i++) {
-		fprintf(logfile, " %02x", ldub(ptr + i));
-	    }
-	    fprintf(logfile, "\n");
-	}
+        {
+            int i;
+            uint8_t *ptr;
+
+            fprintf(logfile, "       code=");
+            ptr = (uint8_t *)env->pc;
+            for(i = 0; i < 16; i++) {
+                fprintf(logfile, " %02x", ldub(ptr + i));
+            }
+            fprintf(logfile, "\n");
+        }
 #endif
-	count++;
+        count++;
     }
 #endif
 #if !defined(CONFIG_USER_ONLY)
     if (env->tl == MAXTL) {
         cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
-	return;
+        return;
     }
 #endif
     env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
-	((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
+        ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
     env->tpc[env->tl] = env->pc;
     env->tnpc[env->tl] = env->npc;
     env->tt[env->tl] = intno;
@@ -971,11 +971,11 @@ void do_interrupt(int intno)
     env->tbr &= ~0x7fffULL;
     env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
     if (env->tl < MAXTL - 1) {
-	env->tl++;
+        env->tl++;
     } else {
-	env->pstate |= PS_RED;
-	if (env->tl != MAXTL)
-	    env->tl++;
+        env->pstate |= PS_RED;
+        if (env->tl != MAXTL)
+            env->tl++;
     }
     env->pc = env->tbr;
     env->npc = env->pc + 4;
@@ -988,32 +988,32 @@ void do_interrupt(int intno)
 #ifdef DEBUG_PCALL
     if (loglevel & CPU_LOG_INT) {
-	static int count;
-	fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
+        static int count;
+        fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
                 count, intno,
                 env->pc,
                 env->npc, env->regwptr[6]);
-	cpu_dump_state(env, logfile, fprintf, 0);
+        cpu_dump_state(env, logfile, fprintf, 0);
 #if 0
-	{
-	    int i;
-	    uint8_t *ptr;
-
-	    fprintf(logfile, "       code=");
-	    ptr = (uint8_t *)env->pc;
-	    for(i = 0; i < 16; i++) {
-		fprintf(logfile, " %02x", ldub(ptr + i));
-	    }
-	    fprintf(logfile, "\n");
-	}
+        {
+            int i;
+            uint8_t *ptr;
+
+            fprintf(logfile, "       code=");
+            ptr = (uint8_t *)env->pc;
+            for(i = 0; i < 16; i++) {
+                fprintf(logfile, " %02x", ldub(ptr + i));
+            }
+            fprintf(logfile, "\n");
+        }
 #endif
-	count++;
+        count++;
     }
 #endif
 #if !defined(CONFIG_USER_ONLY)
     if (env->psret == 0) {
         cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
-	return;
+        return;
     }
 #endif
     env->psret = 0;
@@ -1106,7 +1106,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
     saved_env = env;
     env = cpu_single_env;
     if (env->mmuregs[3]) /* Fault status register */
-	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
     if (is_asi)
         env->mmuregs[3] |= 1 << 16;
     if (env->psrs)
@@ -2,13 +2,13 @@
 #define SPARC_LD_OP(name, qp)                                                 \
 void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void)                           \
 {                                                                             \
-    T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0);				\
+    T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0);                         \
 }
-#define SPARC_LD_OP_S(name, qp)						\
-    void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void)			\
-    {									\
-	T1 = (target_long)glue(qp, MEMSUFFIX)(T0);			\
+#define SPARC_LD_OP_S(name, qp)                                         \
+    void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void)                 \
+    {                                                                   \
+        T1 = (target_long)glue(qp, MEMSUFFIX)(T0);                      \
     }
 #define SPARC_ST_OP(name, op)                                                 \
@@ -85,7 +85,7 @@ void OPPROTO glue(op_cas, MEMSUFFIX)(void)
     tmp = glue(ldl, MEMSUFFIX)(T0);
     T2 &=  0xffffffffULL;
     if (tmp == (T1 & 0xffffffffULL)) {
-	glue(stl, MEMSUFFIX)(T0, T2);
+        glue(stl, MEMSUFFIX)(T0, T2);
     }
     T2 = tmp;
 }
@@ -98,7 +98,7 @@ void OPPROTO glue(op_casx, MEMSUFFIX)(void)
     tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32;
     tmp |= glue(ldl, MEMSUFFIX)(T0);
     if (tmp == T1) {
-	glue(stq, MEMSUFFIX)(T0, T2);
+        glue(stq, MEMSUFFIX)(T0, T2);
     }
     T2 = tmp;
 }
@@ -45,8 +45,8 @@
                          according to jump_pc[T2] */
 typedef struct DisasContext {
-    target_ulong pc;	/* current Program Counter: integer or DYNAMIC_PC */
-    target_ulong npc;	/* next PC: integer or DYNAMIC_PC or JUMP_PC */
+    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
+    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
     int is_br;
     int mem_idx;
@@ -359,57 +359,57 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 #define supervisor(dc) 0
 #define hypervisor(dc) 0
 #define gen_op_ldst(name)        gen_op_##name##_raw()
-#define OP_LD_TABLE(width)						\
+#define OP_LD_TABLE(width)                                              \
     static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
-    {									\
-	int asi, offset;						\
-									\
-	if (IS_IMM) {							\
-	    offset = GET_FIELD(insn, 25, 31);				\
-	    if (is_ld)							\
-		gen_op_ld_asi_reg(offset, size, sign);			\
-	    else							\
-		gen_op_st_asi_reg(offset, size, sign);			\
-	    return;							\
-	}								\
-	asi = GET_FIELD(insn, 19, 26);					\
-	switch (asi) {							\
-	case 0x80: /* Primary address space */				\
-	    gen_op_##width##_raw();					\
-	    break;							\
-	case 0x82: /* Primary address space, non-faulting load */       \
-	    gen_op_##width##_raw();					\
-	    break;							\
-	default:							\
-            break;							\
-	}								\
+    {                                                                   \
+        int asi, offset;                                                \
+                                                                        \
+        if (IS_IMM) {                                                   \
+            offset = GET_FIELD(insn, 25, 31);                           \
+            if (is_ld)                                                  \
+                gen_op_ld_asi_reg(offset, size, sign);                  \
+            else                                                        \
+                gen_op_st_asi_reg(offset, size, sign);                  \
+            return;                                                     \
+        }                                                               \
+        asi = GET_FIELD(insn, 19, 26);                                  \
+        switch (asi) {                                                  \
+        case 0x80: /* Primary address space */                          \
+            gen_op_##width##_raw();                                     \
+            break;                                                      \
+        case 0x82: /* Primary address space, non-faulting load */       \
+            gen_op_##width##_raw();                                     \
+            break;                                                      \
+        default:                                                        \
+            break;                                                      \
+        }                                                               \
     }
 #else
 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
-#define OP_LD_TABLE(width)						\
+#define OP_LD_TABLE(width)                                              \
     static GenOpFunc * const gen_op_##width[] = {                       \
-	&gen_op_##width##_user,						\
-	&gen_op_##width##_kernel,					\
-    };									\
-									\
+        &gen_op_##width##_user,                                         \
+        &gen_op_##width##_kernel,                                       \
+    };                                                                  \
+                                                                        \
     static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
-    {									\
-	int asi, offset;						\
-									\
-	if (IS_IMM) {							\
-	    offset = GET_FIELD(insn, 25, 31);				\
-	    if (is_ld)							\
-		gen_op_ld_asi_reg(offset, size, sign);			\
-	    else							\
-		gen_op_st_asi_reg(offset, size, sign);			\
-	    return;							\
-	}								\
-	asi = GET_FIELD(insn, 19, 26);					\
-	if (is_ld)							\
-	    gen_op_ld_asi(asi, size, sign);				\
-	else								\
-	    gen_op_st_asi(asi, size, sign);				\
+    {                                                                   \
+        int asi, offset;                                                \
+                                                                        \
+        if (IS_IMM) {                                                   \
+            offset = GET_FIELD(insn, 25, 31);                           \
+            if (is_ld)                                                  \
+                gen_op_ld_asi_reg(offset, size, sign);                  \
+            else                                                        \
+                gen_op_st_asi_reg(offset, size, sign);                  \
+            return;                                                     \
+        }                                                               \
+        asi = GET_FIELD(insn, 19, 26);                                  \
+        if (is_ld)                                                      \
+            gen_op_ld_asi(asi, size, sign);                             \
+        else                                                            \
+            gen_op_st_asi(asi, size, sign);                             \
     }
 #define supervisor(dc) (dc->mem_idx == 1)
@@ -422,7 +422,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 #define supervisor(dc) 0
 #else
 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
-#define OP_LD_TABLE(width)						      \
+#define OP_LD_TABLE(width)                                                    \
 static GenOpFunc * const gen_op_##width[] = {                                 \
     &gen_op_##width##_user,                                                   \
     &gen_op_##width##_kernel,                                                 \
@@ -434,23 +434,23 @@ static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
                                                                               \
     asi = GET_FIELD(insn, 19, 26);                                            \
     switch (asi) {                                                            \
-	case 10: /* User data access */                                       \
-	    gen_op_##width##_user();                                          \
-	    break;                                                            \
-	case 11: /* Supervisor data access */                                 \
-	    gen_op_##width##_kernel();                                        \
-	    break;                                                            \
-        case 0x20 ... 0x2f: /* MMU passthrough */			      \
-	    if (is_ld)                                                        \
-		gen_op_ld_asi(asi, size, sign);				      \
-	    else                                                              \
-		gen_op_st_asi(asi, size, sign);				      \
-	    break;                                                            \
-	default:                                                              \
-	    if (is_ld)                                                        \
-		gen_op_ld_asi(asi, size, sign);			              \
-	    else                                                              \
-		gen_op_st_asi(asi, size, sign);				      \
+        case 10: /* User data access */                                       \
+            gen_op_##width##_user();                                          \
+            break;                                                            \
+        case 11: /* Supervisor data access */                                 \
+            gen_op_##width##_kernel();                                        \
+            break;                                                            \
+        case 0x20 ... 0x2f: /* MMU passthrough */                             \
+            if (is_ld)                                                        \
+                gen_op_ld_asi(asi, size, sign);                               \
+            else                                                              \
+                gen_op_st_asi(asi, size, sign);                               \
+            break;                                                            \
+        default:                                                              \
+            if (is_ld)                                                        \
+                gen_op_ld_asi(asi, size, sign);                               \
+            else                                                              \
+                gen_op_st_asi(asi, size, sign);                               \
             break;                                                            \
     }                                                                         \
 }
@@ -518,9 +518,9 @@ static inline void gen_movl_simm_T0(int32_t val)
 static inline void gen_movl_reg_TN(int reg, int t)
 {
     if (reg)
-	gen_op_movl_reg_TN[t][reg] ();
+        gen_op_movl_reg_TN[t][reg] ();
     else
-	gen_movl_imm_TN(t, 0);
+        gen_movl_imm_TN(t, 0);
 }
 static inline void gen_movl_reg_T0(int reg)
@@ -541,7 +541,7 @@ static inline void gen_movl_reg_T2(int reg)
 static inline void gen_movl_TN_reg(int reg, int t)
 {
     if (reg)
-	gen_op_movl_TN_reg[t][reg] ();
+        gen_op_movl_TN_reg[t][reg] ();
 }
 static inline void gen_movl_T0_reg(int reg)
@@ -699,118 +699,118 @@ static inline void gen_mov_pc_npc(DisasContext * dc)
 static GenOpFunc * const gen_cond[2][16] = {
     {
-	gen_op_eval_bn,
-	gen_op_eval_be,
-	gen_op_eval_ble,
-	gen_op_eval_bl,
-	gen_op_eval_bleu,
-	gen_op_eval_bcs,
-	gen_op_eval_bneg,
-	gen_op_eval_bvs,
-	gen_op_eval_ba,
-	gen_op_eval_bne,
-	gen_op_eval_bg,
-	gen_op_eval_bge,
-	gen_op_eval_bgu,
-	gen_op_eval_bcc,
-	gen_op_eval_bpos,
-	gen_op_eval_bvc,
+        gen_op_eval_bn,
+        gen_op_eval_be,
+        gen_op_eval_ble,
+        gen_op_eval_bl,
+        gen_op_eval_bleu,
+        gen_op_eval_bcs,
+        gen_op_eval_bneg,
+        gen_op_eval_bvs,
+        gen_op_eval_ba,
+        gen_op_eval_bne,
+        gen_op_eval_bg,
+        gen_op_eval_bge,
+        gen_op_eval_bgu,
+        gen_op_eval_bcc,
+        gen_op_eval_bpos,
+        gen_op_eval_bvc,
     },
     {
 #ifdef TARGET_SPARC64
-	gen_op_eval_bn,
-	gen_op_eval_xbe,
-	gen_op_eval_xble,
-	gen_op_eval_xbl,
-	gen_op_eval_xbleu,
-	gen_op_eval_xbcs,
-	gen_op_eval_xbneg,
-	gen_op_eval_xbvs,
-	gen_op_eval_ba,
-	gen_op_eval_xbne,
-	gen_op_eval_xbg,
-	gen_op_eval_xbge,
-	gen_op_eval_xbgu,
-	gen_op_eval_xbcc,
-	gen_op_eval_xbpos,
-	gen_op_eval_xbvc,
+        gen_op_eval_bn,
+        gen_op_eval_xbe,
+        gen_op_eval_xble,
+        gen_op_eval_xbl,
+        gen_op_eval_xbleu,
+        gen_op_eval_xbcs,
+        gen_op_eval_xbneg,
+        gen_op_eval_xbvs,
+        gen_op_eval_ba,
+        gen_op_eval_xbne,
+        gen_op_eval_xbg,
+        gen_op_eval_xbge,
+        gen_op_eval_xbgu,
+        gen_op_eval_xbcc,
+        gen_op_eval_xbpos,
+        gen_op_eval_xbvc,
 #endif
     },
 };
 static GenOpFunc * const gen_fcond[4][16] = {
     {
-	gen_op_eval_bn,
-	gen_op_eval_fbne,
-	gen_op_eval_fblg,
-	gen_op_eval_fbul,
-	gen_op_eval_fbl,
-	gen_op_eval_fbug,
-	gen_op_eval_fbg,
-	gen_op_eval_fbu,
-	gen_op_eval_ba,
-	gen_op_eval_fbe,
-	gen_op_eval_fbue,
-	gen_op_eval_fbge,
-	gen_op_eval_fbuge,
-	gen_op_eval_fble,
-	gen_op_eval_fbule,
-	gen_op_eval_fbo,
+        gen_op_eval_bn,
+        gen_op_eval_fbne,
+        gen_op_eval_fblg,
+        gen_op_eval_fbul,
+        gen_op_eval_fbl,
+        gen_op_eval_fbug,
+        gen_op_eval_fbg,
+        gen_op_eval_fbu,
+        gen_op_eval_ba,
+        gen_op_eval_fbe,
+        gen_op_eval_fbue,
+        gen_op_eval_fbge,
+        gen_op_eval_fbuge,
+        gen_op_eval_fble,
+        gen_op_eval_fbule,
+        gen_op_eval_fbo,
     },
 #ifdef TARGET_SPARC64
     {
-	gen_op_eval_bn,
-	gen_op_eval_fbne_fcc1,
-	gen_op_eval_fblg_fcc1,
-	gen_op_eval_fbul_fcc1,
-	gen_op_eval_fbl_fcc1,
-	gen_op_eval_fbug_fcc1,
-	gen_op_eval_fbg_fcc1,
-	gen_op_eval_fbu_fcc1,
-	gen_op_eval_ba,
-	gen_op_eval_fbe_fcc1,
-	gen_op_eval_fbue_fcc1,
-	gen_op_eval_fbge_fcc1,
-	gen_op_eval_fbuge_fcc1,
-	gen_op_eval_fble_fcc1,
-	gen_op_eval_fbule_fcc1,
-	gen_op_eval_fbo_fcc1,
+        gen_op_eval_bn,
+        gen_op_eval_fbne_fcc1,
+        gen_op_eval_fblg_fcc1,
+        gen_op_eval_fbul_fcc1,
+        gen_op_eval_fbl_fcc1,
+        gen_op_eval_fbug_fcc1,
+        gen_op_eval_fbg_fcc1,
+        gen_op_eval_fbu_fcc1,
+        gen_op_eval_ba,
+        gen_op_eval_fbe_fcc1,
+        gen_op_eval_fbue_fcc1,
+        gen_op_eval_fbge_fcc1,
+        gen_op_eval_fbuge_fcc1,
+        gen_op_eval_fble_fcc1,
+        gen_op_eval_fbule_fcc1,
+        gen_op_eval_fbo_fcc1,
     },
     {
-	gen_op_eval_bn,
-	gen_op_eval_fbne_fcc2,
-	gen_op_eval_fblg_fcc2,
-	gen_op_eval_fbul_fcc2,
-	gen_op_eval_fbl_fcc2,
-	gen_op_eval_fbug_fcc2,
-	gen_op_eval_fbg_fcc2,
-	gen_op_eval_fbu_fcc2,
-	gen_op_eval_ba,
-	gen_op_eval_fbe_fcc2,
-	gen_op_eval_fbue_fcc2,
-	gen_op_eval_fbge_fcc2,
-	gen_op_eval_fbuge_fcc2,
-	gen_op_eval_fble_fcc2,
-	gen_op_eval_fbule_fcc2,
-	gen_op_eval_fbo_fcc2,
+        gen_op_eval_bn,
+        gen_op_eval_fbne_fcc2,
+        gen_op_eval_fblg_fcc2,
+        gen_op_eval_fbul_fcc2,
+        gen_op_eval_fbl_fcc2,
+        gen_op_eval_fbug_fcc2,
+        gen_op_eval_fbg_fcc2,
+        gen_op_eval_fbu_fcc2,
+        gen_op_eval_ba,
+        gen_op_eval_fbe_fcc2,
+        gen_op_eval_fbue_fcc2,
+        gen_op_eval_fbge_fcc2,
+        gen_op_eval_fbuge_fcc2,
+        gen_op_eval_fble_fcc2,
+        gen_op_eval_fbule_fcc2,
+        gen_op_eval_fbo_fcc2,
     },
     {
-	gen_op_eval_bn,
-	gen_op_eval_fbne_fcc3,
-	gen_op_eval_fblg_fcc3,
-	gen_op_eval_fbul_fcc3,
-	gen_op_eval_fbl_fcc3,
-	gen_op_eval_fbug_fcc3,
-	gen_op_eval_fbg_fcc3,
-	gen_op_eval_fbu_fcc3,
-	gen_op_eval_ba,
-	gen_op_eval_fbe_fcc3,
-	gen_op_eval_fbue_fcc3,
-	gen_op_eval_fbge_fcc3,
-	gen_op_eval_fbuge_fcc3,
-	gen_op_eval_fble_fcc3,
-	gen_op_eval_fbule_fcc3,
-	gen_op_eval_fbo_fcc3,
+        gen_op_eval_bn,
+        gen_op_eval_fbne_fcc3,
+        gen_op_eval_fblg_fcc3,
+        gen_op_eval_fbul_fcc3,
+        gen_op_eval_fbl_fcc3,
+        gen_op_eval_fbug_fcc3,
+        gen_op_eval_fbg_fcc3,
+        gen_op_eval_fbu_fcc3,
+        gen_op_eval_ba,
+        gen_op_eval_fbe_fcc3,
+        gen_op_eval_fbue_fcc3,
+        gen_op_eval_fbge_fcc3,
+        gen_op_eval_fbuge_fcc3,
+        gen_op_eval_fble_fcc3,
+        gen_op_eval_fbule_fcc3,
+        gen_op_eval_fbo_fcc3,
     },
 #else
     {}, {}, {},
@@ -820,27 +820,27 @@ static GenOpFunc * const gen_fcond[4][16] = {
 #ifdef TARGET_SPARC64
 static void gen_cond_reg(int cond)
 {
-	switch (cond) {
-	case 0x1:
-	    gen_op_eval_brz();
-	    break;
-	case 0x2:
-	    gen_op_eval_brlez();
-	    break;
-	case 0x3:
-	    gen_op_eval_brlz();
-	    break;
-	case 0x5:
-	    gen_op_eval_brnz();
-	    break;
-	case 0x6:
-	    gen_op_eval_brgz();
-	    break;
+        switch (cond) {
+        case 0x1:
+            gen_op_eval_brz();
+            break;
+        case 0x2:
+            gen_op_eval_brlez();
+            break;
+        case 0x3:
+            gen_op_eval_brlz();
+            break;
+        case 0x5:
+            gen_op_eval_brnz();
+            break;
+        case 0x6:
+            gen_op_eval_brgz();
+            break;
         default:
-	case 0x7:
-	    gen_op_eval_brgez();
-	    break;
-	}
+        case 0x7:
+            gen_op_eval_brgez();
+            break;
+        }
 }
 #endif
@@ -851,35 +851,35 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
     target_ulong target = dc->pc + offset;
     if (cond == 0x0) {
-	/* unconditional not taken */
-	if (a) {
-	    dc->pc = dc->npc + 4;
-	    dc->npc = dc->pc + 4;
-	} else {
-	    dc->pc = dc->npc;
-	    dc->npc = dc->pc + 4;
-	}
+        /* unconditional not taken */
+        if (a) {
+            dc->pc = dc->npc + 4;
+            dc->npc = dc->pc + 4;
+        } else {
+            dc->pc = dc->npc;
+            dc->npc = dc->pc + 4;
+        }
     } else if (cond == 0x8) {
-	/* unconditional taken */
-	if (a) {
-	    dc->pc = target;
-	    dc->npc = dc->pc + 4;
-	} else {
-	    dc->pc = dc->npc;
-	    dc->npc = target;
-	}
+        /* unconditional taken */
+        if (a) {
+            dc->pc = target;
+            dc->npc = dc->pc + 4;
+        } else {
+            dc->pc = dc->npc;
+            dc->npc = target;
+        }
     } else {
         flush_T2(dc);
         gen_cond[cc][cond]();
-	if (a) {
-	    gen_branch_a(dc, target, dc->npc);
+        if (a) {
+            gen_branch_a(dc, target, dc->npc);
             dc->is_br = 1;
-	} else {
+        } else {
             dc->pc = dc->npc;
             dc->jump_pc[0] = target;
             dc->jump_pc[1] = dc->npc + 4;
             dc->npc = JUMP_PC;
-	}
+        }
     }
 }
@@ -890,35 +890,35 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
     target_ulong target = dc->pc + offset;
     if (cond == 0x0) {
-	/* unconditional not taken */
-	if (a) {
-	    dc->pc = dc->npc + 4;
-	    dc->npc = dc->pc + 4;
-	} else {
-	    dc->pc = dc->npc;
-	    dc->npc = dc->pc + 4;
-	}
+        /* unconditional not taken */
+        if (a) {
+            dc->pc = dc->npc + 4;
+            dc->npc = dc->pc + 4;
+        } else {
+            dc->pc = dc->npc;
+            dc->npc = dc->pc + 4;
+        }
     } else if (cond == 0x8) {
-	/* unconditional taken */
-	if (a) {
-	    dc->pc = target;
-	    dc->npc = dc->pc + 4;
-	} else {
-	    dc->pc = dc->npc;
-	    dc->npc = target;
-	}
+        /* unconditional taken */
+        if (a) {
+            dc->pc = target;
+            dc->npc = dc->pc + 4;
+        } else {
+            dc->pc = dc->npc;
+            dc->npc = target;
+        }
     } else {
         flush_T2(dc);
         gen_fcond[cc][cond]();
-	if (a) {
-	    gen_branch_a(dc, target, dc->npc);
+        if (a) {
+            gen_branch_a(dc, target, dc->npc);
             dc->is_br = 1;
-	} else {
+        } else {
             dc->pc = dc->npc;
             dc->jump_pc[0] = target;
             dc->jump_pc[1] = dc->npc + 4;
             dc->npc = JUMP_PC;
-	}
+        }
     }
 }
@@ -932,13 +932,13 @@ static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
     flush_T2(dc);
     gen_cond_reg(cond);
     if (a) {
-	gen_branch_a(dc, target, dc->npc);
-	dc->is_br = 1;
+        gen_branch_a(dc, target, dc->npc);
+        dc->is_br = 1;
     } else {
-	dc->pc = dc->npc;
-	dc->jump_pc[0] = target;
-	dc->jump_pc[1] = dc->npc + 4;
-	dc->npc = JUMP_PC;
+        dc->pc = dc->npc;
+        dc->jump_pc[0] = target;
+        dc->jump_pc[1] = dc->npc + 4;
+        dc->npc = JUMP_PC;
     }
 }
@@ -995,139 +995,139 @@ static void disas_sparc_insn(DisasContext * dc)
     rd = GET_FIELD(insn, 2, 6);
     switch (opc) {
-    case 0:			/* branches/sethi */
-	{
-	    unsigned int xop = GET_FIELD(insn, 7, 9);
-	    int32_t target;
-	    switch (xop) {
+    case 0:                     /* branches/sethi */
+        {
+            unsigned int xop = GET_FIELD(insn, 7, 9);
+            int32_t target;
+            switch (xop) {
 #ifdef TARGET_SPARC64
-	    case 0x1:		/* V9 BPcc */
-		{
-		    int cc;
-
-		    target = GET_FIELD_SP(insn, 0, 18);
-		    target = sign_extend(target, 18);
-		    target <<= 2;
-		    cc = GET_FIELD_SP(insn, 20, 21);
-		    if (cc == 0)
-			do_branch(dc, target, insn, 0);
-		    else if (cc == 2)
-			do_branch(dc, target, insn, 1);
-		    else
-			goto illegal_insn;
-		    goto jmp_insn;
-		}
-	    case 0x3:		/* V9 BPr */
-		{
-		    target = GET_FIELD_SP(insn, 0, 13) |
+            case 0x1:           /* V9 BPcc */
+                {
+                    int cc;
+
+                    target = GET_FIELD_SP(insn, 0, 18);
+                    target = sign_extend(target, 18);
+                    target <<= 2;
+                    cc = GET_FIELD_SP(insn, 20, 21);
+                    if (cc == 0)
+                        do_branch(dc, target, insn, 0);
+                    else if (cc == 2)
+                        do_branch(dc, target, insn, 1);
+                    else
+                        goto illegal_insn;
+                    goto jmp_insn;
+                }
+            case 0x3:           /* V9 BPr */
+                {
+                    target = GET_FIELD_SP(insn, 0, 13) |
                         (GET_FIELD_SP(insn, 20, 21) << 14);
-		    target = sign_extend(target, 16);
-		    target <<= 2;
-		    rs1 = GET_FIELD(insn, 13, 17);
-		    gen_movl_reg_T0(rs1);
-		    do_branch_reg(dc, target, insn);
-		    goto jmp_insn;
-		}
-	    case 0x5:		/* V9 FBPcc */
-		{
-		    int cc = GET_FIELD_SP(insn, 20, 21);
+                    target = sign_extend(target, 16);
+                    target <<= 2;
+                    rs1 = GET_FIELD(insn, 13, 17);
+                    gen_movl_reg_T0(rs1);
+                    do_branch_reg(dc, target, insn);
+                    goto jmp_insn;
+                }
+            case 0x5:           /* V9 FBPcc */
+                {
+                    int cc = GET_FIELD_SP(insn, 20, 21);
                     if (gen_trap_ifnofpu(dc))
                         goto jmp_insn;
-		    target = GET_FIELD_SP(insn, 0, 18);
-		    target = sign_extend(target, 19);
-		    target <<= 2;
-		    do_fbranch(dc, target, insn, cc);
-		    goto jmp_insn;
-		}
+                    target = GET_FIELD_SP(insn, 0, 18);
+                    target = sign_extend(target, 19);
+                    target <<= 2;
+                    do_fbranch(dc, target, insn, cc);
+                    goto jmp_insn;
+                }
 #else
-	    case 0x7:		/* CBN+x */
-		{
-		    goto ncp_insn;
-		}
-#endif
-	    case 0x2:		/* BN+x */
-		{
-		    target = GET_FIELD(insn, 10, 31);
-		    target = sign_extend(target, 22);
-		    target <<= 2;
-		    do_branch(dc, target, insn, 0);
-		    goto jmp_insn;
-		}
-	    case 0x6:		/* FBN+x */
-		{
+            case 0x7:           /* CBN+x */
+                {
+                    goto ncp_insn;
+                }
+#endif
+            case 0x2:           /* BN+x */
+                {
+                    target = GET_FIELD(insn, 10, 31);
+                    target = sign_extend(target, 22);
+                    target <<= 2;
+                    do_branch(dc, target, insn, 0);
+                    goto jmp_insn;
+                }
+            case 0x6:           /* FBN+x */
+                {
                     if (gen_trap_ifnofpu(dc))
                         goto jmp_insn;
-		    target = GET_FIELD(insn, 10, 31);
-		    target = sign_extend(target, 22);
-		    target <<= 2;
-		    do_fbranch(dc, target, insn, 0);
-		    goto jmp_insn;
-		}
-	    case 0x4:		/* SETHI */
+                    target = GET_FIELD(insn, 10, 31);
+                    target = sign_extend(target, 22);
+                    target <<= 2;
+                    do_fbranch(dc, target, insn, 0);
+                    goto jmp_insn;
+                }
+            case 0x4:           /* SETHI */
 #define OPTIM
 #if defined(OPTIM)
-		if (rd) { // nop
+                if (rd) { // nop
 #endif
-		    uint32_t value = GET_FIELD(insn, 10, 31);
-		    gen_movl_imm_T0(value << 10);
-		    gen_movl_T0_reg(rd);
+                    uint32_t value = GET_FIELD(insn, 10, 31);
+                    gen_movl_imm_T0(value << 10);
+                    gen_movl_T0_reg(rd);
 #if defined(OPTIM)
-		}
+                }
 #endif
-		break;
-	    case 0x0:		/* UNIMPL */
-	    default:
+                break;
+            case 0x0:           /* UNIMPL */
+            default:
                 goto illegal_insn;
-	    }
-	    break;
-	}
-	break;
+            }
+            break;
+        }
+        break;
     case 1:
-	/*CALL*/ {
-	    target_long target = GET_FIELDs(insn, 2, 31) << 2;
+        /*CALL*/ {
+            target_long target = GET_FIELDs(insn, 2, 31) << 2;
 #ifdef TARGET_SPARC64
-	    if (dc->pc == (uint32_t)dc->pc) {
-		gen_op_movl_T0_im(dc->pc);
-	    } else {
-		gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
-	    }
+            if (dc->pc == (uint32_t)dc->pc) {
+                gen_op_movl_T0_im(dc->pc);
+            } else {
+                gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+            }
 #else
-	    gen_op_movl_T0_im(dc->pc);
+            gen_op_movl_T0_im(dc->pc);
 #endif
-	    gen_movl_T0_reg(15);
-	    target += dc->pc;
+            gen_movl_T0_reg(15);
+            target += dc->pc;
             gen_mov_pc_npc(dc);
-	    dc->npc = target;
-	}
-	goto jmp_insn;
-    case 2:			/* FPU & Logical Operations */
-	{
-	    unsigned int xop = GET_FIELD(insn, 7, 12);
-	    if (xop == 0x3a) {	/* generate trap */
+            dc->npc = target;
+        }
+        goto jmp_insn;
+    case 2:                     /* FPU & Logical Operations */
+        {
+            unsigned int xop = GET_FIELD(insn, 7, 12);
+            if (xop == 0x3a) {  /* generate trap */
                 int cond;
                 rs1 = GET_FIELD(insn, 13, 17);
                 gen_movl_reg_T0(rs1);
-		if (IS_IMM) {
-		    rs2 = GET_FIELD(insn, 25, 31);
+                if (IS_IMM) {
+                    rs2 = GET_FIELD(insn, 25, 31);
 #if defined(OPTIM)
-		    if (rs2 != 0) {
+                    if (rs2 != 0) {
 #endif
-			gen_movl_simm_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_simm_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
                 } else {
                     rs2 = GET_FIELD(insn, 27, 31);
 #if defined(OPTIM)
-		    if (rs2 != 0) {
+                    if (rs2 != 0) {
 #endif
-			gen_movl_reg_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_reg_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
                 }
                 cond = GET_FIELD(insn, 3, 6);
@@ -1136,20 +1136,20 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_op_trap_T0();
                 } else if (cond != 0) {
 #ifdef TARGET_SPARC64
-		    /* V9 icc/xcc */
-		    int cc = GET_FIELD_SP(insn, 11, 12);
-		    flush_T2(dc);
+                    /* V9 icc/xcc */
+                    int cc = GET_FIELD_SP(insn, 11, 12);
+                    flush_T2(dc);
                     save_state(dc);
-		    if (cc == 0)
-			gen_cond[0][cond]();
-		    else if (cc == 2)
-			gen_cond[1][cond]();
-		    else
-			goto illegal_insn;
+                    if (cc == 0)
+                        gen_cond[0][cond]();
+                    else if (cc == 2)
+                        gen_cond[1][cond]();
+                    else
+                        goto illegal_insn;
 #else
-		    flush_T2(dc);
+                    flush_T2(dc);
                     save_state(dc);
-		    gen_cond[0][cond]();
+                    gen_cond[0][cond]();
 #endif
                     gen_op_trapcc_T0();
                 }
@@ -1176,56 +1176,56 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_movl_T0_reg(rd);
                     break;
 #ifdef TARGET_SPARC64
-		case 0x2: /* V9 rdccr */
+                case 0x2: /* V9 rdccr */
                     gen_op_rdccr();
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x3: /* V9 rdasi */
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
+                case 0x3: /* V9 rdasi */
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x4: /* V9 rdtick */
+                case 0x4: /* V9 rdtick */
                     gen_op_rdtick();
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x5: /* V9 rdpc */
-		    if (dc->pc == (uint32_t)dc->pc) {
-			gen_op_movl_T0_im(dc->pc);
-		    } else {
-			gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
-		    }
-		    gen_movl_T0_reg(rd);
-		    break;
-		case 0x6: /* V9 rdfprs */
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
+                case 0x5: /* V9 rdpc */
+                    if (dc->pc == (uint32_t)dc->pc) {
+                        gen_op_movl_T0_im(dc->pc);
+                    } else {
+                        gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+                    }
+                    gen_movl_T0_reg(rd);
+                    break;
+                case 0x6: /* V9 rdfprs */
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
                     gen_movl_T0_reg(rd);
                     break;
                 case 0xf: /* V9 membar */
                     break; /* no effect */
-		case 0x13: /* Graphics Status */
+                case 0x13: /* Graphics Status */
                     if (gen_trap_ifnofpu(dc))
                         goto jmp_insn;
-		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
+                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x17: /* Tick compare */
-		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
+                case 0x17: /* Tick compare */
+                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x18: /* System tick */
+                case 0x18: /* System tick */
                     gen_op_rdstick();
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x19: /* System tick compare */
-		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
+                case 0x19: /* System tick compare */
+                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
                     gen_movl_T0_reg(rd);
                     break;
-		case 0x10: /* Performance Control */
-		case 0x11: /* Performance Instrumentation Counter */
-		case 0x12: /* Dispatch Control */
-		case 0x14: /* Softint set, WO */
-		case 0x15: /* Softint clear, WO */
-		case 0x16: /* Softint write */
+                case 0x10: /* Performance Control */
+                case 0x11: /* Performance Instrumentation Counter */
+                case 0x12: /* Dispatch Control */
+                case 0x14: /* Softint set, WO */
+                case 0x15: /* Softint clear, WO */
+                case 0x16: /* Softint write */
 #endif
                 default:
                     goto illegal_insn;
@@ -1233,8 +1233,8 @@ static void disas_sparc_insn(DisasContext * dc)
 #if !defined(CONFIG_USER_ONLY)
             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
 #ifndef TARGET_SPARC64
-		if (!supervisor(dc))
-		    goto priv_insn;
+                if (!supervisor(dc))
+                    goto priv_insn;
                 gen_op_rdpsr();
 #else
                 if (!hypervisor(dc))
@@ -1266,56 +1266,56 @@ static void disas_sparc_insn(DisasContext * dc)
                 gen_movl_T0_reg(rd);
                 break;
             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
-		if (!supervisor(dc))
-		    goto priv_insn;
+                if (!supervisor(dc))
+                    goto priv_insn;
 #ifdef TARGET_SPARC64
                 rs1 = GET_FIELD(insn, 13, 17);
-		switch (rs1) {
-		case 0: // tpc
-		    gen_op_rdtpc();
-		    break;
-		case 1: // tnpc
-		    gen_op_rdtnpc();
-		    break;
-		case 2: // tstate
-		    gen_op_rdtstate();
-		    break;
-		case 3: // tt
-		    gen_op_rdtt();
-		    break;
-		case 4: // tick
-		    gen_op_rdtick();
-		    break;
-		case 5: // tba
-		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
-		    break;
-		case 6: // pstate
-		    gen_op_rdpstate();
-		    break;
-		case 7: // tl
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
-		    break;
-		case 8: // pil
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
-		    break;
-		case 9: // cwp
-		    gen_op_rdcwp();
-		    break;
-		case 10: // cansave
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
-		    break;
-		case 11: // canrestore
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
-		    break;
-		case 12: // cleanwin
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
-		    break;
-		case 13: // otherwin
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
-		    break;
-		case 14: // wstate
-		    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
-		    break;
+                switch (rs1) {
+                case 0: // tpc
+                    gen_op_rdtpc();
+                    break;
+                case 1: // tnpc
+                    gen_op_rdtnpc();
+                    break;
+                case 2: // tstate
+                    gen_op_rdtstate();
+                    break;
+                case 3: // tt
+                    gen_op_rdtt();
+                    break;
+                case 4: // tick
+                    gen_op_rdtick();
+                    break;
+                case 5: // tba
+                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+                    break;
+                case 6: // pstate
+                    gen_op_rdpstate();
+                    break;
+                case 7: // tl
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
+                    break;
+                case 8: // pil
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
+                    break;
+                case 9: // cwp
+                    gen_op_rdcwp();
+                    break;
+                case 10: // cansave
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
+                    break;
+                case 11: // canrestore
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
+                    break;
+                case 12: // cleanwin
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
+                    break;
+                case 13: // otherwin
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
+                    break;
+                case 14: // wstate
+                    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
+                    break;
                 case 16: // UA2005 gl
                     gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
                     break;
@@ -1324,506 +1324,506 @@ static void disas_sparc_insn(DisasContext * dc)
                         goto priv_insn;
                     gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
                     break;
-		case 31: // ver
-		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
-		    break;
-		case 15: // fq
-		default:
-		    goto illegal_insn;
-		}
+                case 31: // ver
+                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
+                    break;
+                case 15: // fq
+                default:
+                    goto illegal_insn;
+                }
 #else
-		gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
+                gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
 #endif
                 gen_movl_T0_reg(rd);
                 break;
             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
 #ifdef TARGET_SPARC64
-		gen_op_flushw();
+                gen_op_flushw();
 #else
-		if (!supervisor(dc))
-		    goto priv_insn;
-		gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+                if (!supervisor(dc))
+                    goto priv_insn;
+                gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
                 gen_movl_T0_reg(rd);
 #endif
                 break;
 #endif
-	    } else if (xop == 0x34) {	/* FPU Operations */
+            } else if (xop == 0x34) {   /* FPU Operations */
                 if (gen_trap_ifnofpu(dc))
                     goto jmp_insn;
-		gen_op_clear_ieee_excp_and_FTT();
+                gen_op_clear_ieee_excp_and_FTT();
                 rs1 = GET_FIELD(insn, 13, 17);
-	        rs2 = GET_FIELD(insn, 27, 31);
-	        xop = GET_FIELD(insn, 18, 26);
-		switch (xop) {
-		    case 0x1: /* fmovs */
-                	gen_op_load_fpr_FT0(rs2);
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x5: /* fnegs */
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fnegs();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x9: /* fabss */
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fabss();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x29: /* fsqrts */
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fsqrts();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x2a: /* fsqrtd */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fsqrtd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x2b: /* fsqrtq */
-		        goto nfpu_insn;
-		    case 0x41:
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fadds();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x42:
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_faddd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x43: /* faddq */
-		        goto nfpu_insn;
-		    case 0x45:
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fsubs();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x46:
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fsubd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x47: /* fsubq */
-		        goto nfpu_insn;
-		    case 0x49:
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fmuls();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x4a:
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fmuld();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x4b: /* fmulq */
-		        goto nfpu_insn;
-		    case 0x4d:
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fdivs();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x4e:
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-			gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fdivd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x4f: /* fdivq */
-		        goto nfpu_insn;
-		    case 0x69:
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fsmuld();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x6e: /* fdmulq */
-		        goto nfpu_insn;
-		    case 0xc4:
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fitos();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0xc6:
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fdtos();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0xc7: /* fqtos */
-		        goto nfpu_insn;
-		    case 0xc8:
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fitod();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0xc9:
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fstod();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0xcb: /* fqtod */
-		        goto nfpu_insn;
-		    case 0xcc: /* fitoq */
-		        goto nfpu_insn;
-		    case 0xcd: /* fstoq */
-		        goto nfpu_insn;
-		    case 0xce: /* fdtoq */
-		        goto nfpu_insn;
-		    case 0xd1:
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fstoi();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0xd2:
-                	gen_op_load_fpr_DT1(rs2);
-			gen_op_fdtoi();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0xd3: /* fqtoi */
-		        goto nfpu_insn;
+                rs2 = GET_FIELD(insn, 27, 31);
+                xop = GET_FIELD(insn, 18, 26);
+                switch (xop) {
+                    case 0x1: /* fmovs */
+                        gen_op_load_fpr_FT0(rs2);
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x5: /* fnegs */
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fnegs();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x9: /* fabss */
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fabss();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x29: /* fsqrts */
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fsqrts();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x2a: /* fsqrtd */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fsqrtd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x2b: /* fsqrtq */
+                        goto nfpu_insn;
+                    case 0x41:
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fadds();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x42:
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_faddd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x43: /* faddq */
+                        goto nfpu_insn;
+                    case 0x45:
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fsubs();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x46:
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fsubd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x47: /* fsubq */
+                        goto nfpu_insn;
+                    case 0x49:
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fmuls();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x4a:
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fmuld();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x4b: /* fmulq */
+                        goto nfpu_insn;
+                    case 0x4d:
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fdivs();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x4e:
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fdivd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x4f: /* fdivq */
+                        goto nfpu_insn;
+                    case 0x69:
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fsmuld();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x6e: /* fdmulq */
+                        goto nfpu_insn;
+                    case 0xc4:
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fitos();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0xc6:
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fdtos();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0xc7: /* fqtos */
+                        goto nfpu_insn;
+                    case 0xc8:
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fitod();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0xc9:
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fstod();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0xcb: /* fqtod */
+                        goto nfpu_insn;
+                    case 0xcc: /* fitoq */
+                        goto nfpu_insn;
+                    case 0xcd: /* fstoq */
+                        goto nfpu_insn;
+                    case 0xce: /* fdtoq */
+                        goto nfpu_insn;
+                    case 0xd1:
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fstoi();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0xd2:
+                        gen_op_load_fpr_DT1(rs2);
+                        gen_op_fdtoi();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0xd3: /* fqtoi */
+                        goto nfpu_insn;
 #ifdef TARGET_SPARC64
-		    case 0x2: /* V9 fmovd */
-                	gen_op_load_fpr_DT0(DFPREG(rs2));
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x6: /* V9 fnegd */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fnegd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0xa: /* V9 fabsd */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fabsd();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x81: /* V9 fstox */
-                	gen_op_load_fpr_FT1(rs2);
-			gen_op_fstox();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x82: /* V9 fdtox */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fdtox();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x84: /* V9 fxtos */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fxtos();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x88: /* V9 fxtod */
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
-			gen_op_fxtod();
-			gen_op_store_DT0_fpr(DFPREG(rd));
-			break;
-		    case 0x3: /* V9 fmovq */
-		    case 0x7: /* V9 fnegq */
-		    case 0xb: /* V9 fabsq */
-		    case 0x83: /* V9 fqtox */
-		    case 0x8c: /* V9 fxtoq */
-		        goto nfpu_insn;
-#endif
-		    default:
-                	goto illegal_insn;
-		}
-	    } else if (xop == 0x35) {	/* FPU Operations */
+                    case 0x2: /* V9 fmovd */
+                        gen_op_load_fpr_DT0(DFPREG(rs2));
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x6: /* V9 fnegd */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fnegd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0xa: /* V9 fabsd */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fabsd();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x81: /* V9 fstox */
+                        gen_op_load_fpr_FT1(rs2);
+                        gen_op_fstox();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x82: /* V9 fdtox */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fdtox();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x84: /* V9 fxtos */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fxtos();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x88: /* V9 fxtod */
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
+                        gen_op_fxtod();
+                        gen_op_store_DT0_fpr(DFPREG(rd));
+                        break;
+                    case 0x3: /* V9 fmovq */
+                    case 0x7: /* V9 fnegq */
+                    case 0xb: /* V9 fabsq */
+                    case 0x83: /* V9 fqtox */
+                    case 0x8c: /* V9 fxtoq */
+                        goto nfpu_insn;
+#endif
+                    default:
+                        goto illegal_insn;
+                }
+            } else if (xop == 0x35) {   /* FPU Operations */
 #ifdef TARGET_SPARC64
-		int cond;
+                int cond;
 #endif
                 if (gen_trap_ifnofpu(dc))
                     goto jmp_insn;
-		gen_op_clear_ieee_excp_and_FTT();
+                gen_op_clear_ieee_excp_and_FTT();
                 rs1 = GET_FIELD(insn, 13, 17);
-	        rs2 = GET_FIELD(insn, 27, 31);
-	        xop = GET_FIELD(insn, 18, 26);
+                rs2 = GET_FIELD(insn, 27, 31);
+                xop = GET_FIELD(insn, 18, 26);
 #ifdef TARGET_SPARC64
-		if ((xop & 0x11f) == 0x005) { // V9 fmovsr
-		    cond = GET_FIELD_SP(insn, 14, 17);
-		    gen_op_load_fpr_FT0(rd);
-		    gen_op_load_fpr_FT1(rs2);
-		    rs1 = GET_FIELD(insn, 13, 17);
-		    gen_movl_reg_T0(rs1);
-		    flush_T2(dc);
-		    gen_cond_reg(cond);
-		    gen_op_fmovs_cc();
-		    gen_op_store_FT0_fpr(rd);
-		    break;
-		} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
-		    cond = GET_FIELD_SP(insn, 14, 17);
-		    gen_op_load_fpr_DT0(rd);
-		    gen_op_load_fpr_DT1(rs2);
-		    flush_T2(dc);
-		    rs1 = GET_FIELD(insn, 13, 17);
-		    gen_movl_reg_T0(rs1);
-		    gen_cond_reg(cond);
-		    gen_op_fmovs_cc();
-		    gen_op_store_DT0_fpr(rd);
-		    break;
-		} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
-		    goto nfpu_insn;
-		}
-#endif
-		switch (xop) {
+                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
+                    cond = GET_FIELD_SP(insn, 14, 17);
+                    gen_op_load_fpr_FT0(rd);
+                    gen_op_load_fpr_FT1(rs2);
+                    rs1 = GET_FIELD(insn, 13, 17);
+                    gen_movl_reg_T0(rs1);
+                    flush_T2(dc);
+                    gen_cond_reg(cond);
+                    gen_op_fmovs_cc();
+                    gen_op_store_FT0_fpr(rd);
+                    break;
+                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
+                    cond = GET_FIELD_SP(insn, 14, 17);
+                    gen_op_load_fpr_DT0(rd);
+                    gen_op_load_fpr_DT1(rs2);
+                    flush_T2(dc);
+                    rs1 = GET_FIELD(insn, 13, 17);
+                    gen_movl_reg_T0(rs1);
+                    gen_cond_reg(cond);
+                    gen_op_fmovs_cc();
+                    gen_op_store_DT0_fpr(rd);
+                    break;
+                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
+                    goto nfpu_insn;
+                }
+#endif
+                switch (xop) {
 #ifdef TARGET_SPARC64
-		    case 0x001: /* V9 fmovscc %fcc0 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_fcond[0][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x002: /* V9 fmovdcc %fcc0 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_fcond[0][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x003: /* V9 fmovqcc %fcc0 */
-		        goto nfpu_insn;
-		    case 0x041: /* V9 fmovscc %fcc1 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_fcond[1][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x042: /* V9 fmovdcc %fcc1 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_fcond[1][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x043: /* V9 fmovqcc %fcc1 */
-		        goto nfpu_insn;
-		    case 0x081: /* V9 fmovscc %fcc2 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_fcond[2][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x082: /* V9 fmovdcc %fcc2 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_fcond[2][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x083: /* V9 fmovqcc %fcc2 */
-		        goto nfpu_insn;
-		    case 0x0c1: /* V9 fmovscc %fcc3 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_fcond[3][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x0c2: /* V9 fmovdcc %fcc3 */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_fcond[3][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x0c3: /* V9 fmovqcc %fcc3 */
-		        goto nfpu_insn;
-		    case 0x101: /* V9 fmovscc %icc */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_cond[0][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x102: /* V9 fmovdcc %icc */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_cond[0][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x103: /* V9 fmovqcc %icc */
-		        goto nfpu_insn;
-		    case 0x181: /* V9 fmovscc %xcc */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_FT0(rd);
-                	gen_op_load_fpr_FT1(rs2);
-			flush_T2(dc);
-			gen_cond[1][cond]();
-			gen_op_fmovs_cc();
-			gen_op_store_FT0_fpr(rd);
-			break;
-		    case 0x182: /* V9 fmovdcc %xcc */
-			cond = GET_FIELD_SP(insn, 14, 17);
-                	gen_op_load_fpr_DT0(rd);
-                	gen_op_load_fpr_DT1(rs2);
-			flush_T2(dc);
-			gen_cond[1][cond]();
-			gen_op_fmovd_cc();
-			gen_op_store_DT0_fpr(rd);
-			break;
-		    case 0x183: /* V9 fmovqcc %xcc */
-		        goto nfpu_insn;
-#endif
-		    case 0x51: /* V9 %fcc */
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
+                    case 0x001: /* V9 fmovscc %fcc0 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[0][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x002: /* V9 fmovdcc %fcc0 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[0][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x003: /* V9 fmovqcc %fcc0 */
+                        goto nfpu_insn;
+                    case 0x041: /* V9 fmovscc %fcc1 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[1][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x042: /* V9 fmovdcc %fcc1 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[1][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x043: /* V9 fmovqcc %fcc1 */
+                        goto nfpu_insn;
+                    case 0x081: /* V9 fmovscc %fcc2 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[2][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x082: /* V9 fmovdcc %fcc2 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[2][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x083: /* V9 fmovqcc %fcc2 */
+                        goto nfpu_insn;
+                    case 0x0c1: /* V9 fmovscc %fcc3 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[3][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x0c2: /* V9 fmovdcc %fcc3 */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_fcond[3][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x0c3: /* V9 fmovqcc %fcc3 */
+                        goto nfpu_insn;
+                    case 0x101: /* V9 fmovscc %icc */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_cond[0][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x102: /* V9 fmovdcc %icc */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_cond[0][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x103: /* V9 fmovqcc %icc */
+                        goto nfpu_insn;
+                    case 0x181: /* V9 fmovscc %xcc */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_FT0(rd);
+                        gen_op_load_fpr_FT1(rs2);
+                        flush_T2(dc);
+                        gen_cond[1][cond]();
+                        gen_op_fmovs_cc();
+                        gen_op_store_FT0_fpr(rd);
+                        break;
+                    case 0x182: /* V9 fmovdcc %xcc */
+                        cond = GET_FIELD_SP(insn, 14, 17);
+                        gen_op_load_fpr_DT0(rd);
+                        gen_op_load_fpr_DT1(rs2);
+                        flush_T2(dc);
+                        gen_cond[1][cond]();
+                        gen_op_fmovd_cc();
+                        gen_op_store_DT0_fpr(rd);
+                        break;
+                    case 0x183: /* V9 fmovqcc %xcc */
+                        goto nfpu_insn;
+#endif
+                    case 0x51: /* V9 %fcc */
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
 #ifdef TARGET_SPARC64
-			gen_fcmps[rd & 3]();
+                        gen_fcmps[rd & 3]();
 #else
-			gen_op_fcmps();
+                        gen_op_fcmps();
 #endif
-			break;
-		    case 0x52: /* V9 %fcc */
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
+                        break;
+                    case 0x52: /* V9 %fcc */
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
 #ifdef TARGET_SPARC64
-			gen_fcmpd[rd & 3]();
+                        gen_fcmpd[rd & 3]();
 #else
-			gen_op_fcmpd();
-#endif
-			break;
-		    case 0x53: /* fcmpq */
-		        goto nfpu_insn;
-		    case 0x55: /* fcmpes, V9 %fcc */
-                	gen_op_load_fpr_FT0(rs1);
-                	gen_op_load_fpr_FT1(rs2);
+                        gen_op_fcmpd();
+#endif
+                        break;
+                    case 0x53: /* fcmpq */
+                        goto nfpu_insn;
+                    case 0x55: /* fcmpes, V9 %fcc */
+                        gen_op_load_fpr_FT0(rs1);
+                        gen_op_load_fpr_FT1(rs2);
 #ifdef TARGET_SPARC64
-			gen_fcmpes[rd & 3]();
+                        gen_fcmpes[rd & 3]();
 #else
-			gen_op_fcmpes();
+                        gen_op_fcmpes();
 #endif
-			break;
-		    case 0x56: /* fcmped, V9 %fcc */
-                	gen_op_load_fpr_DT0(DFPREG(rs1));
-                	gen_op_load_fpr_DT1(DFPREG(rs2));
+                        break;
+                    case 0x56: /* fcmped, V9 %fcc */
+                        gen_op_load_fpr_DT0(DFPREG(rs1));
+                        gen_op_load_fpr_DT1(DFPREG(rs2));
 #ifdef TARGET_SPARC64
-			gen_fcmped[rd & 3]();
+                        gen_fcmped[rd & 3]();
 #else
-			gen_op_fcmped();
-#endif
-			break;
-		    case 0x57: /* fcmpeq */
-		        goto nfpu_insn;
-		    default:
-                	goto illegal_insn;
-		}
+                        gen_op_fcmped();
+#endif
+                        break;
+                    case 0x57: /* fcmpeq */
+                        goto nfpu_insn;
+                    default:
+                        goto illegal_insn;
+                }
 #if defined(OPTIM)
-	    } else if (xop == 0x2) {
-		// clr/mov shortcut
+            } else if (xop == 0x2) {
+                // clr/mov shortcut
                 rs1 = GET_FIELD(insn, 13, 17);
-		if (rs1 == 0) {
-		    // or %g0, x, y -> mov T1, x; mov y, T1
-		    if (IS_IMM) {	/* immediate */
-			rs2 = GET_FIELDs(insn, 19, 31);
-			gen_movl_simm_T1(rs2);
-		    } else {		/* register */
-			rs2 = GET_FIELD(insn, 27, 31);
-			gen_movl_reg_T1(rs2);
-		    }
-		    gen_movl_T1_reg(rd);
-		} else {
-		    gen_movl_reg_T0(rs1);
-		    if (IS_IMM) {	/* immediate */
-			// or x, #0, y -> mov T1, x; mov y, T1
-			rs2 = GET_FIELDs(insn, 19, 31);
-			if (rs2 != 0) {
-			    gen_movl_simm_T1(rs2);
-			    gen_op_or_T1_T0();
-			}
-		    } else {		/* register */
-			// or x, %g0, y -> mov T1, x; mov y, T1
-			rs2 = GET_FIELD(insn, 27, 31);
-			if (rs2 != 0) {
-			    gen_movl_reg_T1(rs2);
-			    gen_op_or_T1_T0();
-			}
-		    }
-		    gen_movl_T0_reg(rd);
-		}
+                if (rs1 == 0) {
+                    // or %g0, x, y -> mov T1, x; mov y, T1
+                    if (IS_IMM) {       /* immediate */
+                        rs2 = GET_FIELDs(insn, 19, 31);
+                        gen_movl_simm_T1(rs2);
+                    } else {            /* register */
+                        rs2 = GET_FIELD(insn, 27, 31);
+                        gen_movl_reg_T1(rs2);
+                    }
+                    gen_movl_T1_reg(rd);
+                } else {
+                    gen_movl_reg_T0(rs1);
+                    if (IS_IMM) {       /* immediate */
+                        // or x, #0, y -> mov T1, x; mov y, T1
+                        rs2 = GET_FIELDs(insn, 19, 31);
+                        if (rs2 != 0) {
+                            gen_movl_simm_T1(rs2);
+                            gen_op_or_T1_T0();
+                        }
+                    } else {            /* register */
+                        // or x, %g0, y -> mov T1, x; mov y, T1
+                        rs2 = GET_FIELD(insn, 27, 31);
+                        if (rs2 != 0) {
+                            gen_movl_reg_T1(rs2);
+                            gen_op_or_T1_T0();
+                        }
+                    }
+                    gen_movl_T0_reg(rd);
+                }
 #endif
 #ifdef TARGET_SPARC64
-	    } else if (xop == 0x25) { /* sll, V9 sllx */
+            } else if (xop == 0x25) { /* sll, V9 sllx */
                 rs1 = GET_FIELD(insn, 13, 17);
-		gen_movl_reg_T0(rs1);
-		if (IS_IMM) {	/* immediate */
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
                     rs2 = GET_FIELDs(insn, 20, 31);
                     gen_movl_simm_T1(rs2);
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
                     gen_movl_reg_T1(rs2);
                 }
-		if (insn & (1 << 12))
-		    gen_op_sllx();
-		else
-		    gen_op_sll();
-		gen_movl_T0_reg(rd);
-	    } else if (xop == 0x26) { /* srl, V9 srlx */
+                if (insn & (1 << 12))
+                    gen_op_sllx();
+                else
+                    gen_op_sll();
+                gen_movl_T0_reg(rd);
+            } else if (xop == 0x26) { /* srl, V9 srlx */
                 rs1 = GET_FIELD(insn, 13, 17);
-		gen_movl_reg_T0(rs1);
-		if (IS_IMM) {	/* immediate */
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
                     rs2 = GET_FIELDs(insn, 20, 31);
                     gen_movl_simm_T1(rs2);
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
                     gen_movl_reg_T1(rs2);
                 }
-		if (insn & (1 << 12))
-		    gen_op_srlx();
-		else
-		    gen_op_srl();
-		gen_movl_T0_reg(rd);
-	    } else if (xop == 0x27) { /* sra, V9 srax */
+                if (insn & (1 << 12))
+                    gen_op_srlx();
+                else
+                    gen_op_srl();
+                gen_movl_T0_reg(rd);
+            } else if (xop == 0x27) { /* sra, V9 srax */
                 rs1 = GET_FIELD(insn, 13, 17);
-		gen_movl_reg_T0(rs1);
-		if (IS_IMM) {	/* immediate */
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
                     rs2 = GET_FIELDs(insn, 20, 31);
                     gen_movl_simm_T1(rs2);
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
                     gen_movl_reg_T1(rs2);
                 }
-		if (insn & (1 << 12))
-		    gen_op_srax();
-		else
-		    gen_op_sra();
-		gen_movl_T0_reg(rd);
+                if (insn & (1 << 12))
+                    gen_op_srax();
+                else
+                    gen_op_sra();
+                gen_movl_T0_reg(rd);
 #endif
             } else if (xop < 0x36) {
                 rs1 = GET_FIELD(insn, 13, 17);
-		gen_movl_reg_T0(rs1);
-		if (IS_IMM) {	/* immediate */
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
                     rs2 = GET_FIELDs(insn, 19, 31);
                     gen_movl_simm_T1(rs2);
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
                     gen_movl_reg_T1(rs2);
                 }
@@ -1841,10 +1841,10 @@ static void disas_sparc_insn(DisasContext * dc)
                             gen_op_logic_T0_cc();
                         break;
                     case 0x2:
-			gen_op_or_T1_T0();
-			if (xop & 0x10)
-			    gen_op_logic_T0_cc();
-			break;
+                        gen_op_or_T1_T0();
+                        if (xop & 0x10)
+                            gen_op_logic_T0_cc();
+                        break;
                     case 0x3:
                         gen_op_xor_T1_T0();
                         if (xop & 0x10)
@@ -1878,7 +1878,7 @@ static void disas_sparc_insn(DisasContext * dc)
                             gen_op_addx_T1_T0();
                         break;
 #ifdef TARGET_SPARC64
-		    case 0x9: /* V9 mulx */
+                    case 0x9: /* V9 mulx */
                         gen_op_mulx_T1_T0();
                         break;
 #endif
@@ -1899,7 +1899,7 @@ static void disas_sparc_insn(DisasContext * dc)
                             gen_op_subx_T1_T0();
                         break;
 #ifdef TARGET_SPARC64
-		    case 0xd: /* V9 udivx */
+                    case 0xd: /* V9 udivx */
                         gen_op_udivx_T1_T0();
                         break;
 #endif
@@ -1916,40 +1916,40 @@ static void disas_sparc_insn(DisasContext * dc)
                     default:
                         goto illegal_insn;
                     }
-		    gen_movl_T0_reg(rd);
+                    gen_movl_T0_reg(rd);
                 } else {
                     switch (xop) {
-		    case 0x20: /* taddcc */
-			gen_op_tadd_T1_T0_cc();
-		        gen_movl_T0_reg(rd);
-			break;
-		    case 0x21: /* tsubcc */
-			gen_op_tsub_T1_T0_cc();
-		        gen_movl_T0_reg(rd);
-			break;
-		    case 0x22: /* taddcctv */
-			gen_op_tadd_T1_T0_ccTV();
-		        gen_movl_T0_reg(rd);
-			break;
-		    case 0x23: /* tsubcctv */
-			gen_op_tsub_T1_T0_ccTV();
-		        gen_movl_T0_reg(rd);
-			break;
+                    case 0x20: /* taddcc */
+                        gen_op_tadd_T1_T0_cc();
+                        gen_movl_T0_reg(rd);
+                        break;
+                    case 0x21: /* tsubcc */
+                        gen_op_tsub_T1_T0_cc();
+                        gen_movl_T0_reg(rd);
+                        break;
+                    case 0x22: /* taddcctv */
+                        gen_op_tadd_T1_T0_ccTV();
+                        gen_movl_T0_reg(rd);
+                        break;
+                    case 0x23: /* tsubcctv */
+                        gen_op_tsub_T1_T0_ccTV();
+                        gen_movl_T0_reg(rd);
+                        break;
                     case 0x24: /* mulscc */
                         gen_op_mulscc_T1_T0();
                         gen_movl_T0_reg(rd);
                         break;
 #ifndef TARGET_SPARC64
-                    case 0x25:	/* sll */
-			gen_op_sll();
+                    case 0x25:  /* sll */
+                        gen_op_sll();
                         gen_movl_T0_reg(rd);
                         break;
                     case 0x26:  /* srl */
-			gen_op_srl();
+                        gen_op_srl();
                         gen_movl_T0_reg(rd);
                         break;
                     case 0x27:  /* sra */
-			gen_op_sra();
+                        gen_op_sra();
                         gen_movl_T0_reg(rd);
                         break;
 #endif
@@ -1957,8 +1957,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         {
                             switch(rd) {
                             case 0: /* wry */
-				gen_op_xor_T1_T0();
-				gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
+                                gen_op_xor_T1_T0();
+                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
                                 break;
 #ifndef TARGET_SPARC64
                             case 0x01 ... 0x0f: /* undefined in the
@@ -1971,62 +1971,62 @@ static void disas_sparc_insn(DisasContext * dc)
                                                    microSPARC II */
                                 break;
 #else
-			    case 0x2: /* V9 wrccr */
+                            case 0x2: /* V9 wrccr */
                                 gen_op_wrccr();
-				break;
-			    case 0x3: /* V9 wrasi */
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
-				break;
-			    case 0x6: /* V9 wrfprs */
-				gen_op_xor_T1_T0();
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
+                                break;
+                            case 0x3: /* V9 wrasi */
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
+                                break;
+                            case 0x6: /* V9 wrfprs */
+                                gen_op_xor_T1_T0();
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
                                 save_state(dc);
                                 gen_op_next_insn();
                                 gen_op_movl_T0_0();
                                 gen_op_exit_tb();
                                 dc->is_br = 1;
-				break;
-			    case 0xf: /* V9 sir, nop if user */
+                                break;
+                            case 0xf: /* V9 sir, nop if user */
 #if !defined(CONFIG_USER_ONLY)
-				if (supervisor(dc))
-				    gen_op_sir();
+                                if (supervisor(dc))
+                                    gen_op_sir();
 #endif
-				break;
-			    case 0x13: /* Graphics Status */
+                                break;
+                            case 0x13: /* Graphics Status */
                                 if (gen_trap_ifnofpu(dc))
                                     goto jmp_insn;
-				gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
-				break;
-			    case 0x17: /* Tick compare */
+                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
+                                break;
+                            case 0x17: /* Tick compare */
 #if !defined(CONFIG_USER_ONLY)
-				if (!supervisor(dc))
-				    goto illegal_insn;
+                                if (!supervisor(dc))
+                                    goto illegal_insn;
 #endif
                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
                                 gen_op_wrtick_cmpr();
-				break;
-			    case 0x18: /* System tick */
+                                break;
+                            case 0x18: /* System tick */
 #if !defined(CONFIG_USER_ONLY)
-				if (!supervisor(dc))
-				    goto illegal_insn;
+                                if (!supervisor(dc))
+                                    goto illegal_insn;
 #endif
                                 gen_op_wrstick();
-				break;
-			    case 0x19: /* System tick compare */
+                                break;
+                            case 0x19: /* System tick compare */
 #if !defined(CONFIG_USER_ONLY)
-				if (!supervisor(dc))
-				    goto illegal_insn;
+                                if (!supervisor(dc))
+                                    goto illegal_insn;
 #endif
                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
                                 gen_op_wrstick_cmpr();
-				break;
+                                break;
-			    case 0x10: /* Performance Control */
-			    case 0x11: /* Performance Instrumentation Counter */
-			    case 0x12: /* Dispatch Control */
-			    case 0x14: /* Softint set */
-			    case 0x15: /* Softint clear */
-			    case 0x16: /* Softint write */
+                            case 0x10: /* Performance Control */
+                            case 0x11: /* Performance Instrumentation Counter */
+                            case 0x12: /* Dispatch Control */
+                            case 0x14: /* Softint set */
+                            case 0x15: /* Softint clear */
+                            case 0x16: /* Softint write */
 #endif
                             default:
                                 goto illegal_insn;
@@ -2036,22 +2036,22 @@ static void disas_sparc_insn(DisasContext * dc)
 #if !defined(CONFIG_USER_ONLY)
                     case 0x31: /* wrpsr, V9 saved, restored */
                         {
-			    if (!supervisor(dc))
-				goto priv_insn;
+                            if (!supervisor(dc))
+                                goto priv_insn;
 #ifdef TARGET_SPARC64
-			    switch (rd) {
-			    case 0:
-				gen_op_saved();
-				break;
-			    case 1:
-				gen_op_restored();
-				break;
+                            switch (rd) {
+                            case 0:
+                                gen_op_saved();
+                                break;
+                            case 1:
+                                gen_op_restored();
+                                break;
                             case 2: /* UA2005 allclean */
                             case 3: /* UA2005 otherw */
                             case 4: /* UA2005 normalw */
                             case 5: /* UA2005 invalw */
                                 // XXX
-			    default:
+                            default:
                                 goto illegal_insn;
                             }
 #else
@@ -2059,69 +2059,69 @@ static void disas_sparc_insn(DisasContext * dc)
                             gen_op_wrpsr();
                             save_state(dc);
                             gen_op_next_insn();
-			    gen_op_movl_T0_0();
-			    gen_op_exit_tb();
-			    dc->is_br = 1;
+                            gen_op_movl_T0_0();
+                            gen_op_exit_tb();
+                            dc->is_br = 1;
 #endif
                         }
                         break;
                     case 0x32: /* wrwim, V9 wrpr */
                         {
-			    if (!supervisor(dc))
-				goto priv_insn;
+                            if (!supervisor(dc))
+                                goto priv_insn;
                             gen_op_xor_T1_T0();
 #ifdef TARGET_SPARC64
-			    switch (rd) {
-			    case 0: // tpc
-				gen_op_wrtpc();
-				break;
-			    case 1: // tnpc
-				gen_op_wrtnpc();
-				break;
-			    case 2: // tstate
-				gen_op_wrtstate();
-				break;
-			    case 3: // tt
-				gen_op_wrtt();
-				break;
-			    case 4: // tick
-				gen_op_wrtick();
-				break;
-			    case 5: // tba
-				gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
-				break;
-			    case 6: // pstate
-				gen_op_wrpstate();
+                            switch (rd) {
+                            case 0: // tpc
+                                gen_op_wrtpc();
+                                break;
+                            case 1: // tnpc
+                                gen_op_wrtnpc();
+                                break;
+                            case 2: // tstate
+                                gen_op_wrtstate();
+                                break;
+                            case 3: // tt
+                                gen_op_wrtt();
+                                break;
+                            case 4: // tick
+                                gen_op_wrtick();
+                                break;
+                            case 5: // tba
+                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+                                break;
+                            case 6: // pstate
+                                gen_op_wrpstate();
                                 save_state(dc);
                                 gen_op_next_insn();
                                 gen_op_movl_T0_0();
                                 gen_op_exit_tb();
                                 dc->is_br = 1;
-				break;
-			    case 7: // tl
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
-				break;
-			    case 8: // pil
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
-				break;
-			    case 9: // cwp
-				gen_op_wrcwp();
-				break;
-			    case 10: // cansave
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
-				break;
-			    case 11: // canrestore
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
-				break;
-			    case 12: // cleanwin
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
-				break;
-			    case 13: // otherwin
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
-				break;
-			    case 14: // wstate
-				gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
-				break;
+                                break;
+                            case 7: // tl
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
+                                break;
+                            case 8: // pil
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
+                                break;
+                            case 9: // cwp
+                                gen_op_wrcwp();
+                                break;
+                            case 10: // cansave
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
+                                break;
+                            case 11: // canrestore
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
+                                break;
+                            case 12: // cleanwin
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
+                                break;
+                            case 13: // otherwin
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
+                                break;
+                            case 14: // wstate
+                                gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
+                                break;
                             case 16: // UA2005 gl
                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
                                 break;
@@ -2130,19 +2130,19 @@ static void disas_sparc_insn(DisasContext * dc)
                                     goto priv_insn;
                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
                                 break;
-			    default:
-				goto illegal_insn;
-			    }
+                            default:
+                                goto illegal_insn;
+                            }
 #else
-			    gen_op_wrwim();
+                            gen_op_wrwim();
 #endif
                         }
                         break;
                     case 0x33: /* wrtbr, UA2005 wrhpr */
                         {
 #ifndef TARGET_SPARC64
-			    if (!supervisor(dc))
-				goto priv_insn;
+                            if (!supervisor(dc))
+                                goto priv_insn;
                             gen_op_xor_T1_T0();
                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
 #else
@@ -2180,77 +2180,77 @@ static void disas_sparc_insn(DisasContext * dc)
                         break;
 #endif
 #ifdef TARGET_SPARC64
-		    case 0x2c: /* V9 movcc */
-			{
-			    int cc = GET_FIELD_SP(insn, 11, 12);
-			    int cond = GET_FIELD_SP(insn, 14, 17);
-			    if (IS_IMM) {	/* immediate */
-				rs2 = GET_FIELD_SPs(insn, 0, 10);
-				gen_movl_simm_T1(rs2);
-			    }
-			    else {
-				rs2 = GET_FIELD_SP(insn, 0, 4);
-				gen_movl_reg_T1(rs2);
-			    }
-			    gen_movl_reg_T0(rd);
-			    flush_T2(dc);
-			    if (insn & (1 << 18)) {
-				if (cc == 0)
-				    gen_cond[0][cond]();
-				else if (cc == 2)
-				    gen_cond[1][cond]();
-				else
-				    goto illegal_insn;
-			    } else {
-				gen_fcond[cc][cond]();
-			    }
-			    gen_op_mov_cc();
-			    gen_movl_T0_reg(rd);
-			    break;
-			}
-		    case 0x2d: /* V9 sdivx */
+                    case 0x2c: /* V9 movcc */
+                        {
+                            int cc = GET_FIELD_SP(insn, 11, 12);
+                            int cond = GET_FIELD_SP(insn, 14, 17);
+                            if (IS_IMM) {       /* immediate */
+                                rs2 = GET_FIELD_SPs(insn, 0, 10);
+                                gen_movl_simm_T1(rs2);
+                            }
+                            else {
+                                rs2 = GET_FIELD_SP(insn, 0, 4);
+                                gen_movl_reg_T1(rs2);
+                            }
+                            gen_movl_reg_T0(rd);
+                            flush_T2(dc);
+                            if (insn & (1 << 18)) {
+                                if (cc == 0)
+                                    gen_cond[0][cond]();
+                                else if (cc == 2)
+                                    gen_cond[1][cond]();
+                                else
+                                    goto illegal_insn;
+                            } else {
+                                gen_fcond[cc][cond]();
+                            }
+                            gen_op_mov_cc();
+                            gen_movl_T0_reg(rd);
+                            break;
+                        }
+                    case 0x2d: /* V9 sdivx */
                         gen_op_sdivx_T1_T0();
-			gen_movl_T0_reg(rd);
-                        break;
-		    case 0x2e: /* V9 popc */
-			{
-			    if (IS_IMM) {	/* immediate */
-				rs2 = GET_FIELD_SPs(insn, 0, 12);
-				gen_movl_simm_T1(rs2);
-				// XXX optimize: popc(constant)
-			    }
-			    else {
-				rs2 = GET_FIELD_SP(insn, 0, 4);
-				gen_movl_reg_T1(rs2);
-			    }
-			    gen_op_popc();
-			    gen_movl_T0_reg(rd);
-			}
-		    case 0x2f: /* V9 movr */
-			{
-			    int cond = GET_FIELD_SP(insn, 10, 12);
-			    rs1 = GET_FIELD(insn, 13, 17);
-			    flush_T2(dc);
-			    gen_movl_reg_T0(rs1);
-			    gen_cond_reg(cond);
-			    if (IS_IMM) {	/* immediate */
-				rs2 = GET_FIELD_SPs(insn, 0, 9);
-				gen_movl_simm_T1(rs2);
-			    }
-			    else {
-				rs2 = GET_FIELD_SP(insn, 0, 4);
-				gen_movl_reg_T1(rs2);
-			    }
-			    gen_movl_reg_T0(rd);
-			    gen_op_mov_cc();
-			    gen_movl_T0_reg(rd);
-			    break;
-			}
-#endif
-		    default:
-			goto illegal_insn;
-		    }
-		}
+                        gen_movl_T0_reg(rd);
+                        break;
+                    case 0x2e: /* V9 popc */
+                        {
+                            if (IS_IMM) {       /* immediate */
+                                rs2 = GET_FIELD_SPs(insn, 0, 12);
+                                gen_movl_simm_T1(rs2);
+                                // XXX optimize: popc(constant)
+                            }
+                            else {
+                                rs2 = GET_FIELD_SP(insn, 0, 4);
+                                gen_movl_reg_T1(rs2);
+                            }
+                            gen_op_popc();
+                            gen_movl_T0_reg(rd);
+                        }
+                    case 0x2f: /* V9 movr */
+                        {
+                            int cond = GET_FIELD_SP(insn, 10, 12);
+                            rs1 = GET_FIELD(insn, 13, 17);
+                            flush_T2(dc);
+                            gen_movl_reg_T0(rs1);
+                            gen_cond_reg(cond);
+                            if (IS_IMM) {       /* immediate */
+                                rs2 = GET_FIELD_SPs(insn, 0, 9);
+                                gen_movl_simm_T1(rs2);
+                            }
+                            else {
+                                rs2 = GET_FIELD_SP(insn, 0, 4);
+                                gen_movl_reg_T1(rs2);
+                            }
+                            gen_movl_reg_T0(rd);
+                            gen_op_mov_cc();
+                            gen_movl_T0_reg(rd);
+                            break;
+                        }
+#endif
+                    default:
+                        goto illegal_insn;
+                    }
+                }
             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
 #ifdef TARGET_SPARC64
                 int opf = GET_FIELD_SP(insn, 5, 13);
@@ -2647,75 +2647,75 @@ static void disas_sparc_insn(DisasContext * dc)
                     goto illegal_insn;
                 }
 #else
-	        goto ncp_insn;
+                goto ncp_insn;
 #endif
             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
 #ifdef TARGET_SPARC64
-	        goto illegal_insn;
+                goto illegal_insn;
 #else
-	        goto ncp_insn;
+                goto ncp_insn;
 #endif
 #ifdef TARGET_SPARC64
-	    } else if (xop == 0x39) { /* V9 return */
+            } else if (xop == 0x39) { /* V9 return */
                 rs1 = GET_FIELD(insn, 13, 17);
                 save_state(dc);
-		gen_movl_reg_T0(rs1);
-                if (IS_IMM) {	/* immediate */
-		    rs2 = GET_FIELDs(insn, 19, 31);
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
+                    rs2 = GET_FIELDs(insn, 19, 31);
 #if defined(OPTIM)
-		    if (rs2) {
+                    if (rs2) {
 #endif
-			gen_movl_simm_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_simm_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
 #if defined(OPTIM)
-		    if (rs2) {
+                    if (rs2) {
 #endif
-			gen_movl_reg_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_reg_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
                 }
-		gen_op_restore();
-		gen_mov_pc_npc(dc);
+                gen_op_restore();
+                gen_mov_pc_npc(dc);
                 gen_op_check_align_T0_3();
-		gen_op_movl_npc_T0();
-		dc->npc = DYNAMIC_PC;
-		goto jmp_insn;
+                gen_op_movl_npc_T0();
+                dc->npc = DYNAMIC_PC;
+                goto jmp_insn;
 #endif
-	    } else {
+            } else {
                 rs1 = GET_FIELD(insn, 13, 17);
-		gen_movl_reg_T0(rs1);
-                if (IS_IMM) {	/* immediate */
-		    rs2 = GET_FIELDs(insn, 19, 31);
+                gen_movl_reg_T0(rs1);
+                if (IS_IMM) {   /* immediate */
+                    rs2 = GET_FIELDs(insn, 19, 31);
 #if defined(OPTIM)
-		    if (rs2) {
+                    if (rs2) {
 #endif
-			gen_movl_simm_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_simm_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
-                } else {		/* register */
+                } else {                /* register */
                     rs2 = GET_FIELD(insn, 27, 31);
 #if defined(OPTIM)
-		    if (rs2) {
+                    if (rs2) {
 #endif
-			gen_movl_reg_T1(rs2);
-			gen_op_add_T1_T0();
+                        gen_movl_reg_T1(rs2);
+                        gen_op_add_T1_T0();
 #if defined(OPTIM)
-		    }
+                    }
 #endif
                 }
-		switch (xop) {
-		case 0x38:	/* jmpl */
-		    {
-			if (rd != 0) {
+                switch (xop) {
+                case 0x38:      /* jmpl */
+                    {
+                        if (rd != 0) {
 #ifdef TARGET_SPARC64
                             if (dc->pc == (uint32_t)dc->pc) {
                                 gen_op_movl_T1_im(dc->pc);
@@ -2723,250 +2723,250 @@ static void disas_sparc_insn(DisasContext * dc)
                                 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
                             }
 #else
-			    gen_op_movl_T1_im(dc->pc);
+                            gen_op_movl_T1_im(dc->pc);
 #endif
-			    gen_movl_T1_reg(rd);
-			}
+                            gen_movl_T1_reg(rd);
+                        }
                         gen_mov_pc_npc(dc);
                         gen_op_check_align_T0_3();
-			gen_op_movl_npc_T0();
-			dc->npc = DYNAMIC_PC;
-		    }
-		    goto jmp_insn;
+                        gen_op_movl_npc_T0();
+                        dc->npc = DYNAMIC_PC;
+                    }
+                    goto jmp_insn;
 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
-		case 0x39:	/* rett, V9 return */
-		    {
-			if (!supervisor(dc))
-			    goto priv_insn;
+                case 0x39:      /* rett, V9 return */
+                    {
+                        if (!supervisor(dc))
+                            goto priv_insn;
                         gen_mov_pc_npc(dc);
                         gen_op_check_align_T0_3();
-			gen_op_movl_npc_T0();
-			dc->npc = DYNAMIC_PC;
-			gen_op_rett();
-		    }
-		    goto jmp_insn;
-#endif
-		case 0x3b: /* flush */
-		    gen_op_flush_T0();
-		    break;
-		case 0x3c:	/* save */
-		    save_state(dc);
-		    gen_op_save();
-		    gen_movl_T0_reg(rd);
-		    break;
-		case 0x3d:	/* restore */
-		    save_state(dc);
-		    gen_op_restore();
-		    gen_movl_T0_reg(rd);
-		    break;
+                        gen_op_movl_npc_T0();
+                        dc->npc = DYNAMIC_PC;
+                        gen_op_rett();
+                    }
+                    goto jmp_insn;
+#endif
+                case 0x3b: /* flush */
+                    gen_op_flush_T0();
+                    break;
+                case 0x3c:      /* save */
+                    save_state(dc);
+                    gen_op_save();
+                    gen_movl_T0_reg(rd);
+                    break;
+                case 0x3d:      /* restore */
+                    save_state(dc);
+                    gen_op_restore();
+                    gen_movl_T0_reg(rd);
+                    break;
 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
-		case 0x3e:      /* V9 done/retry */
-		    {
-			switch (rd) {
-			case 0:
-			    if (!supervisor(dc))
-				goto priv_insn;
-			    dc->npc = DYNAMIC_PC;
-			    dc->pc = DYNAMIC_PC;
-			    gen_op_done();
-			    goto jmp_insn;
-			case 1:
-			    if (!supervisor(dc))
-				goto priv_insn;
-			    dc->npc = DYNAMIC_PC;
-			    dc->pc = DYNAMIC_PC;
-			    gen_op_retry();
-			    goto jmp_insn;
-			default:
-			    goto illegal_insn;
-			}
-		    }
-		    break;
-#endif
-		default:
-		    goto illegal_insn;
-		}
+                case 0x3e:      /* V9 done/retry */
+                    {
+                        switch (rd) {
+                        case 0:
+                            if (!supervisor(dc))
+                                goto priv_insn;
+                            dc->npc = DYNAMIC_PC;
+                            dc->pc = DYNAMIC_PC;
+                            gen_op_done();
+                            goto jmp_insn;
+                        case 1:
+                            if (!supervisor(dc))
+                                goto priv_insn;
+                            dc->npc = DYNAMIC_PC;
+                            dc->pc = DYNAMIC_PC;
+                            gen_op_retry();
+                            goto jmp_insn;
+                        default:
+                            goto illegal_insn;
+                        }
+                    }
+                    break;
+#endif
+                default:
+                    goto illegal_insn;
+                }
             }
-	    break;
-	}
-	break;
-    case 3:			/* load/store instructions */
-	{
-	    unsigned int xop = GET_FIELD(insn, 7, 12);
-	    rs1 = GET_FIELD(insn, 13, 17);
+            break;
+        }
+        break;
+    case 3:                     /* load/store instructions */
+        {
+            unsigned int xop = GET_FIELD(insn, 7, 12);
+            rs1 = GET_FIELD(insn, 13, 17);
             save_state(dc);
-	    gen_movl_reg_T0(rs1);
-	    if (IS_IMM) {	/* immediate */
-		rs2 = GET_FIELDs(insn, 19, 31);
+            gen_movl_reg_T0(rs1);
+            if (IS_IMM) {       /* immediate */
+                rs2 = GET_FIELDs(insn, 19, 31);
 #if defined(OPTIM)
-		if (rs2 != 0) {
+                if (rs2 != 0) {
 #endif
-		    gen_movl_simm_T1(rs2);
-		    gen_op_add_T1_T0();
+                    gen_movl_simm_T1(rs2);
+                    gen_op_add_T1_T0();
 #if defined(OPTIM)
-		}
+                }
 #endif
-	    } else {		/* register */
-		rs2 = GET_FIELD(insn, 27, 31);
+            } else {            /* register */
+                rs2 = GET_FIELD(insn, 27, 31);
 #if defined(OPTIM)
-		if (rs2 != 0) {
+                if (rs2 != 0) {
 #endif
-		    gen_movl_reg_T1(rs2);
-		    gen_op_add_T1_T0();
+                    gen_movl_reg_T1(rs2);
+                    gen_op_add_T1_T0();
 #if defined(OPTIM)
-		}
+                }
 #endif
-	    }
+            }
             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
                 (xop > 0x17 && xop <= 0x1d ) ||
                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
-		switch (xop) {
-		case 0x0:	/* load word */
+                switch (xop) {
+                case 0x0:       /* load word */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
 #ifndef TARGET_SPARC64
-		    gen_op_ldst(ld);
+                    gen_op_ldst(ld);
 #else
                     gen_op_ldst(lduw);
 #endif
-		    break;
-		case 0x1:	/* load unsigned byte */
-		    gen_op_ldst(ldub);
-		    break;
-		case 0x2:	/* load unsigned halfword */
+                    break;
+                case 0x1:       /* load unsigned byte */
+                    gen_op_ldst(ldub);
+                    break;
+                case 0x2:       /* load unsigned halfword */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_ldst(lduh);
-		    break;
-		case 0x3:	/* load double word */
+                    gen_op_ldst(lduh);
+                    break;
+                case 0x3:       /* load double word */
                     gen_op_check_align_T0_7();
-		    if (rd & 1)
+                    if (rd & 1)
                         goto illegal_insn;
-		    gen_op_ldst(ldd);
-		    gen_movl_T0_reg(rd + 1);
-		    break;
-		case 0x9:	/* load signed byte */
-		    gen_op_ldst(ldsb);
-		    break;
-		case 0xa:	/* load signed halfword */
+                    gen_op_ldst(ldd);
+                    gen_movl_T0_reg(rd + 1);
+                    break;
+                case 0x9:       /* load signed byte */
+                    gen_op_ldst(ldsb);
+                    break;
+                case 0xa:       /* load signed halfword */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_ldst(ldsh);
-		    break;
-		case 0xd:	/* ldstub -- XXX: should be atomically */
-		    gen_op_ldst(ldstub);
-		    break;
-		case 0x0f:	/* swap register with memory. Also atomically */
+                    gen_op_ldst(ldsh);
+                    break;
+                case 0xd:       /* ldstub -- XXX: should be atomically */
+                    gen_op_ldst(ldstub);
+                    break;
+                case 0x0f:      /* swap register with memory. Also atomically */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_movl_reg_T1(rd);
-		    gen_op_ldst(swap);
-		    break;
+                    gen_movl_reg_T1(rd);
+                    gen_op_ldst(swap);
+                    break;
 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-		case 0x10:	/* load word alternate */
+                case 0x10:      /* load word alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_lda(insn, 1, 4, 0);
+                    gen_op_lda(insn, 1, 4, 0);
 #else
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
                     gen_op_lduwa(insn, 1, 4, 0);
 #endif
-		    break;
-		case 0x11:	/* load unsigned byte alternate */
+                    break;
+                case 0x11:      /* load unsigned byte alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
-#endif
-		    gen_op_lduba(insn, 1, 1, 0);
-		    break;
-		case 0x12:	/* load unsigned halfword alternate */
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
+#endif
+                    gen_op_lduba(insn, 1, 1, 0);
+                    break;
+                case 0x12:      /* load unsigned halfword alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_lduha(insn, 1, 2, 0);
-		    break;
-		case 0x13:	/* load double word alternate */
+                    gen_op_lduha(insn, 1, 2, 0);
+                    break;
+                case 0x13:      /* load double word alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
-		    if (rd & 1)
+                    if (rd & 1)
                         goto illegal_insn;
                     gen_op_check_align_T0_7();
-		    gen_op_ldda(insn, 1, 8, 0);
-		    gen_movl_T0_reg(rd + 1);
-		    break;
-		case 0x19:	/* load signed byte alternate */
+                    gen_op_ldda(insn, 1, 8, 0);
+                    gen_movl_T0_reg(rd + 1);
+                    break;
+                case 0x19:      /* load signed byte alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
-#endif
-		    gen_op_ldsba(insn, 1, 1, 1);
-		    break;
-		case 0x1a:	/* load signed halfword alternate */
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
+#endif
+                    gen_op_ldsba(insn, 1, 1, 1);
+                    break;
+                case 0x1a:      /* load signed halfword alternate */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_ldsha(insn, 1, 2 ,1);
-		    break;
-		case 0x1d:	/* ldstuba -- XXX: should be atomically */
+                    gen_op_ldsha(insn, 1, 2 ,1);
+                    break;
+                case 0x1d:      /* ldstuba -- XXX: should be atomically */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
-#endif
-		    gen_op_ldstuba(insn, 1, 1, 0);
-		    break;
-		case 0x1f:	/* swap reg with alt. memory. Also atomically */
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
+#endif
+                    gen_op_ldstuba(insn, 1, 1, 0);
+                    break;
+                case 0x1f:      /* swap reg with alt. memory. Also atomically */
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
-		    gen_movl_reg_T1(rd);
+                    gen_movl_reg_T1(rd);
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_swapa(insn, 1, 4, 0);
-		    break;
+                    gen_op_swapa(insn, 1, 4, 0);
+                    break;
 #ifndef TARGET_SPARC64
-		case 0x30: /* ldc */
-		case 0x31: /* ldcsr */
-		case 0x33: /* lddc */
-		    goto ncp_insn;
+                case 0x30: /* ldc */
+                case 0x31: /* ldcsr */
+                case 0x33: /* lddc */
+                    goto ncp_insn;
                     /* avoid warnings */
                     (void) &gen_op_stfa;
                     (void) &gen_op_stdfa;
@@ -2975,260 +2975,260 @@ static void disas_sparc_insn(DisasContext * dc)
 #else
                     (void) &gen_op_lda;
 #if !defined(CONFIG_USER_ONLY)
-		    (void) &gen_op_cas;
-		    (void) &gen_op_casx;
+                    (void) &gen_op_cas;
+                    (void) &gen_op_casx;
 #endif
 #endif
 #endif
 #ifdef TARGET_SPARC64
-		case 0x08: /* V9 ldsw */
+                case 0x08: /* V9 ldsw */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldst(ldsw);
-		    break;
-		case 0x0b: /* V9 ldx */
+                    gen_op_ldst(ldsw);
+                    break;
+                case 0x0b: /* V9 ldx */
                     gen_op_check_align_T0_7();
-		    gen_op_ldst(ldx);
-		    break;
-		case 0x18: /* V9 ldswa */
+                    gen_op_ldst(ldx);
+                    break;
+                case 0x18: /* V9 ldswa */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldswa(insn, 1, 4, 1);
-		    break;
-		case 0x1b: /* V9 ldxa */
+                    gen_op_ldswa(insn, 1, 4, 1);
+                    break;
+                case 0x1b: /* V9 ldxa */
                     gen_op_check_align_T0_7();
-		    gen_op_ldxa(insn, 1, 8, 0);
-		    break;
-		case 0x2d: /* V9 prefetch, no effect */
-		    goto skip_move;
-		case 0x30: /* V9 ldfa */
+                    gen_op_ldxa(insn, 1, 8, 0);
+                    break;
+                case 0x2d: /* V9 prefetch, no effect */
+                    goto skip_move;
+                case 0x30: /* V9 ldfa */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldfa(insn, 1, 8, 0); // XXX
-		    break;
-		case 0x33: /* V9 lddfa */
+                    gen_op_ldfa(insn, 1, 8, 0); // XXX
+                    break;
+                case 0x33: /* V9 lddfa */
                     gen_op_check_align_T0_7();
-		    gen_op_lddfa(insn, 1, 8, 0); // XXX
-
-		    break;
-		case 0x3d: /* V9 prefetcha, no effect */
-		    goto skip_move;
-		case 0x32: /* V9 ldqfa */
-		    goto nfpu_insn;
-#endif
-		default:
-		    goto illegal_insn;
-		}
-		gen_movl_T1_reg(rd);
+                    gen_op_lddfa(insn, 1, 8, 0); // XXX
+
+                    break;
+                case 0x3d: /* V9 prefetcha, no effect */
+                    goto skip_move;
+                case 0x32: /* V9 ldqfa */
+                    goto nfpu_insn;
+#endif
+                default:
+                    goto illegal_insn;
+                }
+                gen_movl_T1_reg(rd);
 #ifdef TARGET_SPARC64
-	    skip_move: ;
+            skip_move: ;
 #endif
-	    } else if (xop >= 0x20 && xop < 0x24) {
+            } else if (xop >= 0x20 && xop < 0x24) {
                 if (gen_trap_ifnofpu(dc))
                     goto jmp_insn;
-		switch (xop) {
-		case 0x20:	/* load fpreg */
+                switch (xop) {
+                case 0x20:      /* load fpreg */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldst(ldf);
-		    gen_op_store_FT0_fpr(rd);
-		    break;
-		case 0x21:	/* load fsr */
+                    gen_op_ldst(ldf);
+                    gen_op_store_FT0_fpr(rd);
+                    break;
+                case 0x21:      /* load fsr */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldst(ldf);
-		    gen_op_ldfsr();
-		    break;
-		case 0x22:      /* load quad fpreg */
-		    goto nfpu_insn;
-		case 0x23:	/* load double fpreg */
+                    gen_op_ldst(ldf);
+                    gen_op_ldfsr();
+                    break;
+                case 0x22:      /* load quad fpreg */
+                    goto nfpu_insn;
+                case 0x23:      /* load double fpreg */
                     gen_op_check_align_T0_7();
-		    gen_op_ldst(lddf);
-		    gen_op_store_DT0_fpr(DFPREG(rd));
-		    break;
-		default:
-		    goto illegal_insn;
-		}
-	    } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
-		       xop == 0xe || xop == 0x1e) {
-		gen_movl_reg_T1(rd);
-		switch (xop) {
-		case 0x4:
+                    gen_op_ldst(lddf);
+                    gen_op_store_DT0_fpr(DFPREG(rd));
+                    break;
+                default:
+                    goto illegal_insn;
+                }
+            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
+                       xop == 0xe || xop == 0x1e) {
+                gen_movl_reg_T1(rd);
+                switch (xop) {
+                case 0x4:
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_ldst(st);
-		    break;
-		case 0x5:
-		    gen_op_ldst(stb);
-		    break;
-		case 0x6:
+                    gen_op_ldst(st);
+                    break;
+                case 0x5:
+                    gen_op_ldst(stb);
+                    break;
+                case 0x6:
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_ldst(sth);
-		    break;
-		case 0x7:
-		    if (rd & 1)
+                    gen_op_ldst(sth);
+                    break;
+                case 0x7:
+                    if (rd & 1)
                         goto illegal_insn;
                     gen_op_check_align_T0_7();
                     flush_T2(dc);
-		    gen_movl_reg_T2(rd + 1);
-		    gen_op_ldst(std);
-		    break;
+                    gen_movl_reg_T2(rd + 1);
+                    gen_op_ldst(std);
+                    break;
 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-		case 0x14:
+                case 0x14:
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_sta(insn, 0, 4, 0);
+                    gen_op_sta(insn, 0, 4, 0);
                     break;
-		case 0x15:
+                case 0x15:
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
-		    gen_op_stba(insn, 0, 1, 0);
+                    gen_op_stba(insn, 0, 1, 0);
                     break;
-		case 0x16:
+                case 0x16:
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
 #endif
-		    gen_op_stha(insn, 0, 2, 0);
+                    gen_op_stha(insn, 0, 2, 0);
                     break;
-		case 0x17:
+                case 0x17:
 #ifndef TARGET_SPARC64
-		    if (IS_IMM)
-			goto illegal_insn;
-		    if (!supervisor(dc))
-			goto priv_insn;
+                    if (IS_IMM)
+                        goto illegal_insn;
+                    if (!supervisor(dc))
+                        goto priv_insn;
 #endif
-		    if (rd & 1)
+                    if (rd & 1)
                         goto illegal_insn;
                     gen_op_check_align_T0_7();
                     flush_T2(dc);
-		    gen_movl_reg_T2(rd + 1);
-		    gen_op_stda(insn, 0, 8, 0);
+                    gen_movl_reg_T2(rd + 1);
+                    gen_op_stda(insn, 0, 8, 0);
                     break;
 #endif
 #ifdef TARGET_SPARC64
-		case 0x0e: /* V9 stx */
+                case 0x0e: /* V9 stx */
                     gen_op_check_align_T0_7();
-		    gen_op_ldst(stx);
-		    break;
-		case 0x1e: /* V9 stxa */
+                    gen_op_ldst(stx);
+                    break;
+                case 0x1e: /* V9 stxa */
                     gen_op_check_align_T0_7();
-		    gen_op_stxa(insn, 0, 8, 0); // XXX
-		    break;
+                    gen_op_stxa(insn, 0, 8, 0); // XXX
+                    break;
 #endif
-		default:
-		    goto illegal_insn;
-		}
-	    } else if (xop > 0x23 && xop < 0x28) {
+                default:
+                    goto illegal_insn;
+                }
+            } else if (xop > 0x23 && xop < 0x28) {
                 if (gen_trap_ifnofpu(dc))
                     goto jmp_insn;
-		switch (xop) {
-		case 0x24:
+                switch (xop) {
+                case 0x24:
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
                     gen_op_load_fpr_FT0(rd);
-		    gen_op_ldst(stf);
-		    break;
-		case 0x25: /* stfsr, V9 stxfsr */
+                    gen_op_ldst(stf);
+                    break;
+                case 0x25: /* stfsr, V9 stxfsr */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_stfsr();
-		    gen_op_ldst(stf);
-		    break;
+                    gen_op_stfsr();
+                    gen_op_ldst(stf);
+                    break;
 #if !defined(CONFIG_USER_ONLY)
-		case 0x26: /* stdfq */
-		    if (!supervisor(dc))
-			goto priv_insn;
-		    if (gen_trap_ifnofpu(dc))
-			goto jmp_insn;
-		    goto nfq_insn;
-#endif
-		case 0x27:
+                case 0x26: /* stdfq */
+                    if (!supervisor(dc))
+                        goto priv_insn;
+                    if (gen_trap_ifnofpu(dc))
+                        goto jmp_insn;
+                    goto nfq_insn;
+#endif
+                case 0x27:
                     gen_op_check_align_T0_7();
                     gen_op_load_fpr_DT0(DFPREG(rd));
-		    gen_op_ldst(stdf);
-		    break;
-		default:
-		    goto illegal_insn;
-		}
-	    } else if (xop > 0x33 && xop < 0x3f) {
-		switch (xop) {
+                    gen_op_ldst(stdf);
+                    break;
+                default:
+                    goto illegal_insn;
+                }
+            } else if (xop > 0x33 && xop < 0x3f) {
+                switch (xop) {
 #ifdef TARGET_SPARC64
-		case 0x34: /* V9 stfa */
+                case 0x34: /* V9 stfa */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_stfa(insn, 0, 0, 0); // XXX
-		    break;
-		case 0x37: /* V9 stdfa */
+                    gen_op_stfa(insn, 0, 0, 0); // XXX
+                    break;
+                case 0x37: /* V9 stdfa */
                     gen_op_check_align_T0_7();
-		    gen_op_stdfa(insn, 0, 0, 0); // XXX
-		    break;
-		case 0x3c: /* V9 casa */
+                    gen_op_stdfa(insn, 0, 0, 0); // XXX
+                    break;
+                case 0x3c: /* V9 casa */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-		    gen_op_casa(insn, 0, 4, 0); // XXX
-		    break;
-		case 0x3e: /* V9 casxa */
+                    gen_op_casa(insn, 0, 4, 0); // XXX
+                    break;
+                case 0x3e: /* V9 casxa */
                     gen_op_check_align_T0_7();
-		    gen_op_casxa(insn, 0, 8, 0); // XXX
-		    break;
-		case 0x36: /* V9 stqfa */
-		    goto nfpu_insn;
+                    gen_op_casxa(insn, 0, 8, 0); // XXX
+                    break;
+                case 0x36: /* V9 stqfa */
+                    goto nfpu_insn;
 #else
-		case 0x34: /* stc */
-		case 0x35: /* stcsr */
-		case 0x36: /* stdcq */
-		case 0x37: /* stdc */
-		    goto ncp_insn;
-#endif
-		default:
-		    goto illegal_insn;
-		}
+                case 0x34: /* stc */
+                case 0x35: /* stcsr */
+                case 0x36: /* stdcq */
+                case 0x37: /* stdc */
+                    goto ncp_insn;
+#endif
+                default:
+                    goto illegal_insn;
+                }
             }
-	    else
-		goto illegal_insn;
-	}
-	break;
+            else
+                goto illegal_insn;
+        }
+        break;
     }
     /* default case for non jump instructions */
     if (dc->npc == DYNAMIC_PC) {
-	dc->pc = DYNAMIC_PC;
-	gen_op_next_insn();
+        dc->pc = DYNAMIC_PC;
+        gen_op_next_insn();
     } else if (dc->npc == JUMP_PC) {
         /* we can do a static jump */
         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
         dc->is_br = 1;
     } else {
-	dc->pc = dc->npc;
-	dc->npc = dc->npc + 4;
+        dc->pc = dc->npc;
+        dc->npc = dc->npc + 4;
     }
  jmp_insn:
     return;
@@ -3266,7 +3266,7 @@ static void disas_sparc_insn(DisasContext * dc)
 }
 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
-						 int spc, CPUSPARCState *env)
+                                                 int spc, CPUSPARCState *env)
 {
     target_ulong pc_start, last_pc;
     uint16_t *gen_opc_end;
@@ -3299,12 +3299,12 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
         if (env->nb_breakpoints > 0) {
             for(j = 0; j < env->nb_breakpoints; j++) {
                 if (env->breakpoints[j] == dc->pc) {
-		    if (dc->pc != pc_start)
-			save_state(dc);
+                    if (dc->pc != pc_start)
+                        save_state(dc);
                     gen_op_debug();
-		    gen_op_movl_T0_0();
-		    gen_op_exit_tb();
-		    dc->is_br = 1;
+                    gen_op_movl_T0_0();
+                    gen_op_exit_tb();
+                    dc->is_br = 1;
                     goto exit_gen_loop;
                 }
             }
@@ -3322,14 +3322,14 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
                 gen_opc_instr_start[lj] = 1;
             }
         }
-	last_pc = dc->pc;
-	disas_sparc_insn(dc);
-
-	if (dc->is_br)
-	    break;
-	/* if the next PC is different, we abort now */
-	if (dc->pc != (last_pc + 4))
-	    break;
+        last_pc = dc->pc;
+        disas_sparc_insn(dc);
+
+        if (dc->is_br)
+            break;
+        /* if the next PC is different, we abort now */
+        if (dc->pc != (last_pc + 4))
+            break;
         /* if we reach a page boundary, we stop generation so that the
            PC of a TT_TFAULT exception is always in the right page */
         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
@@ -3343,7 +3343,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
             break;
         }
     } while ((gen_opc_ptr < gen_opc_end) &&
-	     (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
+             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
  exit_gen_loop:
     if (!dc->is_br) {
@@ -3377,10 +3377,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
     }
 #ifdef DEBUG_DISAS
     if (loglevel & CPU_LOG_TB_IN_ASM) {
-	fprintf(logfile, "--------------\n");
-	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
-	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
-	fprintf(logfile, "\n");
+        fprintf(logfile, "--------------\n");
+        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
+        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
+        fprintf(logfile, "\n");
         if (loglevel & CPU_LOG_TB_OP) {
             fprintf(logfile, "OP:\n");
             dump_ops(gen_opc_buf, gen_opparam_buf);
@@ -3438,7 +3438,7 @@ CPUSPARCState *cpu_sparc_init(void)
     env = qemu_mallocz(sizeof(CPUSPARCState));
     if (!env)
-	return NULL;
+        return NULL;
     cpu_exec_init(env);
     cpu_reset(env);
     return (env);
@@ -3539,22 +3539,22 @@ void cpu_dump_state(CPUState *env, FILE *f,
     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
     cpu_fprintf(f, "General Registers:\n");
     for (i = 0; i < 4; i++)
-	cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
     cpu_fprintf(f, "\n");
     for (; i < 8; i++)
-	cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
     cpu_fprintf(f, "\nCurrent Register Window:\n");
     for (x = 0; x < 3; x++) {
-	for (i = 0; i < 4; i++)
-	    cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
-		    (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
-		    env->regwptr[i + x * 8]);
-	cpu_fprintf(f, "\n");
-	for (; i < 8; i++)
-	    cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
-		    (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
-		    env->regwptr[i + x * 8]);
-	cpu_fprintf(f, "\n");
+        for (i = 0; i < 4; i++)
+            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+                    (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
+                    env->regwptr[i + x * 8]);
+        cpu_fprintf(f, "\n");
+        for (; i < 8; i++)
+            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+                    (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
+                    env->regwptr[i + x * 8]);
+        cpu_fprintf(f, "\n");
     }
     cpu_fprintf(f, "\nFloating Point Registers:\n");
     for (i = 0; i < 32; i++) {
@@ -3566,16 +3566,16 @@ void cpu_dump_state(CPUState *env, FILE *f,
     }
 #ifdef TARGET_SPARC64
     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
-		env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
+                env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
-		env->cansave, env->canrestore, env->otherwin, env->wstate,
-		env->cleanwin, NWINDOWS - 1 - env->cwp);
+                env->cansave, env->canrestore, env->otherwin, env->wstate,
+                env->cleanwin, NWINDOWS - 1 - env->cwp);
 #else
     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
-	    GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
-	    GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
-	    env->psrs?'S':'-', env->psrps?'P':'-',
-	    env->psret?'E':'-', env->wim);
+            GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
+            GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
+            env->psrs?'S':'-', env->psrps?'P':'-',
+            env->psret?'E':'-', env->wim);
 #endif
     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
 }