gwj / at91sam9263 · Commits

Commit 0f2f39c234a33d3ded4365182b4794b51c0d92a2

Authored by aurel32
1 parent 34fc643f

target-ppc: fix TCG type errors introduced in r5754 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5756 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 16 additions and 15 deletions
target-ppc/translate.c
  View file @0f2f39c
... ... @@ -243,31 +243,31 @@ static always_inline void gen_reset_fpstatus (void)
243 243 #endif
244 244 }
245 245  
246   -static always_inline void gen_compute_fprf (TCGv arg, int set_fprf, int set_rc)
  246 +static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
247 247 {
248   - TCGv t0 = tcg_temp_new_i32();
  248 + TCGv_i32 t0 = tcg_temp_new_i32();
249 249  
250 250 if (set_fprf != 0) {
251 251 /* This case might be optimized later */
252 252 #if defined(OPTIMIZE_FPRF_UPDATE)
253 253 *gen_fprf_ptr++ = gen_opc_ptr;
254 254 #endif
255   - tcg_gen_movi_tl(t0, 1);
  255 + tcg_gen_movi_i32(t0, 1);
256 256 gen_helper_compute_fprf(t0, arg, t0);
257 257 if (unlikely(set_rc)) {
258   - tcg_gen_movi_i32(cpu_crf[1], t0);
  258 + tcg_gen_mov_i32(cpu_crf[1], t0);
259 259 }
260 260 gen_helper_float_check_status();
261 261 } else if (unlikely(set_rc)) {
262 262 /* We always need to compute fpcc */
263   - tcg_gen_movi_tl(t0, 0);
  263 + tcg_gen_movi_i32(t0, 0);
264 264 gen_helper_compute_fprf(t0, arg, t0);
265   - tcg_gen_movi_i32(cpu_crf[1], t0);
  265 + tcg_gen_mov_i32(cpu_crf[1], t0);
266 266 if (set_fprf)
267 267 gen_helper_float_check_status();
268 268 }
269 269  
270   - tcg_temp_free(t0);
  270 + tcg_temp_free_i32(t0);
271 271 }
272 272  
273 273 static always_inline void gen_optimize_fprf (void)
... ... @@ -2385,9 +2385,9 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2385 2385 gen_reset_fpstatus();
2386 2386 /* XXX: we pretend we can only do IEEE floating-point computations */
2387 2387 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2388   - TCGv t0 = tcg_const_tl(crb);
  2388 + TCGv_i32 t0 = tcg_const_i32(crb);
2389 2389 gen_helper_fpscr_setbit(t0);
2390   - tcg_temp_free(t0);
  2390 + tcg_temp_free_i32(t0);
2391 2391 }
2392 2392 if (unlikely(Rc(ctx->opcode) != 0)) {
2393 2393 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
... ... @@ -2399,7 +2399,7 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2399 2399 /* mtfsf */
2400 2400 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2401 2401 {
2402   - TCGv t0;
  2402 + TCGv_i32 t0;
2403 2403  
2404 2404 if (unlikely(!ctx->fpu_enabled)) {
2405 2405 GEN_EXCP_NO_FP(ctx);
... ... @@ -2409,7 +2409,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2409 2409 gen_reset_fpstatus();
2410 2410 t0 = tcg_const_i32(FM(ctx->opcode));
2411 2411 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2412   - tcg_temp_free(t0);
  2412 + tcg_temp_free_i32(t0);
2413 2413 if (unlikely(Rc(ctx->opcode) != 0)) {
2414 2414 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2415 2415 }
... ... @@ -2421,7 +2421,8 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2421 2421 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2422 2422 {
2423 2423 int bf, sh;
2424   - TCGv t0, t1;
  2424 + TCGv_i64 t0;
  2425 + TCGv_i32 t1;
2425 2426  
2426 2427 if (unlikely(!ctx->fpu_enabled)) {
2427 2428 GEN_EXCP_NO_FP(ctx);
... ... @@ -2431,11 +2432,11 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2431 2432 sh = 7 - bf;
2432 2433 gen_optimize_fprf();
2433 2434 gen_reset_fpstatus();
2434   - t0 = tcg_const_tl(FPIMM(ctx->opcode) << (4 * sh));
  2435 + t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2435 2436 t1 = tcg_const_i32(1 << sh);
2436 2437 gen_helper_store_fpscr(t0, t1);
2437   - tcg_temp_free(t0);
2438   - tcg_temp_free(t1);
  2438 + tcg_temp_free_i64(t0);
  2439 + tcg_temp_free_i32(t1);
2439 2440 if (unlikely(Rc(ctx->opcode) != 0)) {
2440 2441 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2441 2442 }
... ...