Commit 0ec3ff526ff8410f1a8e0cc3bc0f11c7e4d0e90a
1 parent
6391e47e
sh4: r2d. Endian conversion for peripheral register initialization.
Add endian conversion to hw/r2d.c which lacks consideration of endian on setting BSC registers. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6431 c046a42c-6fe2-441c-8c8c-71466251a162
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hw/r2d.c
| @@ -238,10 +238,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size, | @@ -238,10 +238,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size, | ||
| 238 | { | 238 | { |
| 239 | int kernel_size; | 239 | int kernel_size; |
| 240 | /* initialization which should be done by firmware */ | 240 | /* initialization which should be done by firmware */ |
| 241 | - uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */ | ||
| 242 | - uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */ | ||
| 243 | - cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4); | ||
| 244 | - cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2); | 241 | + stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ |
| 242 | + stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ | ||
| 245 | 243 | ||
| 246 | kernel_size = load_image(kernel_filename, phys_ram_base); | 244 | kernel_size = load_image(kernel_filename, phys_ram_base); |
| 247 | 245 |