gwj / at91sam9263 · Commits

Commit 0ea00c9a3c5e69ca30007f982fb7f2163ab8116c

Authored by bellard
1 parent e1d4294a

added number of arguments 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@52 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 642 additions and 538 deletions
dyngen.c
  View file @0ea00c9
... ... @@ -282,7 +282,9 @@ void gen_code(const char *name, unsigned long offset, unsigned long size,
282 282 error("inconsistent argument numbering in %s", name);
283 283 }
284 284  
285   - if (gen_switch) {
  285 + if (gen_switch == 2) {
  286 + fprintf(outfile, "DEF(%s, %d)\n", name + 3, nb_args);
  287 + } else if (gen_switch == 1) {
286 288  
287 289 /* output C code */
288 290 fprintf(outfile, "case INDEX_%s: {\n", name);
... ... @@ -559,12 +561,13 @@ int load_elf(const char *filename, FILE *outfile, int do_print_enum)
559 561 }
560 562  
561 563 if (do_print_enum) {
562   - fprintf(outfile, "DEF(end)\n");
  564 + fprintf(outfile, "DEF(end, 0)\n");
563 565 for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {
564 566 const char *name, *p;
565 567 name = strtab + sym->st_name;
566 568 if (strstart(name, OP_PREFIX, &p)) {
567   - fprintf(outfile, "DEF(%s)\n", p);
  569 + gen_code(name, sym->st_value, sym->st_size, outfile,
  570 + text, relocs, nb_relocs, reloc_sh_type, symtab, strtab, 2);
568 571 }
569 572 }
570 573 } else {
... ...
opc-i386.h
  View file @0ea00c9
1   -DEF(end)
2   -DEF(movl_A0_EAX)
3   -DEF(addl_A0_EAX)
4   -DEF(addl_A0_EAX_s1)
5   -DEF(addl_A0_EAX_s2)
6   -DEF(addl_A0_EAX_s3)
7   -DEF(movl_T0_EAX)
8   -DEF(movl_T1_EAX)
9   -DEF(movh_T0_EAX)
10   -DEF(movh_T1_EAX)
11   -DEF(movl_EAX_T0)
12   -DEF(movl_EAX_T1)
13   -DEF(movl_EAX_A0)
14   -DEF(cmovw_EAX_T1_T0)
15   -DEF(cmovl_EAX_T1_T0)
16   -DEF(movw_EAX_T0)
17   -DEF(movw_EAX_T1)
18   -DEF(movw_EAX_A0)
19   -DEF(movb_EAX_T0)
20   -DEF(movh_EAX_T0)
21   -DEF(movb_EAX_T1)
22   -DEF(movh_EAX_T1)
23   -DEF(movl_A0_ECX)
24   -DEF(addl_A0_ECX)
25   -DEF(addl_A0_ECX_s1)
26   -DEF(addl_A0_ECX_s2)
27   -DEF(addl_A0_ECX_s3)
28   -DEF(movl_T0_ECX)
29   -DEF(movl_T1_ECX)
30   -DEF(movh_T0_ECX)
31   -DEF(movh_T1_ECX)
32   -DEF(movl_ECX_T0)
33   -DEF(movl_ECX_T1)
34   -DEF(movl_ECX_A0)
35   -DEF(cmovw_ECX_T1_T0)
36   -DEF(cmovl_ECX_T1_T0)
37   -DEF(movw_ECX_T0)
38   -DEF(movw_ECX_T1)
39   -DEF(movw_ECX_A0)
40   -DEF(movb_ECX_T0)
41   -DEF(movh_ECX_T0)
42   -DEF(movb_ECX_T1)
43   -DEF(movh_ECX_T1)
44   -DEF(movl_A0_EDX)
45   -DEF(addl_A0_EDX)
46   -DEF(addl_A0_EDX_s1)
47   -DEF(addl_A0_EDX_s2)
48   -DEF(addl_A0_EDX_s3)
49   -DEF(movl_T0_EDX)
50   -DEF(movl_T1_EDX)
51   -DEF(movh_T0_EDX)
52   -DEF(movh_T1_EDX)
53   -DEF(movl_EDX_T0)
54   -DEF(movl_EDX_T1)
55   -DEF(movl_EDX_A0)
56   -DEF(cmovw_EDX_T1_T0)
57   -DEF(cmovl_EDX_T1_T0)
58   -DEF(movw_EDX_T0)
59   -DEF(movw_EDX_T1)
60   -DEF(movw_EDX_A0)
61   -DEF(movb_EDX_T0)
62   -DEF(movh_EDX_T0)
63   -DEF(movb_EDX_T1)
64   -DEF(movh_EDX_T1)
65   -DEF(movl_A0_EBX)
66   -DEF(addl_A0_EBX)
67   -DEF(addl_A0_EBX_s1)
68   -DEF(addl_A0_EBX_s2)
69   -DEF(addl_A0_EBX_s3)
70   -DEF(movl_T0_EBX)
71   -DEF(movl_T1_EBX)
72   -DEF(movh_T0_EBX)
73   -DEF(movh_T1_EBX)
74   -DEF(movl_EBX_T0)
75   -DEF(movl_EBX_T1)
76   -DEF(movl_EBX_A0)
77   -DEF(cmovw_EBX_T1_T0)
78   -DEF(cmovl_EBX_T1_T0)
79   -DEF(movw_EBX_T0)
80   -DEF(movw_EBX_T1)
81   -DEF(movw_EBX_A0)
82   -DEF(movb_EBX_T0)
83   -DEF(movh_EBX_T0)
84   -DEF(movb_EBX_T1)
85   -DEF(movh_EBX_T1)
86   -DEF(movl_A0_ESP)
87   -DEF(addl_A0_ESP)
88   -DEF(addl_A0_ESP_s1)
89   -DEF(addl_A0_ESP_s2)
90   -DEF(addl_A0_ESP_s3)
91   -DEF(movl_T0_ESP)
92   -DEF(movl_T1_ESP)
93   -DEF(movh_T0_ESP)
94   -DEF(movh_T1_ESP)
95   -DEF(movl_ESP_T0)
96   -DEF(movl_ESP_T1)
97   -DEF(movl_ESP_A0)
98   -DEF(cmovw_ESP_T1_T0)
99   -DEF(cmovl_ESP_T1_T0)
100   -DEF(movw_ESP_T0)
101   -DEF(movw_ESP_T1)
102   -DEF(movw_ESP_A0)
103   -DEF(movb_ESP_T0)
104   -DEF(movh_ESP_T0)
105   -DEF(movb_ESP_T1)
106   -DEF(movh_ESP_T1)
107   -DEF(movl_A0_EBP)
108   -DEF(addl_A0_EBP)
109   -DEF(addl_A0_EBP_s1)
110   -DEF(addl_A0_EBP_s2)
111   -DEF(addl_A0_EBP_s3)
112   -DEF(movl_T0_EBP)
113   -DEF(movl_T1_EBP)
114   -DEF(movh_T0_EBP)
115   -DEF(movh_T1_EBP)
116   -DEF(movl_EBP_T0)
117   -DEF(movl_EBP_T1)
118   -DEF(movl_EBP_A0)
119   -DEF(cmovw_EBP_T1_T0)
120   -DEF(cmovl_EBP_T1_T0)
121   -DEF(movw_EBP_T0)
122   -DEF(movw_EBP_T1)
123   -DEF(movw_EBP_A0)
124   -DEF(movb_EBP_T0)
125   -DEF(movh_EBP_T0)
126   -DEF(movb_EBP_T1)
127   -DEF(movh_EBP_T1)
128   -DEF(movl_A0_ESI)
129   -DEF(addl_A0_ESI)
130   -DEF(addl_A0_ESI_s1)
131   -DEF(addl_A0_ESI_s2)
132   -DEF(addl_A0_ESI_s3)
133   -DEF(movl_T0_ESI)
134   -DEF(movl_T1_ESI)
135   -DEF(movh_T0_ESI)
136   -DEF(movh_T1_ESI)
137   -DEF(movl_ESI_T0)
138   -DEF(movl_ESI_T1)
139   -DEF(movl_ESI_A0)
140   -DEF(cmovw_ESI_T1_T0)
141   -DEF(cmovl_ESI_T1_T0)
142   -DEF(movw_ESI_T0)
143   -DEF(movw_ESI_T1)
144   -DEF(movw_ESI_A0)
145   -DEF(movb_ESI_T0)
146   -DEF(movh_ESI_T0)
147   -DEF(movb_ESI_T1)
148   -DEF(movh_ESI_T1)
149   -DEF(movl_A0_EDI)
150   -DEF(addl_A0_EDI)
151   -DEF(addl_A0_EDI_s1)
152   -DEF(addl_A0_EDI_s2)
153   -DEF(addl_A0_EDI_s3)
154   -DEF(movl_T0_EDI)
155   -DEF(movl_T1_EDI)
156   -DEF(movh_T0_EDI)
157   -DEF(movh_T1_EDI)
158   -DEF(movl_EDI_T0)
159   -DEF(movl_EDI_T1)
160   -DEF(movl_EDI_A0)
161   -DEF(cmovw_EDI_T1_T0)
162   -DEF(cmovl_EDI_T1_T0)
163   -DEF(movw_EDI_T0)
164   -DEF(movw_EDI_T1)
165   -DEF(movw_EDI_A0)
166   -DEF(movb_EDI_T0)
167   -DEF(movh_EDI_T0)
168   -DEF(movb_EDI_T1)
169   -DEF(movh_EDI_T1)
170   -DEF(addl_T0_T1_cc)
171   -DEF(orl_T0_T1_cc)
172   -DEF(andl_T0_T1_cc)
173   -DEF(subl_T0_T1_cc)
174   -DEF(xorl_T0_T1_cc)
175   -DEF(cmpl_T0_T1_cc)
176   -DEF(negl_T0_cc)
177   -DEF(incl_T0_cc)
178   -DEF(decl_T0_cc)
179   -DEF(testl_T0_T1_cc)
180   -DEF(addl_T0_T1)
181   -DEF(orl_T0_T1)
182   -DEF(andl_T0_T1)
183   -DEF(subl_T0_T1)
184   -DEF(xorl_T0_T1)
185   -DEF(negl_T0)
186   -DEF(incl_T0)
187   -DEF(decl_T0)
188   -DEF(notl_T0)
189   -DEF(bswapl_T0)
190   -DEF(mulb_AL_T0)
191   -DEF(imulb_AL_T0)
192   -DEF(mulw_AX_T0)
193   -DEF(imulw_AX_T0)
194   -DEF(mull_EAX_T0)
195   -DEF(imull_EAX_T0)
196   -DEF(imulw_T0_T1)
197   -DEF(imull_T0_T1)
198   -DEF(divb_AL_T0)
199   -DEF(idivb_AL_T0)
200   -DEF(divw_AX_T0)
201   -DEF(idivw_AX_T0)
202   -DEF(divl_EAX_T0)
203   -DEF(idivl_EAX_T0)
204   -DEF(movl_T0_im)
205   -DEF(addl_T0_im)
206   -DEF(andl_T0_ffff)
207   -DEF(movl_T0_T1)
208   -DEF(movl_T1_im)
209   -DEF(addl_T1_im)
210   -DEF(movl_T1_A0)
211   -DEF(movl_A0_im)
212   -DEF(addl_A0_im)
213   -DEF(addl_A0_AL)
214   -DEF(andl_A0_ffff)
215   -DEF(ldub_T0_A0)
216   -DEF(ldsb_T0_A0)
217   -DEF(lduw_T0_A0)
218   -DEF(ldsw_T0_A0)
219   -DEF(ldl_T0_A0)
220   -DEF(ldub_T1_A0)
221   -DEF(ldsb_T1_A0)
222   -DEF(lduw_T1_A0)
223   -DEF(ldsw_T1_A0)
224   -DEF(ldl_T1_A0)
225   -DEF(stb_T0_A0)
226   -DEF(stw_T0_A0)
227   -DEF(stl_T0_A0)
228   -DEF(add_bitw_A0_T1)
229   -DEF(add_bitl_A0_T1)
230   -DEF(jmp_T0)
231   -DEF(jmp_im)
232   -DEF(int_im)
233   -DEF(int3)
234   -DEF(into)
235   -DEF(jb_subb)
236   -DEF(jz_subb)
237   -DEF(jbe_subb)
238   -DEF(js_subb)
239   -DEF(jl_subb)
240   -DEF(jle_subb)
241   -DEF(setb_T0_subb)
242   -DEF(setz_T0_subb)
243   -DEF(setbe_T0_subb)
244   -DEF(sets_T0_subb)
245   -DEF(setl_T0_subb)
246   -DEF(setle_T0_subb)
247   -DEF(rolb_T0_T1_cc)
248   -DEF(rolb_T0_T1)
249   -DEF(rorb_T0_T1_cc)
250   -DEF(rorb_T0_T1)
251   -DEF(rclb_T0_T1_cc)
252   -DEF(rcrb_T0_T1_cc)
253   -DEF(shlb_T0_T1_cc)
254   -DEF(shlb_T0_T1)
255   -DEF(shrb_T0_T1_cc)
256   -DEF(shrb_T0_T1)
257   -DEF(sarb_T0_T1_cc)
258   -DEF(sarb_T0_T1)
259   -DEF(adcb_T0_T1_cc)
260   -DEF(sbbb_T0_T1_cc)
261   -DEF(cmpxchgb_T0_T1_EAX_cc)
262   -DEF(movsb)
263   -DEF(rep_movsb)
264   -DEF(stosb)
265   -DEF(rep_stosb)
266   -DEF(lodsb)
267   -DEF(rep_lodsb)
268   -DEF(scasb)
269   -DEF(repz_scasb)
270   -DEF(repnz_scasb)
271   -DEF(cmpsb)
272   -DEF(repz_cmpsb)
273   -DEF(repnz_cmpsb)
274   -DEF(outsb)
275   -DEF(rep_outsb)
276   -DEF(insb)
277   -DEF(rep_insb)
278   -DEF(outb_T0_T1)
279   -DEF(inb_T0_T1)
280   -DEF(jb_subw)
281   -DEF(jz_subw)
282   -DEF(jbe_subw)
283   -DEF(js_subw)
284   -DEF(jl_subw)
285   -DEF(jle_subw)
286   -DEF(loopnzw)
287   -DEF(loopzw)
288   -DEF(loopw)
289   -DEF(jecxzw)
290   -DEF(setb_T0_subw)
291   -DEF(setz_T0_subw)
292   -DEF(setbe_T0_subw)
293   -DEF(sets_T0_subw)
294   -DEF(setl_T0_subw)
295   -DEF(setle_T0_subw)
296   -DEF(rolw_T0_T1_cc)
297   -DEF(rolw_T0_T1)
298   -DEF(rorw_T0_T1_cc)
299   -DEF(rorw_T0_T1)
300   -DEF(rclw_T0_T1_cc)
301   -DEF(rcrw_T0_T1_cc)
302   -DEF(shlw_T0_T1_cc)
303   -DEF(shlw_T0_T1)
304   -DEF(shrw_T0_T1_cc)
305   -DEF(shrw_T0_T1)
306   -DEF(sarw_T0_T1_cc)
307   -DEF(sarw_T0_T1)
308   -DEF(shldw_T0_T1_im_cc)
309   -DEF(shldw_T0_T1_ECX_cc)
310   -DEF(shrdw_T0_T1_im_cc)
311   -DEF(shrdw_T0_T1_ECX_cc)
312   -DEF(adcw_T0_T1_cc)
313   -DEF(sbbw_T0_T1_cc)
314   -DEF(cmpxchgw_T0_T1_EAX_cc)
315   -DEF(btw_T0_T1_cc)
316   -DEF(btsw_T0_T1_cc)
317   -DEF(btrw_T0_T1_cc)
318   -DEF(btcw_T0_T1_cc)
319   -DEF(bsfw_T0_cc)
320   -DEF(bsrw_T0_cc)
321   -DEF(movsw)
322   -DEF(rep_movsw)
323   -DEF(stosw)
324   -DEF(rep_stosw)
325   -DEF(lodsw)
326   -DEF(rep_lodsw)
327   -DEF(scasw)
328   -DEF(repz_scasw)
329   -DEF(repnz_scasw)
330   -DEF(cmpsw)
331   -DEF(repz_cmpsw)
332   -DEF(repnz_cmpsw)
333   -DEF(outsw)
334   -DEF(rep_outsw)
335   -DEF(insw)
336   -DEF(rep_insw)
337   -DEF(outw_T0_T1)
338   -DEF(inw_T0_T1)
339   -DEF(jb_subl)
340   -DEF(jz_subl)
341   -DEF(jbe_subl)
342   -DEF(js_subl)
343   -DEF(jl_subl)
344   -DEF(jle_subl)
345   -DEF(loopnzl)
346   -DEF(loopzl)
347   -DEF(loopl)
348   -DEF(jecxzl)
349   -DEF(setb_T0_subl)
350   -DEF(setz_T0_subl)
351   -DEF(setbe_T0_subl)
352   -DEF(sets_T0_subl)
353   -DEF(setl_T0_subl)
354   -DEF(setle_T0_subl)
355   -DEF(roll_T0_T1_cc)
356   -DEF(roll_T0_T1)
357   -DEF(rorl_T0_T1_cc)
358   -DEF(rorl_T0_T1)
359   -DEF(rcll_T0_T1_cc)
360   -DEF(rcrl_T0_T1_cc)
361   -DEF(shll_T0_T1_cc)
362   -DEF(shll_T0_T1)
363   -DEF(shrl_T0_T1_cc)
364   -DEF(shrl_T0_T1)
365   -DEF(sarl_T0_T1_cc)
366   -DEF(sarl_T0_T1)
367   -DEF(shldl_T0_T1_im_cc)
368   -DEF(shldl_T0_T1_ECX_cc)
369   -DEF(shrdl_T0_T1_im_cc)
370   -DEF(shrdl_T0_T1_ECX_cc)
371   -DEF(adcl_T0_T1_cc)
372   -DEF(sbbl_T0_T1_cc)
373   -DEF(cmpxchgl_T0_T1_EAX_cc)
374   -DEF(btl_T0_T1_cc)
375   -DEF(btsl_T0_T1_cc)
376   -DEF(btrl_T0_T1_cc)
377   -DEF(btcl_T0_T1_cc)
378   -DEF(bsfl_T0_cc)
379   -DEF(bsrl_T0_cc)
380   -DEF(movsl)
381   -DEF(rep_movsl)
382   -DEF(stosl)
383   -DEF(rep_stosl)
384   -DEF(lodsl)
385   -DEF(rep_lodsl)
386   -DEF(scasl)
387   -DEF(repz_scasl)
388   -DEF(repnz_scasl)
389   -DEF(cmpsl)
390   -DEF(repz_cmpsl)
391   -DEF(repnz_cmpsl)
392   -DEF(outsl)
393   -DEF(rep_outsl)
394   -DEF(insl)
395   -DEF(rep_insl)
396   -DEF(outl_T0_T1)
397   -DEF(inl_T0_T1)
398   -DEF(movsbl_T0_T0)
399   -DEF(movzbl_T0_T0)
400   -DEF(movswl_T0_T0)
401   -DEF(movzwl_T0_T0)
402   -DEF(movswl_EAX_AX)
403   -DEF(movsbw_AX_AL)
404   -DEF(movslq_EDX_EAX)
405   -DEF(movswl_DX_AX)
406   -DEF(pushl_T0)
407   -DEF(pushw_T0)
408   -DEF(pushl_ss32_T0)
409   -DEF(pushw_ss32_T0)
410   -DEF(pushl_ss16_T0)
411   -DEF(pushw_ss16_T0)
412   -DEF(popl_T0)
413   -DEF(popw_T0)
414   -DEF(popl_ss32_T0)
415   -DEF(popw_ss32_T0)
416   -DEF(popl_ss16_T0)
417   -DEF(popw_ss16_T0)
418   -DEF(addl_ESP_4)
419   -DEF(addl_ESP_2)
420   -DEF(addw_ESP_4)
421   -DEF(addw_ESP_2)
422   -DEF(addl_ESP_im)
423   -DEF(addw_ESP_im)
424   -DEF(rdtsc)
425   -DEF(aam)
426   -DEF(aad)
427   -DEF(aaa)
428   -DEF(aas)
429   -DEF(daa)
430   -DEF(das)
431   -DEF(movl_seg_T0)
432   -DEF(movl_T0_seg)
433   -DEF(addl_A0_seg)
434   -DEF(jo_cc)
435   -DEF(jb_cc)
436   -DEF(jz_cc)
437   -DEF(jbe_cc)
438   -DEF(js_cc)
439   -DEF(jp_cc)
440   -DEF(jl_cc)
441   -DEF(jle_cc)
442   -DEF(seto_T0_cc)
443   -DEF(setb_T0_cc)
444   -DEF(setz_T0_cc)
445   -DEF(setbe_T0_cc)
446   -DEF(sets_T0_cc)
447   -DEF(setp_T0_cc)
448   -DEF(setl_T0_cc)
449   -DEF(setle_T0_cc)
450   -DEF(xor_T0_1)
451   -DEF(set_cc_op)
452   -DEF(movl_eflags_T0)
453   -DEF(movb_eflags_T0)
454   -DEF(movl_T0_eflags)
455   -DEF(cld)
456   -DEF(std)
457   -DEF(clc)
458   -DEF(stc)
459   -DEF(cmc)
460   -DEF(salc)
461   -DEF(flds_FT0_A0)
462   -DEF(fldl_FT0_A0)
463   -DEF(fild_FT0_A0)
464   -DEF(fildl_FT0_A0)
465   -DEF(fildll_FT0_A0)
466   -DEF(flds_ST0_A0)
467   -DEF(fldl_ST0_A0)
468   -DEF(fldt_ST0_A0)
469   -DEF(fild_ST0_A0)
470   -DEF(fildl_ST0_A0)
471   -DEF(fildll_ST0_A0)
472   -DEF(fsts_ST0_A0)
473   -DEF(fstl_ST0_A0)
474   -DEF(fstt_ST0_A0)
475   -DEF(fist_ST0_A0)
476   -DEF(fistl_ST0_A0)
477   -DEF(fistll_ST0_A0)
478   -DEF(fbld_ST0_A0)
479   -DEF(fbst_ST0_A0)
480   -DEF(fpush)
481   -DEF(fpop)
482   -DEF(fdecstp)
483   -DEF(fincstp)
484   -DEF(fmov_ST0_FT0)
485   -DEF(fmov_FT0_STN)
486   -DEF(fmov_ST0_STN)
487   -DEF(fmov_STN_ST0)
488   -DEF(fxchg_ST0_STN)
489   -DEF(fcom_ST0_FT0)
490   -DEF(fucom_ST0_FT0)
491   -DEF(fadd_ST0_FT0)
492   -DEF(fmul_ST0_FT0)
493   -DEF(fsub_ST0_FT0)
494   -DEF(fsubr_ST0_FT0)
495   -DEF(fdiv_ST0_FT0)
496   -DEF(fdivr_ST0_FT0)
497   -DEF(fadd_STN_ST0)
498   -DEF(fmul_STN_ST0)
499   -DEF(fsub_STN_ST0)
500   -DEF(fsubr_STN_ST0)
501   -DEF(fdiv_STN_ST0)
502   -DEF(fdivr_STN_ST0)
503   -DEF(fchs_ST0)
504   -DEF(fabs_ST0)
505   -DEF(fxam_ST0)
506   -DEF(fld1_ST0)
507   -DEF(fldl2t_ST0)
508   -DEF(fldl2e_ST0)
509   -DEF(fldpi_ST0)
510   -DEF(fldlg2_ST0)
511   -DEF(fldln2_ST0)
512   -DEF(fldz_ST0)
513   -DEF(fldz_FT0)
514   -DEF(f2xm1)
515   -DEF(fyl2x)
516   -DEF(fptan)
517   -DEF(fpatan)
518   -DEF(fxtract)
519   -DEF(fprem1)
520   -DEF(fprem)
521   -DEF(fyl2xp1)
522   -DEF(fsqrt)
523   -DEF(fsincos)
524   -DEF(frndint)
525   -DEF(fscale)
526   -DEF(fsin)
527   -DEF(fcos)
528   -DEF(fnstsw_A0)
529   -DEF(fnstsw_EAX)
530   -DEF(fnstcw_A0)
531   -DEF(fldcw_A0)
532   -DEF(fclex)
533   -DEF(fninit)
534   -DEF(lock)
535   -DEF(unlock)
  1 +DEF(end, 0)
  2 +DEF(movl_A0_EAX, 0)
  3 +DEF(addl_A0_EAX, 0)
  4 +DEF(addl_A0_EAX_s1, 0)
  5 +DEF(addl_A0_EAX_s2, 0)
  6 +DEF(addl_A0_EAX_s3, 0)
  7 +DEF(movl_T0_EAX, 0)
  8 +DEF(movl_T1_EAX, 0)
  9 +DEF(movh_T0_EAX, 0)
  10 +DEF(movh_T1_EAX, 0)
  11 +DEF(movl_EAX_T0, 0)
  12 +DEF(movl_EAX_T1, 0)
  13 +DEF(movl_EAX_A0, 0)
  14 +DEF(cmovw_EAX_T1_T0, 0)
  15 +DEF(cmovl_EAX_T1_T0, 0)
  16 +DEF(movw_EAX_T0, 0)
  17 +DEF(movw_EAX_T1, 0)
  18 +DEF(movw_EAX_A0, 0)
  19 +DEF(movb_EAX_T0, 0)
  20 +DEF(movh_EAX_T0, 0)
  21 +DEF(movb_EAX_T1, 0)
  22 +DEF(movh_EAX_T1, 0)
  23 +DEF(movl_A0_ECX, 0)
  24 +DEF(addl_A0_ECX, 0)
  25 +DEF(addl_A0_ECX_s1, 0)
  26 +DEF(addl_A0_ECX_s2, 0)
  27 +DEF(addl_A0_ECX_s3, 0)
  28 +DEF(movl_T0_ECX, 0)
  29 +DEF(movl_T1_ECX, 0)
  30 +DEF(movh_T0_ECX, 0)
  31 +DEF(movh_T1_ECX, 0)
  32 +DEF(movl_ECX_T0, 0)
  33 +DEF(movl_ECX_T1, 0)
  34 +DEF(movl_ECX_A0, 0)
  35 +DEF(cmovw_ECX_T1_T0, 0)
  36 +DEF(cmovl_ECX_T1_T0, 0)
  37 +DEF(movw_ECX_T0, 0)
  38 +DEF(movw_ECX_T1, 0)
  39 +DEF(movw_ECX_A0, 0)
  40 +DEF(movb_ECX_T0, 0)
  41 +DEF(movh_ECX_T0, 0)
  42 +DEF(movb_ECX_T1, 0)
  43 +DEF(movh_ECX_T1, 0)
  44 +DEF(movl_A0_EDX, 0)
  45 +DEF(addl_A0_EDX, 0)
  46 +DEF(addl_A0_EDX_s1, 0)
  47 +DEF(addl_A0_EDX_s2, 0)
  48 +DEF(addl_A0_EDX_s3, 0)
  49 +DEF(movl_T0_EDX, 0)
  50 +DEF(movl_T1_EDX, 0)
  51 +DEF(movh_T0_EDX, 0)
  52 +DEF(movh_T1_EDX, 0)
  53 +DEF(movl_EDX_T0, 0)
  54 +DEF(movl_EDX_T1, 0)
  55 +DEF(movl_EDX_A0, 0)
  56 +DEF(cmovw_EDX_T1_T0, 0)
  57 +DEF(cmovl_EDX_T1_T0, 0)
  58 +DEF(movw_EDX_T0, 0)
  59 +DEF(movw_EDX_T1, 0)
  60 +DEF(movw_EDX_A0, 0)
  61 +DEF(movb_EDX_T0, 0)
  62 +DEF(movh_EDX_T0, 0)
  63 +DEF(movb_EDX_T1, 0)
  64 +DEF(movh_EDX_T1, 0)
  65 +DEF(movl_A0_EBX, 0)
  66 +DEF(addl_A0_EBX, 0)
  67 +DEF(addl_A0_EBX_s1, 0)
  68 +DEF(addl_A0_EBX_s2, 0)
  69 +DEF(addl_A0_EBX_s3, 0)
  70 +DEF(movl_T0_EBX, 0)
  71 +DEF(movl_T1_EBX, 0)
  72 +DEF(movh_T0_EBX, 0)
  73 +DEF(movh_T1_EBX, 0)
  74 +DEF(movl_EBX_T0, 0)
  75 +DEF(movl_EBX_T1, 0)
  76 +DEF(movl_EBX_A0, 0)
  77 +DEF(cmovw_EBX_T1_T0, 0)
  78 +DEF(cmovl_EBX_T1_T0, 0)
  79 +DEF(movw_EBX_T0, 0)
  80 +DEF(movw_EBX_T1, 0)
  81 +DEF(movw_EBX_A0, 0)
  82 +DEF(movb_EBX_T0, 0)
  83 +DEF(movh_EBX_T0, 0)
  84 +DEF(movb_EBX_T1, 0)
  85 +DEF(movh_EBX_T1, 0)
  86 +DEF(movl_A0_ESP, 0)
  87 +DEF(addl_A0_ESP, 0)
  88 +DEF(addl_A0_ESP_s1, 0)
  89 +DEF(addl_A0_ESP_s2, 0)
  90 +DEF(addl_A0_ESP_s3, 0)
  91 +DEF(movl_T0_ESP, 0)
  92 +DEF(movl_T1_ESP, 0)
  93 +DEF(movh_T0_ESP, 0)
  94 +DEF(movh_T1_ESP, 0)
  95 +DEF(movl_ESP_T0, 0)
  96 +DEF(movl_ESP_T1, 0)
  97 +DEF(movl_ESP_A0, 0)
  98 +DEF(cmovw_ESP_T1_T0, 0)
  99 +DEF(cmovl_ESP_T1_T0, 0)
  100 +DEF(movw_ESP_T0, 0)
  101 +DEF(movw_ESP_T1, 0)
  102 +DEF(movw_ESP_A0, 0)
  103 +DEF(movb_ESP_T0, 0)
  104 +DEF(movh_ESP_T0, 0)
  105 +DEF(movb_ESP_T1, 0)
  106 +DEF(movh_ESP_T1, 0)
  107 +DEF(movl_A0_EBP, 0)
  108 +DEF(addl_A0_EBP, 0)
  109 +DEF(addl_A0_EBP_s1, 0)
  110 +DEF(addl_A0_EBP_s2, 0)
  111 +DEF(addl_A0_EBP_s3, 0)
  112 +DEF(movl_T0_EBP, 0)
  113 +DEF(movl_T1_EBP, 0)
  114 +DEF(movh_T0_EBP, 0)
  115 +DEF(movh_T1_EBP, 0)
  116 +DEF(movl_EBP_T0, 0)
  117 +DEF(movl_EBP_T1, 0)
  118 +DEF(movl_EBP_A0, 0)
  119 +DEF(cmovw_EBP_T1_T0, 0)
  120 +DEF(cmovl_EBP_T1_T0, 0)
  121 +DEF(movw_EBP_T0, 0)
  122 +DEF(movw_EBP_T1, 0)
  123 +DEF(movw_EBP_A0, 0)
  124 +DEF(movb_EBP_T0, 0)
  125 +DEF(movh_EBP_T0, 0)
  126 +DEF(movb_EBP_T1, 0)
  127 +DEF(movh_EBP_T1, 0)
  128 +DEF(movl_A0_ESI, 0)
  129 +DEF(addl_A0_ESI, 0)
  130 +DEF(addl_A0_ESI_s1, 0)
  131 +DEF(addl_A0_ESI_s2, 0)
  132 +DEF(addl_A0_ESI_s3, 0)
  133 +DEF(movl_T0_ESI, 0)
  134 +DEF(movl_T1_ESI, 0)
  135 +DEF(movh_T0_ESI, 0)
  136 +DEF(movh_T1_ESI, 0)
  137 +DEF(movl_ESI_T0, 0)
  138 +DEF(movl_ESI_T1, 0)
  139 +DEF(movl_ESI_A0, 0)
  140 +DEF(cmovw_ESI_T1_T0, 0)
  141 +DEF(cmovl_ESI_T1_T0, 0)
  142 +DEF(movw_ESI_T0, 0)
  143 +DEF(movw_ESI_T1, 0)
  144 +DEF(movw_ESI_A0, 0)
  145 +DEF(movb_ESI_T0, 0)
  146 +DEF(movh_ESI_T0, 0)
  147 +DEF(movb_ESI_T1, 0)
  148 +DEF(movh_ESI_T1, 0)
  149 +DEF(movl_A0_EDI, 0)
  150 +DEF(addl_A0_EDI, 0)
  151 +DEF(addl_A0_EDI_s1, 0)
  152 +DEF(addl_A0_EDI_s2, 0)
  153 +DEF(addl_A0_EDI_s3, 0)
  154 +DEF(movl_T0_EDI, 0)
  155 +DEF(movl_T1_EDI, 0)
  156 +DEF(movh_T0_EDI, 0)
  157 +DEF(movh_T1_EDI, 0)
  158 +DEF(movl_EDI_T0, 0)
  159 +DEF(movl_EDI_T1, 0)
  160 +DEF(movl_EDI_A0, 0)
  161 +DEF(cmovw_EDI_T1_T0, 0)
  162 +DEF(cmovl_EDI_T1_T0, 0)
  163 +DEF(movw_EDI_T0, 0)
  164 +DEF(movw_EDI_T1, 0)
  165 +DEF(movw_EDI_A0, 0)
  166 +DEF(movb_EDI_T0, 0)
  167 +DEF(movh_EDI_T0, 0)
  168 +DEF(movb_EDI_T1, 0)
  169 +DEF(movh_EDI_T1, 0)
  170 +DEF(addl_T0_T1_cc, 0)
  171 +DEF(orl_T0_T1_cc, 0)
  172 +DEF(andl_T0_T1_cc, 0)
  173 +DEF(subl_T0_T1_cc, 0)
  174 +DEF(xorl_T0_T1_cc, 0)
  175 +DEF(cmpl_T0_T1_cc, 0)
  176 +DEF(negl_T0_cc, 0)
  177 +DEF(incl_T0_cc, 0)
  178 +DEF(decl_T0_cc, 0)
  179 +DEF(testl_T0_T1_cc, 0)
  180 +DEF(addl_T0_T1, 0)
  181 +DEF(orl_T0_T1, 0)
  182 +DEF(andl_T0_T1, 0)
  183 +DEF(subl_T0_T1, 0)
  184 +DEF(xorl_T0_T1, 0)
  185 +DEF(negl_T0, 0)
  186 +DEF(incl_T0, 0)
  187 +DEF(decl_T0, 0)
  188 +DEF(notl_T0, 0)
  189 +DEF(bswapl_T0, 0)
  190 +DEF(mulb_AL_T0, 0)
  191 +DEF(imulb_AL_T0, 0)
  192 +DEF(mulw_AX_T0, 0)
  193 +DEF(imulw_AX_T0, 0)
  194 +DEF(mull_EAX_T0, 0)
  195 +DEF(imull_EAX_T0, 0)
  196 +DEF(imulw_T0_T1, 0)
  197 +DEF(imull_T0_T1, 0)
  198 +DEF(divb_AL_T0, 0)
  199 +DEF(idivb_AL_T0, 0)
  200 +DEF(divw_AX_T0, 0)
  201 +DEF(idivw_AX_T0, 0)
  202 +DEF(divl_EAX_T0, 0)
  203 +DEF(idivl_EAX_T0, 0)
  204 +DEF(movl_T0_im, 1)
  205 +DEF(addl_T0_im, 1)
  206 +DEF(andl_T0_ffff, 0)
  207 +DEF(movl_T0_T1, 0)
  208 +DEF(movl_T1_im, 1)
  209 +DEF(addl_T1_im, 1)
  210 +DEF(movl_T1_A0, 0)
  211 +DEF(movl_A0_im, 1)
  212 +DEF(addl_A0_im, 1)
  213 +DEF(addl_A0_AL, 0)
  214 +DEF(andl_A0_ffff, 0)
  215 +DEF(ldub_T0_A0, 0)
  216 +DEF(ldsb_T0_A0, 0)
  217 +DEF(lduw_T0_A0, 0)
  218 +DEF(ldsw_T0_A0, 0)
  219 +DEF(ldl_T0_A0, 0)
  220 +DEF(ldub_T1_A0, 0)
  221 +DEF(ldsb_T1_A0, 0)
  222 +DEF(lduw_T1_A0, 0)
  223 +DEF(ldsw_T1_A0, 0)
  224 +DEF(ldl_T1_A0, 0)
  225 +DEF(stb_T0_A0, 0)
  226 +DEF(stw_T0_A0, 0)
  227 +DEF(stl_T0_A0, 0)
  228 +DEF(add_bitw_A0_T1, 0)
  229 +DEF(add_bitl_A0_T1, 0)
  230 +DEF(jmp_T0, 0)
  231 +DEF(jmp_im, 1)
  232 +DEF(int_im, 1)
  233 +DEF(int3, 1)
  234 +DEF(into, 0)
  235 +DEF(boundw, 0)
  236 +DEF(boundl, 0)
  237 +DEF(cmpxchg8b, 0)
  238 +DEF(jb_subb, 2)
  239 +DEF(jz_subb, 2)
  240 +DEF(jbe_subb, 2)
  241 +DEF(js_subb, 2)
  242 +DEF(jl_subb, 2)
  243 +DEF(jle_subb, 2)
  244 +DEF(setb_T0_subb, 0)
  245 +DEF(setz_T0_subb, 0)
  246 +DEF(setbe_T0_subb, 0)
  247 +DEF(sets_T0_subb, 0)
  248 +DEF(setl_T0_subb, 0)
  249 +DEF(setle_T0_subb, 0)
  250 +DEF(rolb_T0_T1_cc, 0)
  251 +DEF(rolb_T0_T1, 0)
  252 +DEF(rorb_T0_T1_cc, 0)
  253 +DEF(rorb_T0_T1, 0)
  254 +DEF(rclb_T0_T1_cc, 0)
  255 +DEF(rcrb_T0_T1_cc, 0)
  256 +DEF(shlb_T0_T1_cc, 0)
  257 +DEF(shlb_T0_T1, 0)
  258 +DEF(shrb_T0_T1_cc, 0)
  259 +DEF(shrb_T0_T1, 0)
  260 +DEF(sarb_T0_T1_cc, 0)
  261 +DEF(sarb_T0_T1, 0)
  262 +DEF(adcb_T0_T1_cc, 0)
  263 +DEF(sbbb_T0_T1_cc, 0)
  264 +DEF(cmpxchgb_T0_T1_EAX_cc, 0)
  265 +DEF(movsb_fast, 0)
  266 +DEF(rep_movsb_fast, 0)
  267 +DEF(stosb_fast, 0)
  268 +DEF(rep_stosb_fast, 0)
  269 +DEF(lodsb_fast, 0)
  270 +DEF(rep_lodsb_fast, 0)
  271 +DEF(scasb_fast, 0)
  272 +DEF(repz_scasb_fast, 0)
  273 +DEF(repnz_scasb_fast, 0)
  274 +DEF(cmpsb_fast, 0)
  275 +DEF(repz_cmpsb_fast, 0)
  276 +DEF(repnz_cmpsb_fast, 0)
  277 +DEF(outsb_fast, 0)
  278 +DEF(rep_outsb_fast, 0)
  279 +DEF(insb_fast, 0)
  280 +DEF(rep_insb_fast, 0)
  281 +DEF(movsb_a32, 0)
  282 +DEF(rep_movsb_a32, 0)
  283 +DEF(stosb_a32, 0)
  284 +DEF(rep_stosb_a32, 0)
  285 +DEF(lodsb_a32, 0)
  286 +DEF(rep_lodsb_a32, 0)
  287 +DEF(scasb_a32, 0)
  288 +DEF(repz_scasb_a32, 0)
  289 +DEF(repnz_scasb_a32, 0)
  290 +DEF(cmpsb_a32, 0)
  291 +DEF(repz_cmpsb_a32, 0)
  292 +DEF(repnz_cmpsb_a32, 0)
  293 +DEF(outsb_a32, 0)
  294 +DEF(rep_outsb_a32, 0)
  295 +DEF(insb_a32, 0)
  296 +DEF(rep_insb_a32, 0)
  297 +DEF(movsb_a16, 0)
  298 +DEF(rep_movsb_a16, 0)
  299 +DEF(stosb_a16, 0)
  300 +DEF(rep_stosb_a16, 0)
  301 +DEF(lodsb_a16, 0)
  302 +DEF(rep_lodsb_a16, 0)
  303 +DEF(scasb_a16, 0)
  304 +DEF(repz_scasb_a16, 0)
  305 +DEF(repnz_scasb_a16, 0)
  306 +DEF(cmpsb_a16, 0)
  307 +DEF(repz_cmpsb_a16, 0)
  308 +DEF(repnz_cmpsb_a16, 0)
  309 +DEF(outsb_a16, 0)
  310 +DEF(rep_outsb_a16, 0)
  311 +DEF(insb_a16, 0)
  312 +DEF(rep_insb_a16, 0)
  313 +DEF(outb_T0_T1, 0)
  314 +DEF(inb_T0_T1, 0)
  315 +DEF(jb_subw, 2)
  316 +DEF(jz_subw, 2)
  317 +DEF(jbe_subw, 2)
  318 +DEF(js_subw, 2)
  319 +DEF(jl_subw, 2)
  320 +DEF(jle_subw, 2)
  321 +DEF(loopnzw, 2)
  322 +DEF(loopzw, 2)
  323 +DEF(loopw, 2)
  324 +DEF(jecxzw, 2)
  325 +DEF(setb_T0_subw, 0)
  326 +DEF(setz_T0_subw, 0)
  327 +DEF(setbe_T0_subw, 0)
  328 +DEF(sets_T0_subw, 0)
  329 +DEF(setl_T0_subw, 0)
  330 +DEF(setle_T0_subw, 0)
  331 +DEF(rolw_T0_T1_cc, 0)
  332 +DEF(rolw_T0_T1, 0)
  333 +DEF(rorw_T0_T1_cc, 0)
  334 +DEF(rorw_T0_T1, 0)
  335 +DEF(rclw_T0_T1_cc, 0)
  336 +DEF(rcrw_T0_T1_cc, 0)
  337 +DEF(shlw_T0_T1_cc, 0)
  338 +DEF(shlw_T0_T1, 0)
  339 +DEF(shrw_T0_T1_cc, 0)
  340 +DEF(shrw_T0_T1, 0)
  341 +DEF(sarw_T0_T1_cc, 0)
  342 +DEF(sarw_T0_T1, 0)
  343 +DEF(shldw_T0_T1_im_cc, 1)
  344 +DEF(shldw_T0_T1_ECX_cc, 0)
  345 +DEF(shrdw_T0_T1_im_cc, 1)
  346 +DEF(shrdw_T0_T1_ECX_cc, 0)
  347 +DEF(adcw_T0_T1_cc, 0)
  348 +DEF(sbbw_T0_T1_cc, 0)
  349 +DEF(cmpxchgw_T0_T1_EAX_cc, 0)
  350 +DEF(btw_T0_T1_cc, 0)
  351 +DEF(btsw_T0_T1_cc, 0)
  352 +DEF(btrw_T0_T1_cc, 0)
  353 +DEF(btcw_T0_T1_cc, 0)
  354 +DEF(bsfw_T0_cc, 0)
  355 +DEF(bsrw_T0_cc, 0)
  356 +DEF(movsw_fast, 0)
  357 +DEF(rep_movsw_fast, 0)
  358 +DEF(stosw_fast, 0)
  359 +DEF(rep_stosw_fast, 0)
  360 +DEF(lodsw_fast, 0)
  361 +DEF(rep_lodsw_fast, 0)
  362 +DEF(scasw_fast, 0)
  363 +DEF(repz_scasw_fast, 0)
  364 +DEF(repnz_scasw_fast, 0)
  365 +DEF(cmpsw_fast, 0)
  366 +DEF(repz_cmpsw_fast, 0)
  367 +DEF(repnz_cmpsw_fast, 0)
  368 +DEF(outsw_fast, 0)
  369 +DEF(rep_outsw_fast, 0)
  370 +DEF(insw_fast, 0)
  371 +DEF(rep_insw_fast, 0)
  372 +DEF(movsw_a32, 0)
  373 +DEF(rep_movsw_a32, 0)
  374 +DEF(stosw_a32, 0)
  375 +DEF(rep_stosw_a32, 0)
  376 +DEF(lodsw_a32, 0)
  377 +DEF(rep_lodsw_a32, 0)
  378 +DEF(scasw_a32, 0)
  379 +DEF(repz_scasw_a32, 0)
  380 +DEF(repnz_scasw_a32, 0)
  381 +DEF(cmpsw_a32, 0)
  382 +DEF(repz_cmpsw_a32, 0)
  383 +DEF(repnz_cmpsw_a32, 0)
  384 +DEF(outsw_a32, 0)
  385 +DEF(rep_outsw_a32, 0)
  386 +DEF(insw_a32, 0)
  387 +DEF(rep_insw_a32, 0)
  388 +DEF(movsw_a16, 0)
  389 +DEF(rep_movsw_a16, 0)
  390 +DEF(stosw_a16, 0)
  391 +DEF(rep_stosw_a16, 0)
  392 +DEF(lodsw_a16, 0)
  393 +DEF(rep_lodsw_a16, 0)
  394 +DEF(scasw_a16, 0)
  395 +DEF(repz_scasw_a16, 0)
  396 +DEF(repnz_scasw_a16, 0)
  397 +DEF(cmpsw_a16, 0)
  398 +DEF(repz_cmpsw_a16, 0)
  399 +DEF(repnz_cmpsw_a16, 0)
  400 +DEF(outsw_a16, 0)
  401 +DEF(rep_outsw_a16, 0)
  402 +DEF(insw_a16, 0)
  403 +DEF(rep_insw_a16, 0)
  404 +DEF(outw_T0_T1, 0)
  405 +DEF(inw_T0_T1, 0)
  406 +DEF(jb_subl, 2)
  407 +DEF(jz_subl, 2)
  408 +DEF(jbe_subl, 2)
  409 +DEF(js_subl, 2)
  410 +DEF(jl_subl, 2)
  411 +DEF(jle_subl, 2)
  412 +DEF(loopnzl, 2)
  413 +DEF(loopzl, 2)
  414 +DEF(loopl, 2)
  415 +DEF(jecxzl, 2)
  416 +DEF(setb_T0_subl, 0)
  417 +DEF(setz_T0_subl, 0)
  418 +DEF(setbe_T0_subl, 0)
  419 +DEF(sets_T0_subl, 0)
  420 +DEF(setl_T0_subl, 0)
  421 +DEF(setle_T0_subl, 0)
  422 +DEF(roll_T0_T1_cc, 0)
  423 +DEF(roll_T0_T1, 0)
  424 +DEF(rorl_T0_T1_cc, 0)
  425 +DEF(rorl_T0_T1, 0)
  426 +DEF(rcll_T0_T1_cc, 0)
  427 +DEF(rcrl_T0_T1_cc, 0)
  428 +DEF(shll_T0_T1_cc, 0)
  429 +DEF(shll_T0_T1, 0)
  430 +DEF(shrl_T0_T1_cc, 0)
  431 +DEF(shrl_T0_T1, 0)
  432 +DEF(sarl_T0_T1_cc, 0)
  433 +DEF(sarl_T0_T1, 0)
  434 +DEF(shldl_T0_T1_im_cc, 1)
  435 +DEF(shldl_T0_T1_ECX_cc, 0)
  436 +DEF(shrdl_T0_T1_im_cc, 1)
  437 +DEF(shrdl_T0_T1_ECX_cc, 0)
  438 +DEF(adcl_T0_T1_cc, 0)
  439 +DEF(sbbl_T0_T1_cc, 0)
  440 +DEF(cmpxchgl_T0_T1_EAX_cc, 0)
  441 +DEF(btl_T0_T1_cc, 0)
  442 +DEF(btsl_T0_T1_cc, 0)
  443 +DEF(btrl_T0_T1_cc, 0)
  444 +DEF(btcl_T0_T1_cc, 0)
  445 +DEF(bsfl_T0_cc, 0)
  446 +DEF(bsrl_T0_cc, 0)
  447 +DEF(movsl_fast, 0)
  448 +DEF(rep_movsl_fast, 0)
  449 +DEF(stosl_fast, 0)
  450 +DEF(rep_stosl_fast, 0)
  451 +DEF(lodsl_fast, 0)
  452 +DEF(rep_lodsl_fast, 0)
  453 +DEF(scasl_fast, 0)
  454 +DEF(repz_scasl_fast, 0)
  455 +DEF(repnz_scasl_fast, 0)
  456 +DEF(cmpsl_fast, 0)
  457 +DEF(repz_cmpsl_fast, 0)
  458 +DEF(repnz_cmpsl_fast, 0)
  459 +DEF(outsl_fast, 0)
  460 +DEF(rep_outsl_fast, 0)
  461 +DEF(insl_fast, 0)
  462 +DEF(rep_insl_fast, 0)
  463 +DEF(movsl_a32, 0)
  464 +DEF(rep_movsl_a32, 0)
  465 +DEF(stosl_a32, 0)
  466 +DEF(rep_stosl_a32, 0)
  467 +DEF(lodsl_a32, 0)
  468 +DEF(rep_lodsl_a32, 0)
  469 +DEF(scasl_a32, 0)
  470 +DEF(repz_scasl_a32, 0)
  471 +DEF(repnz_scasl_a32, 0)
  472 +DEF(cmpsl_a32, 0)
  473 +DEF(repz_cmpsl_a32, 0)
  474 +DEF(repnz_cmpsl_a32, 0)
  475 +DEF(outsl_a32, 0)
  476 +DEF(rep_outsl_a32, 0)
  477 +DEF(insl_a32, 0)
  478 +DEF(rep_insl_a32, 0)
  479 +DEF(movsl_a16, 0)
  480 +DEF(rep_movsl_a16, 0)
  481 +DEF(stosl_a16, 0)
  482 +DEF(rep_stosl_a16, 0)
  483 +DEF(lodsl_a16, 0)
  484 +DEF(rep_lodsl_a16, 0)
  485 +DEF(scasl_a16, 0)
  486 +DEF(repz_scasl_a16, 0)
  487 +DEF(repnz_scasl_a16, 0)
  488 +DEF(cmpsl_a16, 0)
  489 +DEF(repz_cmpsl_a16, 0)
  490 +DEF(repnz_cmpsl_a16, 0)
  491 +DEF(outsl_a16, 0)
  492 +DEF(rep_outsl_a16, 0)
  493 +DEF(insl_a16, 0)
  494 +DEF(rep_insl_a16, 0)
  495 +DEF(outl_T0_T1, 0)
  496 +DEF(inl_T0_T1, 0)
  497 +DEF(movsbl_T0_T0, 0)
  498 +DEF(movzbl_T0_T0, 0)
  499 +DEF(movswl_T0_T0, 0)
  500 +DEF(movzwl_T0_T0, 0)
  501 +DEF(movswl_EAX_AX, 0)
  502 +DEF(movsbw_AX_AL, 0)
  503 +DEF(movslq_EDX_EAX, 0)
  504 +DEF(movswl_DX_AX, 0)
  505 +DEF(pushl_T0, 0)
  506 +DEF(pushw_T0, 0)
  507 +DEF(pushl_ss32_T0, 0)
  508 +DEF(pushw_ss32_T0, 0)
  509 +DEF(pushl_ss16_T0, 0)
  510 +DEF(pushw_ss16_T0, 0)
  511 +DEF(popl_T0, 0)
  512 +DEF(popw_T0, 0)
  513 +DEF(popl_ss32_T0, 0)
  514 +DEF(popw_ss32_T0, 0)
  515 +DEF(popl_ss16_T0, 0)
  516 +DEF(popw_ss16_T0, 0)
  517 +DEF(addl_ESP_4, 0)
  518 +DEF(addl_ESP_2, 0)
  519 +DEF(addw_ESP_4, 0)
  520 +DEF(addw_ESP_2, 0)
  521 +DEF(addl_ESP_im, 1)
  522 +DEF(addw_ESP_im, 1)
  523 +DEF(rdtsc, 0)
  524 +DEF(cpuid, 0)
  525 +DEF(aam, 1)
  526 +DEF(aad, 1)
  527 +DEF(aaa, 0)
  528 +DEF(aas, 0)
  529 +DEF(daa, 0)
  530 +DEF(das, 0)
  531 +DEF(movl_seg_T0, 1)
  532 +DEF(movl_T0_seg, 1)
  533 +DEF(movl_A0_seg, 1)
  534 +DEF(addl_A0_seg, 1)
  535 +DEF(jo_cc, 2)
  536 +DEF(jb_cc, 2)
  537 +DEF(jz_cc, 2)
  538 +DEF(jbe_cc, 2)
  539 +DEF(js_cc, 2)
  540 +DEF(jp_cc, 2)
  541 +DEF(jl_cc, 2)
  542 +DEF(jle_cc, 2)
  543 +DEF(seto_T0_cc, 0)
  544 +DEF(setb_T0_cc, 0)
  545 +DEF(setz_T0_cc, 0)
  546 +DEF(setbe_T0_cc, 0)
  547 +DEF(sets_T0_cc, 0)
  548 +DEF(setp_T0_cc, 0)
  549 +DEF(setl_T0_cc, 0)
  550 +DEF(setle_T0_cc, 0)
  551 +DEF(xor_T0_1, 0)
  552 +DEF(set_cc_op, 1)
  553 +DEF(movl_eflags_T0, 0)
  554 +DEF(movb_eflags_T0, 0)
  555 +DEF(movl_T0_eflags, 0)
  556 +DEF(cld, 0)
  557 +DEF(std, 0)
  558 +DEF(clc, 0)
  559 +DEF(stc, 0)
  560 +DEF(cmc, 0)
  561 +DEF(salc, 0)
  562 +DEF(flds_FT0_A0, 0)
  563 +DEF(fldl_FT0_A0, 0)
  564 +DEF(fild_FT0_A0, 0)
  565 +DEF(fildl_FT0_A0, 0)
  566 +DEF(fildll_FT0_A0, 0)
  567 +DEF(flds_ST0_A0, 0)
  568 +DEF(fldl_ST0_A0, 0)
  569 +DEF(fldt_ST0_A0, 0)
  570 +DEF(fild_ST0_A0, 0)
  571 +DEF(fildl_ST0_A0, 0)
  572 +DEF(fildll_ST0_A0, 0)
  573 +DEF(fsts_ST0_A0, 0)
  574 +DEF(fstl_ST0_A0, 0)
  575 +DEF(fstt_ST0_A0, 0)
  576 +DEF(fist_ST0_A0, 0)
  577 +DEF(fistl_ST0_A0, 0)
  578 +DEF(fistll_ST0_A0, 0)
  579 +DEF(fbld_ST0_A0, 0)
  580 +DEF(fbst_ST0_A0, 0)
  581 +DEF(fpush, 0)
  582 +DEF(fpop, 0)
  583 +DEF(fdecstp, 0)
  584 +DEF(fincstp, 0)
  585 +DEF(fmov_ST0_FT0, 0)
  586 +DEF(fmov_FT0_STN, 1)
  587 +DEF(fmov_ST0_STN, 1)
  588 +DEF(fmov_STN_ST0, 1)
  589 +DEF(fxchg_ST0_STN, 1)
  590 +DEF(fcom_ST0_FT0, 0)
  591 +DEF(fucom_ST0_FT0, 0)
  592 +DEF(fadd_ST0_FT0, 0)
  593 +DEF(fmul_ST0_FT0, 0)
  594 +DEF(fsub_ST0_FT0, 0)
  595 +DEF(fsubr_ST0_FT0, 0)
  596 +DEF(fdiv_ST0_FT0, 0)
  597 +DEF(fdivr_ST0_FT0, 0)
  598 +DEF(fadd_STN_ST0, 1)
  599 +DEF(fmul_STN_ST0, 1)
  600 +DEF(fsub_STN_ST0, 1)
  601 +DEF(fsubr_STN_ST0, 1)
  602 +DEF(fdiv_STN_ST0, 1)
  603 +DEF(fdivr_STN_ST0, 1)
  604 +DEF(fchs_ST0, 0)
  605 +DEF(fabs_ST0, 0)
  606 +DEF(fxam_ST0, 0)
  607 +DEF(fld1_ST0, 0)
  608 +DEF(fldl2t_ST0, 0)
  609 +DEF(fldl2e_ST0, 0)
  610 +DEF(fldpi_ST0, 0)
  611 +DEF(fldlg2_ST0, 0)
  612 +DEF(fldln2_ST0, 0)
  613 +DEF(fldz_ST0, 0)
  614 +DEF(fldz_FT0, 0)
  615 +DEF(f2xm1, 0)
  616 +DEF(fyl2x, 0)
  617 +DEF(fptan, 0)
  618 +DEF(fpatan, 0)
  619 +DEF(fxtract, 0)
  620 +DEF(fprem1, 0)
  621 +DEF(fprem, 0)
  622 +DEF(fyl2xp1, 0)
  623 +DEF(fsqrt, 0)
  624 +DEF(fsincos, 0)
  625 +DEF(frndint, 0)
  626 +DEF(fscale, 0)
  627 +DEF(fsin, 0)
  628 +DEF(fcos, 0)
  629 +DEF(fnstsw_A0, 0)
  630 +DEF(fnstsw_EAX, 0)
  631 +DEF(fnstcw_A0, 0)
  632 +DEF(fldcw_A0, 0)
  633 +DEF(fclex, 0)
  634 +DEF(fninit, 0)
  635 +DEF(lock, 0)
  636 +DEF(unlock, 0)
... ...