gwj / at91sam9263 · Commits

Commit 0da75eb13524d5aa426486d015d63e1b6ce34aa2

Authored by ths
1 parent 605686cd

Big endian support for Gallileo, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2330 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 67 additions and 5 deletions
hw/gt64xxx.c
  View file @0da75eb
... ... @@ -240,14 +240,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
240 240 GT64120State *s = opaque;
241 241 uint32_t saddr;
242 242  
  243 +#ifdef TARGET_WORDS_BIGENDIAN
  244 + val = bswap32(val);
  245 +#endif
  246 +
243 247 saddr = (addr & 0xfff) >> 2;
244 248 switch (saddr) {
245   - /* CPU Configuration Register */
  249 +
  250 + /* CPU Configuration */
246 251 case GT_CPU:
247 252 s->regs[GT_CPU] = val;
248   - gt64120_pci_mapping(s);
249 253 break;
250 254 case GT_MULTI:
  255 + /* Read-only register as only one GT64xxx is present on the CPU bus */
251 256 break;
252 257  
253 258 /* CPU Address Decode */
... ... @@ -306,6 +311,13 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
306 311 case GT_CPUERR_DATALO:
307 312 case GT_CPUERR_DATAHI:
308 313 case GT_CPUERR_PARITY:
  314 + /* Read-only registers, do nothing */
  315 + break;
  316 +
  317 + /* CPU Sync Barrier */
  318 + case GT_PCI0SYNC:
  319 + case GT_PCI1SYNC:
  320 + /* Read-only registers, do nothing */
309 321 break;
310 322  
311 323 /* ECC */
... ... @@ -314,6 +326,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
314 326 case GT_ECC_MEM:
315 327 case GT_ECC_CALC:
316 328 case GT_ECC_ERRADDR:
  329 + /* Read-only registers, do nothing */
317 330 break;
318 331  
319 332 /* PCI Internal */
... ... @@ -328,6 +341,16 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
328 341 pci_host_data_writel(s->pci, 0, val);
329 342 break;
330 343  
  344 + /* SDRAM Parameters */
  345 + case GT_SDRAM_B0:
  346 + case GT_SDRAM_B1:
  347 + case GT_SDRAM_B2:
  348 + case GT_SDRAM_B3:
  349 + /* We don't simulate electrical parameters of the SDRAM.
  350 + Accept, but ignore the values. */
  351 + s->regs[saddr] = val;
  352 + break;
  353 +
331 354 default:
332 355 #if 0
333 356 printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
... ... @@ -348,13 +371,31 @@ static uint32_t gt64120_readl (void *opaque,
348 371  
349 372 switch (saddr) {
350 373  
  374 + /* CPU Configuration */
  375 + case GT_MULTI:
  376 + /* Only one GT64xxx is present on the CPU bus, return
  377 + the initial value */
  378 + val = s->regs[saddr];
  379 + break;
  380 +
351 381 /* CPU Error Report */
352 382 case GT_CPUERR_ADDRLO:
353 383 case GT_CPUERR_ADDRHI:
354 384 case GT_CPUERR_DATALO:
355 385 case GT_CPUERR_DATAHI:
356 386 case GT_CPUERR_PARITY:
357   - return 0;
  387 + /* Emulated memory has no error, always return the initial
  388 + values */
  389 + val = s->regs[saddr];
  390 + break;
  391 +
  392 + /* CPU Sync Barrier */
  393 + case GT_PCI0SYNC:
  394 + case GT_PCI1SYNC:
  395 + /* Reading those register should empty all FIFO on the PCI
  396 + bus, which are not emulated. The return value should be
  397 + a random value that should be ignored. */
  398 + val = 0xc000ffee;
358 399 break;
359 400  
360 401 /* ECC */
... ... @@ -363,11 +404,12 @@ static uint32_t gt64120_readl (void *opaque,
363 404 case GT_ECC_MEM:
364 405 case GT_ECC_CALC:
365 406 case GT_ECC_ERRADDR:
366   - return 0;
  407 + /* Emulated memory has no error, always return the initial
  408 + values */
  409 + val = s->regs[saddr];
367 410 break;
368 411  
369 412 case GT_CPU:
370   - case GT_MULTI:
371 413 case GT_PCI0IOLD:
372 414 case GT_PCI0M0LD:
373 415 case GT_PCI0M1LD:
... ... @@ -394,6 +436,16 @@ static uint32_t gt64120_readl (void *opaque,
394 436 val = pic_intack_read(isa_pic);
395 437 break;
396 438  
  439 + /* SDRAM Parameters */
  440 + case GT_SDRAM_B0:
  441 + case GT_SDRAM_B1:
  442 + case GT_SDRAM_B2:
  443 + case GT_SDRAM_B3:
  444 + /* We don't simulate electrical parameters of the SDRAM.
  445 + Just return the last written value. */
  446 + val = s->regs[saddr];
  447 + break;
  448 +
397 449 /* PCI Internal */
398 450 case GT_PCI0_CFGADDR:
399 451 val = s->pci->config_reg;
... ... @@ -410,7 +462,11 @@ static uint32_t gt64120_readl (void *opaque,
410 462 break;
411 463 }
412 464  
  465 +#ifdef TARGET_WORDS_BIGENDIAN
  466 + return bswap32(val);
  467 +#else
413 468 return val;
  469 +#endif
414 470 }
415 471  
416 472 static CPUWriteMemoryFunc *gt64120_write[] = {
... ... @@ -521,6 +577,12 @@ void gt64120_reset(void *opaque)
521 577 s->regs[GT_ECC_CALC] = 0x00000000;
522 578 s->regs[GT_ECC_ERRADDR] = 0x00000000;
523 579  
  580 + /* SDRAM Parameters */
  581 + s->regs[GT_SDRAM_B0] = 0x00000005;
  582 + s->regs[GT_SDRAM_B1] = 0x00000005;
  583 + s->regs[GT_SDRAM_B2] = 0x00000005;
  584 + s->regs[GT_SDRAM_B3] = 0x00000005;
  585 +
524 586 /* PCI Internal FIXME: not complete*/
525 587 #ifdef TARGET_WORDS_BIGENDIAN
526 588 s->regs[GT_PCI0_CMD] = 0x00000000;
... ...