gwj / at91sam9263 · Commits

Commit 0d3301964df6d36c72dfa95ba5ae5e3b789cd1f8

Authored by bellard
1 parent fe1e3ce3

ia64 support 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@115 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 154 additions and 1 deletions
@@ -767,6 +767,114 @@ typedef struct { @@ -767,6 +767,114 @@ typedef struct {
767 #define PF_HP_LAZYSWAP 0x04000000 767 #define PF_HP_LAZYSWAP 0x04000000
768 #define PF_HP_SBP 0x08000000 768 #define PF_HP_SBP 0x08000000
769 769
  770 +/* IA-64 specific declarations. */
  771 +
  772 +/* Processor specific flags for the Ehdr e_flags field. */
  773 +#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
  774 +#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */
  775 +#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */
  776 +
  777 +/* Processor specific values for the Phdr p_type field. */
  778 +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */
  779 +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */
  780 +
  781 +/* Processor specific flags for the Phdr p_flags field. */
  782 +#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */
  783 +
  784 +/* Processor specific values for the Shdr sh_type field. */
  785 +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */
  786 +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */
  787 +
  788 +/* Processor specific flags for the Shdr sh_flags field. */
  789 +#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
  790 +#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */
  791 +
  792 +/* Processor specific values for the Dyn d_tag field. */
  793 +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
  794 +#define DT_IA_64_NUM 1
  795 +
  796 +/* IA-64 relocations. */
  797 +#define R_IA64_NONE 0x00 /* none */
  798 +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */
  799 +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */
  800 +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */
  801 +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */
  802 +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */
  803 +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */
  804 +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */
  805 +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */
  806 +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */
  807 +#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */
  808 +#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */
  809 +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */
  810 +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */
  811 +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */
  812 +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */
  813 +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */
  814 +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */
  815 +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */
  816 +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */
  817 +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */
  818 +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */
  819 +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */
  820 +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */
  821 +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */
  822 +#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */
  823 +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */
  824 +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */
  825 +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */
  826 +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */
  827 +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */
  828 +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */
  829 +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */
  830 +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */
  831 +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */
  832 +#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */
  833 +#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */
  834 +#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */
  835 +#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */
  836 +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */
  837 +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */
  838 +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */
  839 +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */
  840 +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */
  841 +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */
  842 +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */
  843 +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */
  844 +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */
  845 +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */
  846 +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */
  847 +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */
  848 +#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */
  849 +#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */
  850 +#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */
  851 +#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */
  852 +#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */
  853 +#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */
  854 +#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */
  855 +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */
  856 +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */
  857 +#define R_IA64_COPY 0x84 /* copy relocation */
  858 +#define R_IA64_SUB 0x85 /* Addend and symbol difference */
  859 +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
  860 +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */
  861 +#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */
  862 +#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */
  863 +#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */
  864 +#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */
  865 +#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */
  866 +#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */
  867 +#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */
  868 +#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */
  869 +#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */
  870 +#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */
  871 +#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */
  872 +#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */
  873 +#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */
  874 +#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */
  875 +#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */
  876 +#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
  877 +#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
770 878
771 typedef struct elf32_rel { 879 typedef struct elf32_rel {
772 Elf32_Addr r_offset; 880 Elf32_Addr r_offset;
exec-i386.h
  View file @0d33019
@@ -106,6 +106,12 @@ register unsigned int T1 asm("$10"); @@ -106,6 +106,12 @@ register unsigned int T1 asm("$10");
106 register unsigned int A0 asm("$11"); 106 register unsigned int A0 asm("$11");
107 register struct CPUX86State *env asm("$12"); 107 register struct CPUX86State *env asm("$12");
108 #endif 108 #endif
  109 +#ifdef __ia64__
  110 +register unsigned int T0 asm("r24");
  111 +register unsigned int T1 asm("r25");
  112 +register unsigned int A0 asm("r26");
  113 +register struct CPUX86State *env asm("r27");
  114 +#endif
109 115
110 /* force GCC to generate only one epilog at the end of the function */ 116 /* force GCC to generate only one epilog at the end of the function */
111 #define FORCE_RET() asm volatile (""); 117 #define FORCE_RET() asm volatile ("");
ia64-syscall.S 0 → 100644
  View file @0d33019
  1 +/* derived from glibc sysdeps/unix/sysv/linux/ia64/sysdep.S */
  2 +
  3 +#define __ASSEMBLY__
  4 +
  5 +#include <asm/asmmacro.h>
  6 +#include <asm/unistd.h>
  7 +
  8 +ENTRY(__syscall_error)
  9 + .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(0)
  10 + alloc r33=ar.pfs, 0, 4, 0, 0
  11 + mov r32=rp
  12 + .body
  13 + mov r35=r8
  14 + mov r34=r1
  15 + ;;
  16 + br.call.sptk.many b0 = __errno_location
  17 +.Lret0: /* force new bundle */
  18 + st4 [r8]=r35
  19 + mov r1=r34
  20 + mov rp=r32
  21 + mov r8=-1
  22 + mov ar.pfs=r33
  23 + br.ret.sptk.few b0
  24 +END(__syscall_error)
  25 +
  26 +GLOBAL_ENTRY(__ia64_syscall)
  27 + mov r15=r37 /* syscall number */
  28 + break __BREAK_SYSCALL
  29 + cmp.eq p6,p0=-1,r10 /* r10 = -1 on error */
  30 +(p6) br.cond.spnt.few __syscall_error
  31 + br.ret.sptk.few b0
  32 +.endp __ia64_syscall
linux-user/signal.c
  View file @0d33019
@@ -26,6 +26,13 @@ @@ -26,6 +26,13 @@
26 #include <errno.h> 26 #include <errno.h>
27 #include <sys/ucontext.h> 27 #include <sys/ucontext.h>
28 28
  29 +#ifdef __ia64__
  30 +#undef uc_mcontext
  31 +#undef uc_sigmask
  32 +#undef uc_stack
  33 +#undef uc_link
  34 +#endif
  35 +
29 #include "qemu.h" 36 #include "qemu.h"
30 37
31 //#define DEBUG_SIGNAL 38 //#define DEBUG_SIGNAL
@@ -70,7 +70,7 @@ @@ -70,7 +70,7 @@
70 #define TARGET_LONG_BITS 32 70 #define TARGET_LONG_BITS 32
71 71
72 72
73 -#if defined(__alpha__) 73 +#if defined(__alpha__) || defined (__ia64__)
74 #define HOST_LONG_BITS 64 74 #define HOST_LONG_BITS 64
75 #else 75 #else
76 #define HOST_LONG_BITS 32 76 #define HOST_LONG_BITS 32