gwj / at91sam9263 · Commits

Commit 0d1d0094d76a0423c55b345fc2f832a000b5b12f

Authored by ths
1 parent aa0bf00b

Delete obsolete file. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4733 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 0 additions and 104 deletions
target-mips/fop_template.c deleted 100644 → 0
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1 -/*  
2 - * MIPS emulation micro-operations templates for floating point reg  
3 - * load & store for qemu.  
4 - *  
5 - * Copyright (c) 2006 Marius Groeger  
6 - *  
7 - * This library is free software; you can redistribute it and/or  
8 - * modify it under the terms of the GNU Lesser General Public  
9 - * License as published by the Free Software Foundation; either  
10 - * version 2 of the License, or (at your option) any later version.  
11 - *  
12 - * This library is distributed in the hope that it will be useful,  
13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
15 - * Lesser General Public License for more details.  
16 - *  
17 - * You should have received a copy of the GNU Lesser General Public  
18 - * License along with this library; if not, write to the Free Software  
19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
20 - */  
21 -  
22 -#if defined(FREG)  
23 -  
24 -#define OP_WLOAD_FREG(treg, tregname, FREG) \  
25 - void glue(glue(op_load_fpr_,tregname), FREG) (void) \  
26 - { \  
27 - treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \  
28 - FORCE_RET(); \  
29 - }  
30 -  
31 -#define OP_WSTORE_FREG(treg, tregname, FREG) \  
32 - void glue(glue(op_store_fpr_,tregname), FREG) (void) \  
33 - { \  
34 - env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \  
35 - FORCE_RET(); \  
36 - }  
37 -  
38 -/* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */  
39 -OP_WLOAD_FREG(WT0, WT0_fpr, FREG)  
40 -/* FREG.w = WT0: op_store_fpr_WT0_fprFREG */  
41 -OP_WSTORE_FREG(WT0, WT0_fpr, FREG)  
42 -  
43 -OP_WLOAD_FREG(WT1, WT1_fpr, FREG)  
44 -OP_WSTORE_FREG(WT1, WT1_fpr, FREG)  
45 -  
46 -OP_WLOAD_FREG(WT2, WT2_fpr, FREG)  
47 -OP_WSTORE_FREG(WT2, WT2_fpr, FREG)  
48 -  
49 -#define OP_DLOAD_FREG(treg, tregname, FREG) \  
50 - void glue(glue(op_load_fpr_,tregname), FREG) (void) \  
51 - { \  
52 - if (env->hflags & MIPS_HFLAG_F64) \  
53 - treg = env->fpu->fpr[FREG].d; \  
54 - else \  
55 - treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \  
56 - env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \  
57 - FORCE_RET(); \  
58 - }  
59 -  
60 -#define OP_DSTORE_FREG(treg, tregname, FREG) \  
61 - void glue(glue(op_store_fpr_,tregname), FREG) (void) \  
62 - { \  
63 - if (env->hflags & MIPS_HFLAG_F64) \  
64 - env->fpu->fpr[FREG].d = treg; \  
65 - else { \  
66 - env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \  
67 - env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \  
68 - } \  
69 - FORCE_RET(); \  
70 - }  
71 -  
72 -OP_DLOAD_FREG(DT0, DT0_fpr, FREG)  
73 -OP_DSTORE_FREG(DT0, DT0_fpr, FREG)  
74 -  
75 -OP_DLOAD_FREG(DT1, DT1_fpr, FREG)  
76 -OP_DSTORE_FREG(DT1, DT1_fpr, FREG)  
77 -  
78 -OP_DLOAD_FREG(DT2, DT2_fpr, FREG)  
79 -OP_DSTORE_FREG(DT2, DT2_fpr, FREG)  
80 -  
81 -#define OP_PSLOAD_FREG(treg, tregname, FREG) \  
82 - void glue(glue(op_load_fpr_,tregname), FREG) (void) \  
83 - { \  
84 - treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \  
85 - FORCE_RET(); \  
86 - }  
87 -  
88 -#define OP_PSSTORE_FREG(treg, tregname, FREG) \  
89 - void glue(glue(op_store_fpr_,tregname), FREG) (void) \  
90 - { \  
91 - env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \  
92 - FORCE_RET(); \  
93 - }  
94 -  
95 -OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)  
96 -OP_PSSTORE_FREG(WTH0, WTH0_fpr, FREG)  
97 -  
98 -OP_PSLOAD_FREG(WTH1, WTH1_fpr, FREG)  
99 -OP_PSSTORE_FREG(WTH1, WTH1_fpr, FREG)  
100 -  
101 -OP_PSLOAD_FREG(WTH2, WTH2_fpr, FREG)  
102 -OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG)  
103 -  
104 -#endif