gwj / at91sam9263 · Commits

Commit 0c8aacd466ae0f1c78dc8fce215115d5c6052424

Authored by aurel32
1 parent 1c97856d

target-ppc: include the instruction name in load/store handlers name 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5784 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 59 additions and 59 deletions
target-ppc/translate.c
  View file @0c8aacd
@@ -2776,17 +2776,17 @@ static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) @@ -2776,17 +2776,17 @@ static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2776 2776
2777 #endif 2777 #endif
2778 2778
2779 -#define GEN_LD(width, opc, type) \  
2780 -GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ 2779 +#define GEN_LD(name, ldop, opc, type) \
  2780 +GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2781 { \ 2781 { \
2782 - TCGv EA = tcg_temp_new(); \ 2782 + TCGv EA = tcg_temp_new(); \
2783 gen_addr_imm_index(EA, ctx, 0); \ 2783 gen_addr_imm_index(EA, ctx, 0); \
2784 - gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2784 + gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2785 tcg_temp_free(EA); \ 2785 tcg_temp_free(EA); \
2786 } 2786 }
2787 2787
2788 -#define GEN_LDU(width, opc, type) \  
2789 -GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ 2788 +#define GEN_LDU(name, ldop, opc, type) \
  2789 +GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2790 { \ 2790 { \
2791 TCGv EA; \ 2791 TCGv EA; \
2792 if (unlikely(rA(ctx->opcode) == 0 || \ 2792 if (unlikely(rA(ctx->opcode) == 0 || \
@@ -2794,18 +2794,18 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -2794,18 +2794,18 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2794 GEN_EXCP_INVAL(ctx); \ 2794 GEN_EXCP_INVAL(ctx); \
2795 return; \ 2795 return; \
2796 } \ 2796 } \
2797 - EA = tcg_temp_new(); \ 2797 + EA = tcg_temp_new(); \
2798 if (type == PPC_64B) \ 2798 if (type == PPC_64B) \
2799 gen_addr_imm_index(EA, ctx, 0x03); \ 2799 gen_addr_imm_index(EA, ctx, 0x03); \
2800 else \ 2800 else \
2801 gen_addr_imm_index(EA, ctx, 0); \ 2801 gen_addr_imm_index(EA, ctx, 0); \
2802 - gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2802 + gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2803 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2803 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2804 tcg_temp_free(EA); \ 2804 tcg_temp_free(EA); \
2805 } 2805 }
2806 2806
2807 -#define GEN_LDUX(width, opc2, opc3, type) \  
2808 -GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ 2807 +#define GEN_LDUX(name, ldop, opc2, opc3, type) \
  2808 +GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2809 { \ 2809 { \
2810 TCGv EA; \ 2810 TCGv EA; \
2811 if (unlikely(rA(ctx->opcode) == 0 || \ 2811 if (unlikely(rA(ctx->opcode) == 0 || \
@@ -2813,45 +2813,45 @@ GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2813,45 +2813,45 @@ GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2813 GEN_EXCP_INVAL(ctx); \ 2813 GEN_EXCP_INVAL(ctx); \
2814 return; \ 2814 return; \
2815 } \ 2815 } \
2816 - EA = tcg_temp_new(); \ 2816 + EA = tcg_temp_new(); \
2817 gen_addr_reg_index(EA, ctx); \ 2817 gen_addr_reg_index(EA, ctx); \
2818 - gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2818 + gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \ 2820 tcg_temp_free(EA); \
2821 } 2821 }
2822 2822
2823 -#define GEN_LDX(width, opc2, opc3, type) \  
2824 -GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ 2823 +#define GEN_LDX(name, ldop, opc2, opc3, type) \
  2824 +GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2825 { \ 2825 { \
2826 - TCGv EA = tcg_temp_new(); \ 2826 + TCGv EA = tcg_temp_new(); \
2827 gen_addr_reg_index(EA, ctx); \ 2827 gen_addr_reg_index(EA, ctx); \
2828 - gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2828 + gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2829 tcg_temp_free(EA); \ 2829 tcg_temp_free(EA); \
2830 } 2830 }
2831 2831
2832 -#define GEN_LDS(width, op, type) \  
2833 -GEN_LD(width, op | 0x20, type); \  
2834 -GEN_LDU(width, op | 0x21, type); \  
2835 -GEN_LDUX(width, 0x17, op | 0x01, type); \  
2836 -GEN_LDX(width, 0x17, op | 0x00, type) 2832 +#define GEN_LDS(name, ldop, op, type) \
  2833 +GEN_LD(name, ldop, op | 0x20, type); \
  2834 +GEN_LDU(name, ldop, op | 0x21, type); \
  2835 +GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
  2836 +GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2837 2837
2838 /* lbz lbzu lbzux lbzx */ 2838 /* lbz lbzu lbzux lbzx */
2839 -GEN_LDS(8u, 0x02, PPC_INTEGER); 2839 +GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2840 /* lha lhau lhaux lhax */ 2840 /* lha lhau lhaux lhax */
2841 -GEN_LDS(16s, 0x0A, PPC_INTEGER); 2841 +GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2842 /* lhz lhzu lhzux lhzx */ 2842 /* lhz lhzu lhzux lhzx */
2843 -GEN_LDS(16u, 0x08, PPC_INTEGER); 2843 +GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2844 /* lwz lwzu lwzux lwzx */ 2844 /* lwz lwzu lwzux lwzx */
2845 -GEN_LDS(32u, 0x00, PPC_INTEGER); 2845 +GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2846 #if defined(TARGET_PPC64) 2846 #if defined(TARGET_PPC64)
2847 /* lwaux */ 2847 /* lwaux */
2848 -GEN_LDUX(32s, 0x15, 0x0B, PPC_64B); 2848 +GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2849 /* lwax */ 2849 /* lwax */
2850 -GEN_LDX(32s, 0x15, 0x0A, PPC_64B); 2850 +GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2851 /* ldux */ 2851 /* ldux */
2852 -GEN_LDUX(64, 0x15, 0x01, PPC_64B); 2852 +GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2853 /* ldx */ 2853 /* ldx */
2854 -GEN_LDX(64, 0x15, 0x00, PPC_64B); 2854 +GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2855 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) 2855 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2856 { 2856 {
2857 TCGv EA; 2857 TCGv EA;
@@ -2911,72 +2911,72 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) @@ -2911,72 +2911,72 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2911 #endif 2911 #endif
2912 2912
2913 /*** Integer store ***/ 2913 /*** Integer store ***/
2914 -#define GEN_ST(width, opc, type) \  
2915 -GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ 2914 +#define GEN_ST(name, stop, opc, type) \
  2915 +GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2916 { \ 2916 { \
2917 - TCGv EA = tcg_temp_new(); \ 2917 + TCGv EA = tcg_temp_new(); \
2918 gen_addr_imm_index(EA, ctx, 0); \ 2918 gen_addr_imm_index(EA, ctx, 0); \
2919 - gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2919 + gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2920 tcg_temp_free(EA); \ 2920 tcg_temp_free(EA); \
2921 } 2921 }
2922 2922
2923 -#define GEN_STU(width, opc, type) \  
2924 -GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ 2923 +#define GEN_STU(name, stop, opc, type) \
  2924 +GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2925 { \ 2925 { \
2926 TCGv EA; \ 2926 TCGv EA; \
2927 if (unlikely(rA(ctx->opcode) == 0)) { \ 2927 if (unlikely(rA(ctx->opcode) == 0)) { \
2928 GEN_EXCP_INVAL(ctx); \ 2928 GEN_EXCP_INVAL(ctx); \
2929 return; \ 2929 return; \
2930 } \ 2930 } \
2931 - EA = tcg_temp_new(); \ 2931 + EA = tcg_temp_new(); \
2932 if (type == PPC_64B) \ 2932 if (type == PPC_64B) \
2933 gen_addr_imm_index(EA, ctx, 0x03); \ 2933 gen_addr_imm_index(EA, ctx, 0x03); \
2934 else \ 2934 else \
2935 gen_addr_imm_index(EA, ctx, 0); \ 2935 gen_addr_imm_index(EA, ctx, 0); \
2936 - gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2936 + gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2938 tcg_temp_free(EA); \ 2938 tcg_temp_free(EA); \
2939 } 2939 }
2940 2940
2941 -#define GEN_STUX(width, opc2, opc3, type) \  
2942 -GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ 2941 +#define GEN_STUX(name, stop, opc2, opc3, type) \
  2942 +GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2943 { \ 2943 { \
2944 TCGv EA; \ 2944 TCGv EA; \
2945 if (unlikely(rA(ctx->opcode) == 0)) { \ 2945 if (unlikely(rA(ctx->opcode) == 0)) { \
2946 GEN_EXCP_INVAL(ctx); \ 2946 GEN_EXCP_INVAL(ctx); \
2947 return; \ 2947 return; \
2948 } \ 2948 } \
2949 - EA = tcg_temp_new(); \ 2949 + EA = tcg_temp_new(); \
2950 gen_addr_reg_index(EA, ctx); \ 2950 gen_addr_reg_index(EA, ctx); \
2951 - gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2951 + gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2952 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2952 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2953 tcg_temp_free(EA); \ 2953 tcg_temp_free(EA); \
2954 } 2954 }
2955 2955
2956 -#define GEN_STX(width, opc2, opc3, type) \  
2957 -GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ 2956 +#define GEN_STX(name, stop, opc2, opc3, type) \
  2957 +GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2958 { \ 2958 { \
2959 - TCGv EA = tcg_temp_new(); \ 2959 + TCGv EA = tcg_temp_new(); \
2960 gen_addr_reg_index(EA, ctx); \ 2960 gen_addr_reg_index(EA, ctx); \
2961 - gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2961 + gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2962 tcg_temp_free(EA); \ 2962 tcg_temp_free(EA); \
2963 } 2963 }
2964 2964
2965 -#define GEN_STS(width, op, type) \  
2966 -GEN_ST(width, op | 0x20, type); \  
2967 -GEN_STU(width, op | 0x21, type); \  
2968 -GEN_STUX(width, 0x17, op | 0x01, type); \  
2969 -GEN_STX(width, 0x17, op | 0x00, type) 2965 +#define GEN_STS(name, stop, op, type) \
  2966 +GEN_ST(name, stop, op | 0x20, type); \
  2967 +GEN_STU(name, stop, op | 0x21, type); \
  2968 +GEN_STUX(name, stop, 0x17, op | 0x01, type); \
  2969 +GEN_STX(name, stop, 0x17, op | 0x00, type)
2970 2970
2971 /* stb stbu stbux stbx */ 2971 /* stb stbu stbux stbx */
2972 -GEN_STS(8, 0x06, PPC_INTEGER); 2972 +GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2973 /* sth sthu sthux sthx */ 2973 /* sth sthu sthux sthx */
2974 -GEN_STS(16, 0x0C, PPC_INTEGER); 2974 +GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2975 /* stw stwu stwux stwx */ 2975 /* stw stwu stwux stwx */
2976 -GEN_STS(32, 0x04, PPC_INTEGER); 2976 +GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2977 #if defined(TARGET_PPC64) 2977 #if defined(TARGET_PPC64)
2978 -GEN_STUX(64, 0x15, 0x05, PPC_64B);  
2979 -GEN_STX(64, 0x15, 0x04, PPC_64B); 2978 +GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
  2979 +GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2980 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) 2980 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2981 { 2981 {
2982 int rs; 2982 int rs;
@@ -3036,7 +3036,7 @@ void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) @@ -3036,7 +3036,7 @@ void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3036 tcg_gen_extu_i32_tl(t0, temp); 3036 tcg_gen_extu_i32_tl(t0, temp);
3037 tcg_temp_free_i32(temp); 3037 tcg_temp_free_i32(temp);
3038 } 3038 }
3039 -GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER); 3039 +GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3040 3040
3041 /* lwbrx */ 3041 /* lwbrx */
3042 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) 3042 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
@@ -3048,7 +3048,7 @@ void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) @@ -3048,7 +3048,7 @@ void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3048 tcg_gen_extu_i32_tl(t0, temp); 3048 tcg_gen_extu_i32_tl(t0, temp);
3049 tcg_temp_free_i32(temp); 3049 tcg_temp_free_i32(temp);
3050 } 3050 }
3051 -GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER); 3051 +GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3052 3052
3053 /* sthbrx */ 3053 /* sthbrx */
3054 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) 3054 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
@@ -3063,7 +3063,7 @@ void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) @@ -3063,7 +3063,7 @@ void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3063 gen_qemu_st16(t2, t1, flags); 3063 gen_qemu_st16(t2, t1, flags);
3064 tcg_temp_free(t2); 3064 tcg_temp_free(t2);
3065 } 3065 }
3066 -GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER); 3066 +GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3067 3067
3068 /* stwbrx */ 3068 /* stwbrx */
3069 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) 3069 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
@@ -3077,7 +3077,7 @@ void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) @@ -3077,7 +3077,7 @@ void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3077 gen_qemu_st32(t2, t1, flags); 3077 gen_qemu_st32(t2, t1, flags);
3078 tcg_temp_free(t2); 3078 tcg_temp_free(t2);
3079 } 3079 }
3080 -GEN_STX(32r, 0x16, 0x14, PPC_INTEGER); 3080 +GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3081 3081
3082 /*** Integer load and store multiple ***/ 3082 /*** Integer load and store multiple ***/
3083 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) 3083 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)