gwj / at91sam9263 · Commits

Commit 0c34a5d72228e6d6cb0c1eb2797cfa4c68c5292b

Authored by aurel32
1 parent fd69fe2b

target-ppc: kill a few warnings 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 6 additions and 4 deletions
hw/ppc4xx_pci.c
  View file @0c34a5d
@@ -21,6 +21,8 @@ @@ -21,6 +21,8 @@
21 * 4xx SoCs, such as the 440EP. */ 21 * 4xx SoCs, such as the 440EP. */
22 22
23 #include "hw.h" 23 #include "hw.h"
  24 +#include "ppc.h"
  25 +#include "ppc4xx.h"
24 26
25 typedef target_phys_addr_t pci_addr_t; 27 typedef target_phys_addr_t pci_addr_t;
26 #include "pci.h" 28 #include "pci.h"
target-ppc/translate.c
  View file @0c34a5d
@@ -3024,7 +3024,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -3024,7 +3024,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3024 #endif 3024 #endif
3025 /*** Integer load and store with byte reverse ***/ 3025 /*** Integer load and store with byte reverse ***/
3026 /* lhbrx */ 3026 /* lhbrx */
3027 -void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) 3027 +static void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3028 { 3028 {
3029 TCGv_i32 temp = tcg_temp_new_i32(); 3029 TCGv_i32 temp = tcg_temp_new_i32();
3030 gen_qemu_ld16u(t0, t1, flags); 3030 gen_qemu_ld16u(t0, t1, flags);
@@ -3036,7 +3036,7 @@ void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) @@ -3036,7 +3036,7 @@ void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3036 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3036 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3037 3037
3038 /* lwbrx */ 3038 /* lwbrx */
3039 -void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) 3039 +static void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3040 { 3040 {
3041 TCGv_i32 temp = tcg_temp_new_i32(); 3041 TCGv_i32 temp = tcg_temp_new_i32();
3042 gen_qemu_ld32u(t0, t1, flags); 3042 gen_qemu_ld32u(t0, t1, flags);
@@ -3048,7 +3048,7 @@ void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) @@ -3048,7 +3048,7 @@ void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3048 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3048 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3049 3049
3050 /* sthbrx */ 3050 /* sthbrx */
3051 -void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) 3051 +static void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3052 { 3052 {
3053 TCGv_i32 temp = tcg_temp_new_i32(); 3053 TCGv_i32 temp = tcg_temp_new_i32();
3054 TCGv t2 = tcg_temp_new(); 3054 TCGv t2 = tcg_temp_new();
@@ -3063,7 +3063,7 @@ void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) @@ -3063,7 +3063,7 @@ void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3063 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3063 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3064 3064
3065 /* stwbrx */ 3065 /* stwbrx */
3066 -void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) 3066 +static void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3067 { 3067 {
3068 TCGv_i32 temp = tcg_temp_new_i32(); 3068 TCGv_i32 temp = tcg_temp_new_i32();
3069 TCGv t2 = tcg_temp_new(); 3069 TCGv t2 = tcg_temp_new();