gwj / at91sam9263 · Commits

Commit 0b74ed78ef3879af7f32bb31693d9e3e71d4b5dd

Authored by bellard
1 parent f51589da

mode 4 and 5 write fix (Magnus Damn) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1241 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 9 additions and 7 deletions
hw/cirrus_vga.c
  View file @0b74ed7
@@ -790,7 +790,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s) @@ -790,7 +790,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
790 blt_rop = s->gr[0x32]; 790 blt_rop = s->gr[0x32];
791 791
792 #ifdef DEBUG_BITBLT 792 #ifdef DEBUG_BITBLT
793 - printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spicth=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", 793 + printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
794 blt_rop, 794 blt_rop,
795 s->cirrus_blt_mode, 795 s->cirrus_blt_mode,
796 s->cirrus_blt_modeext, 796 s->cirrus_blt_modeext,
@@ -1780,11 +1780,12 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, @@ -1780,11 +1780,12 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1780 dst = s->vram_ptr + offset; 1780 dst = s->vram_ptr + offset;
1781 for (x = 0; x < 8; x++) { 1781 for (x = 0; x < 8; x++) {
1782 if (val & 0x80) { 1782 if (val & 0x80) {
1783 - *dst++ = s->cirrus_shadow_gr1; 1783 + *dst = s->cirrus_shadow_gr1;
1784 } else if (mode == 5) { 1784 } else if (mode == 5) {
1785 - *dst++ = s->cirrus_shadow_gr0; 1785 + *dst = s->cirrus_shadow_gr0;
1786 } 1786 }
1787 val <<= 1; 1787 val <<= 1;
  1788 + dst++;
1788 } 1789 }
1789 cpu_physical_memory_set_dirty(s->vram_offset + offset); 1790 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1790 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7); 1791 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
@@ -1802,13 +1803,14 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, @@ -1802,13 +1803,14 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1802 dst = s->vram_ptr + offset; 1803 dst = s->vram_ptr + offset;
1803 for (x = 0; x < 8; x++) { 1804 for (x = 0; x < 8; x++) {
1804 if (val & 0x80) { 1805 if (val & 0x80) {
1805 - *dst++ = s->cirrus_shadow_gr1;  
1806 - *dst++ = s->gr[0x11]; 1806 + *dst = s->cirrus_shadow_gr1;
  1807 + *(dst + 1) = s->gr[0x11];
1807 } else if (mode == 5) { 1808 } else if (mode == 5) {
1808 - *dst++ = s->cirrus_shadow_gr0;  
1809 - *dst++ = s->gr[0x10]; 1809 + *dst = s->cirrus_shadow_gr0;
  1810 + *(dst + 1) = s->gr[0x10];
1810 } 1811 }
1811 val <<= 1; 1812 val <<= 1;
  1813 + dst += 2;
1812 } 1814 }
1813 cpu_physical_memory_set_dirty(s->vram_offset + offset); 1815 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1814 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15); 1816 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);