gwj / at91sam9263 · Commits

Commit 09a79b4974fbeee660660d79ab45bd37ec416741

Authored by bellard
1 parent 64201201

partial big endian fixes - change VESA VBE ports for non i386 targets to avoid unaligned accesses 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@866 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 63 additions and 27 deletions
hw/vga.c
  View file @09a79b4
... ... @@ -489,34 +489,40 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
489 489 }
490 490  
491 491 #ifdef CONFIG_BOCHS_VBE
492   -static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)
  492 +static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
493 493 {
494 494 VGAState *s = opaque;
495 495 uint32_t val;
  496 + val = s->vbe_index;
  497 + return val;
  498 +}
496 499  
497   - addr &= 1;
498   - if (addr == 0) {
499   - val = s->vbe_index;
500   - } else {
501   - if (s->vbe_index <= VBE_DISPI_INDEX_NB)
502   - val = s->vbe_regs[s->vbe_index];
503   - else
504   - val = 0;
  500 +static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
  501 +{
  502 + VGAState *s = opaque;
  503 + uint32_t val;
  504 +
  505 + if (s->vbe_index <= VBE_DISPI_INDEX_NB)
  506 + val = s->vbe_regs[s->vbe_index];
  507 + else
  508 + val = 0;
505 509 #ifdef DEBUG_BOCHS_VBE
506   - printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
  510 + printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
507 511 #endif
508   - }
509 512 return val;
510 513 }
511 514  
512   -static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
  515 +static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
  516 +{
  517 + VGAState *s = opaque;
  518 + s->vbe_index = val;
  519 +}
  520 +
  521 +static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
513 522 {
514 523 VGAState *s = opaque;
515 524  
516   - addr &= 1;
517   - if (addr == 0) {
518   - s->vbe_index = val;
519   - } else if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
  525 + if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
520 526 #ifdef DEBUG_BOCHS_VBE
521 527 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
522 528 #endif
... ... @@ -709,18 +715,30 @@ static uint32_t vga_mem_readb(target_phys_addr_t addr)
709 715 static uint32_t vga_mem_readw(target_phys_addr_t addr)
710 716 {
711 717 uint32_t v;
  718 +#ifdef TARGET_WORDS_BIGENDIAN
  719 + v = vga_mem_readb(addr) << 8;
  720 + v |= vga_mem_readb(addr + 1);
  721 +#else
712 722 v = vga_mem_readb(addr);
713 723 v |= vga_mem_readb(addr + 1) << 8;
  724 +#endif
714 725 return v;
715 726 }
716 727  
717 728 static uint32_t vga_mem_readl(target_phys_addr_t addr)
718 729 {
719 730 uint32_t v;
  731 +#ifdef TARGET_WORDS_BIGENDIAN
  732 + v = vga_mem_readb(addr) << 24;
  733 + v |= vga_mem_readb(addr + 1) << 16;
  734 + v |= vga_mem_readb(addr + 2) << 8;
  735 + v |= vga_mem_readb(addr + 3);
  736 +#else
720 737 v = vga_mem_readb(addr);
721 738 v |= vga_mem_readb(addr + 1) << 8;
722 739 v |= vga_mem_readb(addr + 2) << 16;
723 740 v |= vga_mem_readb(addr + 3) << 24;
  741 +#endif
724 742 return v;
725 743 }
726 744  
... ... @@ -855,16 +873,28 @@ static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
855 873  
856 874 static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
857 875 {
  876 +#ifdef TARGET_WORDS_BIGENDIAN
  877 + vga_mem_writeb(addr, (val >> 8) & 0xff);
  878 + vga_mem_writeb(addr + 1, val & 0xff);
  879 +#else
858 880 vga_mem_writeb(addr, val & 0xff);
859 881 vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
  882 +#endif
860 883 }
861 884  
862 885 static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
863 886 {
  887 +#ifdef TARGET_WORDS_BIGENDIAN
  888 + vga_mem_writeb(addr, (val >> 24) & 0xff);
  889 + vga_mem_writeb(addr + 1, (val >> 16) & 0xff);
  890 + vga_mem_writeb(addr + 2, (val >> 8) & 0xff);
  891 + vga_mem_writeb(addr + 3, val & 0xff);
  892 +#else
864 893 vga_mem_writeb(addr, val & 0xff);
865 894 vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
866 895 vga_mem_writeb(addr + 2, (val >> 16) & 0xff);
867 896 vga_mem_writeb(addr + 3, (val >> 24) & 0xff);
  897 +#endif
868 898 }
869 899  
870 900 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
... ... @@ -1366,7 +1396,7 @@ static void vga_draw_graphic(VGAState *s, int full_update)
1366 1396 ((s->cr[0x07] & 0x40) << 3);
1367 1397 height = (height + 1);
1368 1398 disp_width = width;
1369   -
  1399 +
1370 1400 shift_control = (s->gr[0x05] >> 5) & 3;
1371 1401 double_scan = (s->cr[0x09] & 0x80);
1372 1402 if (shift_control > 1) {
... ... @@ -1774,19 +1804,27 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
1774 1804 #ifdef CONFIG_BOCHS_VBE
1775 1805 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1776 1806 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
1777   - register_ioport_read(0x1ce, 1, 2, vbe_ioport_read, s);
1778   - register_ioport_read(0x1cf, 1, 2, vbe_ioport_read, s);
  1807 +#if defined (TARGET_I386)
  1808 + register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
  1809 + register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
1779 1810  
1780   - register_ioport_write(0x1ce, 1, 2, vbe_ioport_write, s);
1781   - register_ioport_write(0x1cf, 1, 2, vbe_ioport_write, s);
  1811 + register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
  1812 + register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
1782 1813  
1783 1814 /* old Bochs IO ports */
1784   - register_ioport_read(0xff80, 1, 2, vbe_ioport_read, s);
1785   - register_ioport_read(0xff81, 1, 2, vbe_ioport_read, s);
  1815 + register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
  1816 + register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
1786 1817  
1787   - register_ioport_write(0xff80, 1, 2, vbe_ioport_write, s);
1788   - register_ioport_write(0xff81, 1, 2, vbe_ioport_write, s);
  1818 + register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
  1819 + register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
  1820 +#else
  1821 + register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
  1822 + register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
  1823 +
  1824 + register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
  1825 + register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
1789 1826 #endif
  1827 +#endif /* CONFIG_BOCHS_VBE */
1790 1828  
1791 1829 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
1792 1830 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
... ... @@ -1814,12 +1852,10 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
1814 1852 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
1815 1853 } else {
1816 1854 #ifdef CONFIG_BOCHS_VBE
1817   -#if defined (TARGET_I386)
1818 1855 /* XXX: use optimized standard vga accesses */
1819 1856 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1820 1857 vga_ram_size, vga_ram_offset);
1821 1858 #endif
1822   -#endif
1823 1859 }
1824 1860 return 0;
1825 1861 }
... ...