gwj / at91sam9263 · Commits

Commit 08fa4bab833f834e1511853dd2331fa3d6d5d469

Authored by ths
1 parent fe253235

hflags computation cleanup, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3243 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 32 additions and 62 deletions
target-mips/exec.h
  View file @08fa4ba
@@ -243,7 +243,8 @@ static inline void regs_to_env(void) @@ -243,7 +243,8 @@ static inline void regs_to_env(void)
243 { 243 {
244 } 244 }
245 245
246 -static inline int cpu_halted(CPUState *env) { 246 +static inline int cpu_halted(CPUState *env)
  247 +{
247 if (!env->halted) 248 if (!env->halted)
248 return 0; 249 return 0;
249 if (env->interrupt_request & 250 if (env->interrupt_request &
@@ -254,4 +255,27 @@ static inline int cpu_halted(CPUState *env) { @@ -254,4 +255,27 @@ static inline int cpu_halted(CPUState *env) {
254 return EXCP_HALTED; 255 return EXCP_HALTED;
255 } 256 }
256 257
  258 +static inline void compute_hflags(CPUState *env)
  259 +{
  260 + env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
  261 + MIPS_HFLAG_FPU | MIPS_HFLAG_UM);
  262 + if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
  263 + !(env->CP0_Status & (1 << CP0St_ERL)) &&
  264 + !(env->hflags & MIPS_HFLAG_DM) &&
  265 + (env->CP0_Status & (1 << CP0St_UM)))
  266 + env->hflags |= MIPS_HFLAG_UM;
  267 +#ifdef TARGET_MIPS64
  268 + if (!(env->hflags & MIPS_HFLAG_UM) ||
  269 + (env->CP0_Status & (1 << CP0St_PX)) ||
  270 + (env->CP0_Status & (1 << CP0St_UX)))
  271 + env->hflags |= MIPS_HFLAG_64;
  272 +#endif
  273 + if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
  274 + env->hflags |= MIPS_HFLAG_CP0;
  275 + if (env->CP0_Status & (1 << CP0St_CU1))
  276 + env->hflags |= MIPS_HFLAG_FPU;
  277 + if (env->CP0_Status & (1 << CP0St_FR))
  278 + env->hflags |= MIPS_HFLAG_F64;
  279 +}
  280 +
257 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ 281 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */
target-mips/helper.c
  View file @08fa4ba
@@ -368,10 +368,8 @@ void do_interrupt (CPUState *env) @@ -368,10 +368,8 @@ void do_interrupt (CPUState *env)
368 env->CP0_DEPC = env->PC[env->current_tc]; 368 env->CP0_DEPC = env->PC[env->current_tc];
369 } 369 }
370 enter_debug_mode: 370 enter_debug_mode:
371 - env->hflags |= MIPS_HFLAG_DM;  
372 - env->hflags |= MIPS_HFLAG_64; 371 + env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
373 env->hflags &= ~MIPS_HFLAG_UM; 372 env->hflags &= ~MIPS_HFLAG_UM;
374 - env->hflags |= MIPS_HFLAG_CP0;  
375 /* EJTAG probe trap enable is not implemented... */ 373 /* EJTAG probe trap enable is not implemented... */
376 if (!(env->CP0_Status & (1 << CP0St_EXL))) 374 if (!(env->CP0_Status & (1 << CP0St_EXL)))
377 env->CP0_Cause &= ~(1 << CP0Ca_BD); 375 env->CP0_Cause &= ~(1 << CP0Ca_BD);
@@ -396,9 +394,8 @@ void do_interrupt (CPUState *env) @@ -396,9 +394,8 @@ void do_interrupt (CPUState *env)
396 env->CP0_ErrorEPC = env->PC[env->current_tc]; 394 env->CP0_ErrorEPC = env->PC[env->current_tc];
397 } 395 }
398 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); 396 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
399 - env->hflags |= MIPS_HFLAG_64; 397 + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
400 env->hflags &= ~MIPS_HFLAG_UM; 398 env->hflags &= ~MIPS_HFLAG_UM;
401 - env->hflags |= MIPS_HFLAG_CP0;  
402 if (!(env->CP0_Status & (1 << CP0St_EXL))) 399 if (!(env->CP0_Status & (1 << CP0St_EXL)))
403 env->CP0_Cause &= ~(1 << CP0Ca_BD); 400 env->CP0_Cause &= ~(1 << CP0Ca_BD);
404 env->PC[env->current_tc] = (int32_t)0xBFC00000; 401 env->PC[env->current_tc] = (int32_t)0xBFC00000;
@@ -499,9 +496,8 @@ void do_interrupt (CPUState *env) @@ -499,9 +496,8 @@ void do_interrupt (CPUState *env)
499 env->CP0_Cause &= ~(1 << CP0Ca_BD); 496 env->CP0_Cause &= ~(1 << CP0Ca_BD);
500 } 497 }
501 env->CP0_Status |= (1 << CP0St_EXL); 498 env->CP0_Status |= (1 << CP0St_EXL);
502 - env->hflags |= MIPS_HFLAG_64; 499 + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
503 env->hflags &= ~MIPS_HFLAG_UM; 500 env->hflags &= ~MIPS_HFLAG_UM;
504 - env->hflags |= MIPS_HFLAG_CP0;  
505 } 501 }
506 env->hflags &= ~MIPS_HFLAG_BMASK; 502 env->hflags &= ~MIPS_HFLAG_BMASK;
507 if (env->CP0_Status & (1 << CP0St_BEV)) { 503 if (env->CP0_Status & (1 << CP0St_BEV)) {
target-mips/op.c
  View file @08fa4ba
@@ -1841,30 +1841,8 @@ void op_mtc0_status (void) @@ -1841,30 +1841,8 @@ void op_mtc0_status (void)
1841 1841
1842 val = T0 & mask; 1842 val = T0 & mask;
1843 old = env->CP0_Status; 1843 old = env->CP0_Status;
1844 - if (!(val & (1 << CP0St_EXL)) &&  
1845 - !(val & (1 << CP0St_ERL)) &&  
1846 - !(env->hflags & MIPS_HFLAG_DM) &&  
1847 - (val & (1 << CP0St_UM)))  
1848 - env->hflags |= MIPS_HFLAG_UM;  
1849 -#ifdef TARGET_MIPS64  
1850 - if ((env->hflags & MIPS_HFLAG_UM) &&  
1851 - !(val & (1 << CP0St_PX)) &&  
1852 - !(val & (1 << CP0St_UX)))  
1853 - env->hflags &= ~MIPS_HFLAG_64;  
1854 -#endif  
1855 - if ((val & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))  
1856 - env->hflags |= MIPS_HFLAG_CP0;  
1857 - else  
1858 - env->hflags &= ~MIPS_HFLAG_CP0;  
1859 - if (val & (1 << CP0St_CU1))  
1860 - env->hflags |= MIPS_HFLAG_FPU;  
1861 - else  
1862 - env->hflags &= ~MIPS_HFLAG_FPU;  
1863 - if (val & (1 << CP0St_FR))  
1864 - env->hflags |= MIPS_HFLAG_F64;  
1865 - else  
1866 - env->hflags &= ~MIPS_HFLAG_F64;  
1867 env->CP0_Status = (env->CP0_Status & ~mask) | val; 1844 env->CP0_Status = (env->CP0_Status & ~mask) | val;
  1845 + CALL_FROM_TB1(compute_hflags, env);
1868 if (loglevel & CPU_LOG_EXEC) 1846 if (loglevel & CPU_LOG_EXEC)
1869 CALL_FROM_TB2(do_mtc0_status_debug, old, val); 1847 CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1870 CALL_FROM_TB1(cpu_mips_update_irq, env); 1848 CALL_FROM_TB1(cpu_mips_update_irq, env);
@@ -3009,21 +2987,7 @@ void op_eret (void) @@ -3009,21 +2987,7 @@ void op_eret (void)
3009 env->PC[env->current_tc] = env->CP0_EPC; 2987 env->PC[env->current_tc] = env->CP0_EPC;
3010 env->CP0_Status &= ~(1 << CP0St_EXL); 2988 env->CP0_Status &= ~(1 << CP0St_EXL);
3011 } 2989 }
3012 - if (!(env->CP0_Status & (1 << CP0St_EXL)) &&  
3013 - !(env->CP0_Status & (1 << CP0St_ERL)) &&  
3014 - !(env->hflags & MIPS_HFLAG_DM) &&  
3015 - (env->CP0_Status & (1 << CP0St_UM)))  
3016 - env->hflags |= MIPS_HFLAG_UM;  
3017 -#ifdef TARGET_MIPS64  
3018 - if ((env->hflags & MIPS_HFLAG_UM) &&  
3019 - !(env->CP0_Status & (1 << CP0St_PX)) &&  
3020 - !(env->CP0_Status & (1 << CP0St_UX)))  
3021 - env->hflags &= ~MIPS_HFLAG_64;  
3022 -#endif  
3023 - if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))  
3024 - env->hflags |= MIPS_HFLAG_CP0;  
3025 - else  
3026 - env->hflags &= ~MIPS_HFLAG_CP0; 2990 + CALL_FROM_TB1(compute_hflags, env);
3027 if (loglevel & CPU_LOG_EXEC) 2991 if (loglevel & CPU_LOG_EXEC)
3028 CALL_FROM_TB0(debug_post_eret); 2992 CALL_FROM_TB0(debug_post_eret);
3029 env->CP0_LLAddr = 1; 2993 env->CP0_LLAddr = 1;
@@ -3035,22 +2999,8 @@ void op_deret (void) @@ -3035,22 +2999,8 @@ void op_deret (void)
3035 if (loglevel & CPU_LOG_EXEC) 2999 if (loglevel & CPU_LOG_EXEC)
3036 CALL_FROM_TB0(debug_pre_eret); 3000 CALL_FROM_TB0(debug_pre_eret);
3037 env->PC[env->current_tc] = env->CP0_DEPC; 3001 env->PC[env->current_tc] = env->CP0_DEPC;
3038 - env->hflags |= MIPS_HFLAG_DM;  
3039 - if (!(env->CP0_Status & (1 << CP0St_EXL)) &&  
3040 - !(env->CP0_Status & (1 << CP0St_ERL)) &&  
3041 - !(env->hflags & MIPS_HFLAG_DM) &&  
3042 - (env->CP0_Status & (1 << CP0St_UM)))  
3043 - env->hflags |= MIPS_HFLAG_UM;  
3044 -#ifdef TARGET_MIPS64  
3045 - if ((env->hflags & MIPS_HFLAG_UM) &&  
3046 - !(env->CP0_Status & (1 << CP0St_PX)) &&  
3047 - !(env->CP0_Status & (1 << CP0St_UX)))  
3048 - env->hflags &= ~MIPS_HFLAG_64;  
3049 -#endif  
3050 - if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))  
3051 - env->hflags |= MIPS_HFLAG_CP0;  
3052 - else  
3053 - env->hflags &= ~MIPS_HFLAG_CP0; 3002 + env->hflags &= MIPS_HFLAG_DM;
  3003 + CALL_FROM_TB1(compute_hflags, env);
3054 if (loglevel & CPU_LOG_EXEC) 3004 if (loglevel & CPU_LOG_EXEC)
3055 CALL_FROM_TB0(debug_post_eret); 3005 CALL_FROM_TB0(debug_post_eret);
3056 env->CP0_LLAddr = 1; 3006 env->CP0_LLAddr = 1;