Commit 08e489025b49bb0d9e3781643772e35c445a21b2
1 parent
c326e0af
removed obsolete S3 VGA code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1386 c046a42c-6fe2-441c-8c8c-71466251a162
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62 deletions
hw/vga.c
| @@ -28,12 +28,8 @@ | @@ -28,12 +28,8 @@ | ||
| 28 | //#define DEBUG_VGA_MEM | 28 | //#define DEBUG_VGA_MEM |
| 29 | //#define DEBUG_VGA_REG | 29 | //#define DEBUG_VGA_REG |
| 30 | 30 | ||
| 31 | -//#define DEBUG_S3 | ||
| 32 | //#define DEBUG_BOCHS_VBE | 31 | //#define DEBUG_BOCHS_VBE |
| 33 | 32 | ||
| 34 | -/* S3 VGA is deprecated - another graphic card will be emulated */ | ||
| 35 | -//#define CONFIG_S3VGA | ||
| 36 | - | ||
| 37 | /* force some bits to zero */ | 33 | /* force some bits to zero */ |
| 38 | const uint8_t sr_mask[8] = { | 34 | const uint8_t sr_mask[8] = { |
| 39 | (uint8_t)~0xfc, | 35 | (uint8_t)~0xfc, |
| @@ -225,11 +221,6 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr) | @@ -225,11 +221,6 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr) | ||
| 225 | #ifdef DEBUG_VGA_REG | 221 | #ifdef DEBUG_VGA_REG |
| 226 | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); | 222 | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); |
| 227 | #endif | 223 | #endif |
| 228 | -#ifdef DEBUG_S3 | ||
| 229 | - if (s->cr_index >= 0x20) | ||
| 230 | - printf("S3: CR read index=0x%x val=0x%x\n", | ||
| 231 | - s->cr_index, val); | ||
| 232 | -#endif | ||
| 233 | break; | 224 | break; |
| 234 | case 0x3ba: | 225 | case 0x3ba: |
| 235 | case 0x3da: | 226 | case 0x3da: |
| @@ -359,43 +350,10 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | @@ -359,43 +350,10 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | ||
| 359 | case 0x12: /* veritcal display end */ | 350 | case 0x12: /* veritcal display end */ |
| 360 | s->cr[s->cr_index] = val; | 351 | s->cr[s->cr_index] = val; |
| 361 | break; | 352 | break; |
| 362 | - | ||
| 363 | -#ifdef CONFIG_S3VGA | ||
| 364 | - /* S3 registers */ | ||
| 365 | - case 0x2d: | ||
| 366 | - case 0x2e: | ||
| 367 | - case 0x2f: | ||
| 368 | - case 0x30: | ||
| 369 | - /* chip ID, cannot write */ | ||
| 370 | - break; | ||
| 371 | - case 0x31: | ||
| 372 | - /* update start address */ | ||
| 373 | - { | ||
| 374 | - int v; | ||
| 375 | - s->cr[s->cr_index] = val; | ||
| 376 | - v = (val >> 4) & 3; | ||
| 377 | - s->cr[0x69] = (s->cr[69] & ~0x03) | v; | ||
| 378 | - } | ||
| 379 | - break; | ||
| 380 | - case 0x51: | ||
| 381 | - /* update start address */ | ||
| 382 | - { | ||
| 383 | - int v; | ||
| 384 | - s->cr[s->cr_index] = val; | ||
| 385 | - v = val & 3; | ||
| 386 | - s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2); | ||
| 387 | - } | ||
| 388 | - break; | ||
| 389 | -#endif | ||
| 390 | default: | 353 | default: |
| 391 | s->cr[s->cr_index] = val; | 354 | s->cr[s->cr_index] = val; |
| 392 | break; | 355 | break; |
| 393 | } | 356 | } |
| 394 | -#ifdef DEBUG_S3 | ||
| 395 | - if (s->cr_index >= 0x20) | ||
| 396 | - printf("S3: CR write index=0x%x val=0x%x\n", | ||
| 397 | - s->cr_index, val); | ||
| 398 | -#endif | ||
| 399 | break; | 357 | break; |
| 400 | case 0x3ba: | 358 | case 0x3ba: |
| 401 | case 0x3da: | 359 | case 0x3da: |
| @@ -954,22 +912,10 @@ static void vga_get_offsets(VGAState *s, | @@ -954,22 +912,10 @@ static void vga_get_offsets(VGAState *s, | ||
| 954 | { | 912 | { |
| 955 | /* compute line_offset in bytes */ | 913 | /* compute line_offset in bytes */ |
| 956 | line_offset = s->cr[0x13]; | 914 | line_offset = s->cr[0x13]; |
| 957 | -#ifdef CONFIG_S3VGA | ||
| 958 | - { | ||
| 959 | - uinr32_t v; | ||
| 960 | - v = (s->cr[0x51] >> 4) & 3; /* S3 extension */ | ||
| 961 | - if (v == 0) | ||
| 962 | - v = (s->cr[0x43] >> 2) & 1; /* S3 extension */ | ||
| 963 | - line_offset |= (v << 8); | ||
| 964 | - } | ||
| 965 | -#endif | ||
| 966 | line_offset <<= 3; | 915 | line_offset <<= 3; |
| 967 | - | 916 | + |
| 968 | /* starting address */ | 917 | /* starting address */ |
| 969 | start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8); | 918 | start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8); |
| 970 | -#ifdef CONFIG_S3VGA | ||
| 971 | - start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */ | ||
| 972 | -#endif | ||
| 973 | } | 919 | } |
| 974 | *pline_offset = line_offset; | 920 | *pline_offset = line_offset; |
| 975 | *pstart_addr = start_addr; | 921 | *pstart_addr = start_addr; |
| @@ -1597,13 +1543,6 @@ void vga_invalidate_display(void) | @@ -1597,13 +1543,6 @@ void vga_invalidate_display(void) | ||
| 1597 | static void vga_reset(VGAState *s) | 1543 | static void vga_reset(VGAState *s) |
| 1598 | { | 1544 | { |
| 1599 | memset(s, 0, sizeof(VGAState)); | 1545 | memset(s, 0, sizeof(VGAState)); |
| 1600 | -#ifdef CONFIG_S3VGA | ||
| 1601 | - /* chip ID for 8c968 */ | ||
| 1602 | - s->cr[0x2d] = 0x88; | ||
| 1603 | - s->cr[0x2e] = 0xb0; | ||
| 1604 | - s->cr[0x2f] = 0x01; /* XXX: check revision code */ | ||
| 1605 | - s->cr[0x30] = 0xe1; | ||
| 1606 | -#endif | ||
| 1607 | s->graphic_mode = -1; /* force full update */ | 1546 | s->graphic_mode = -1; /* force full update */ |
| 1608 | } | 1547 | } |
| 1609 | 1548 |