Commit 08ba79632f106a14c981f888a3feaedf6c576fcf

Authored by ths
1 parent 2681b45a

TCGify a few more instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4736 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips/exec.h
@@ -78,7 +78,6 @@ void fpu_dump_state(CPUState *env, FILE *f, @@ -78,7 +78,6 @@ void fpu_dump_state(CPUState *env, FILE *f,
78 int (*fpu_fprintf)(FILE *f, const char *fmt, ...), 78 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
79 int flags); 79 int flags);
80 void dump_sc (void); 80 void dump_sc (void);
81 -void do_pmon (int function);  
82 81
83 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, 82 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
84 int mmu_idx, int is_softmmu); 83 int mmu_idx, int is_softmmu);
target-mips/helper.h
@@ -202,3 +202,7 @@ FOP_PROTO(nge) @@ -202,3 +202,7 @@ FOP_PROTO(nge)
202 FOP_PROTO(le) 202 FOP_PROTO(le)
203 FOP_PROTO(ngt) 203 FOP_PROTO(ngt)
204 #undef FOP_PROTO 204 #undef FOP_PROTO
  205 +
  206 +/* Special functions */
  207 +DEF_HELPER(void, do_pmon, (int function))
  208 +DEF_HELPER(void, do_wait, (void))
target-mips/op.c
@@ -651,18 +651,6 @@ FLOAT_OP(alnv, ps) @@ -651,18 +651,6 @@ FLOAT_OP(alnv, ps)
651 FORCE_RET(); 651 FORCE_RET();
652 } 652 }
653 653
654 -#ifdef CONFIG_SOFTFLOAT  
655 -#define clear_invalid() do { \  
656 - int flags = get_float_exception_flags(&env->fpu->fp_status); \  
657 - flags &= ~float_flag_invalid; \  
658 - set_float_exception_flags(flags, &env->fpu->fp_status); \  
659 -} while(0)  
660 -#else  
661 -#define clear_invalid() do { } while(0)  
662 -#endif  
663 -  
664 -extern void dump_fpu_s(CPUState *env);  
665 -  
666 void op_bc1f (void) 654 void op_bc1f (void)
667 { 655 {
668 T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1)); 656 T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
@@ -701,44 +689,7 @@ void op_bc1any4t (void) @@ -701,44 +689,7 @@ void op_bc1any4t (void)
701 FORCE_RET(); 689 FORCE_RET();
702 } 690 }
703 691
704 -void op_tlbwi (void)  
705 -{  
706 - CALL_FROM_TB0(env->tlb->do_tlbwi);  
707 - FORCE_RET();  
708 -}  
709 -  
710 -void op_tlbwr (void)  
711 -{  
712 - CALL_FROM_TB0(env->tlb->do_tlbwr);  
713 - FORCE_RET();  
714 -}  
715 -  
716 -void op_tlbp (void)  
717 -{  
718 - CALL_FROM_TB0(env->tlb->do_tlbp);  
719 - FORCE_RET();  
720 -}  
721 -  
722 -void op_tlbr (void)  
723 -{  
724 - CALL_FROM_TB0(env->tlb->do_tlbr);  
725 - FORCE_RET();  
726 -}  
727 -  
728 /* Specials */ 692 /* Specials */
729 -#if defined (CONFIG_USER_ONLY)  
730 -void op_tls_value (void)  
731 -{  
732 - T0 = env->tls_value;  
733 -}  
734 -#endif  
735 -  
736 -void op_pmon (void)  
737 -{  
738 - CALL_FROM_TB1(do_pmon, PARAM1);  
739 - FORCE_RET();  
740 -}  
741 -  
742 void op_di (void) 693 void op_di (void)
743 { 694 {
744 T0 = env->CP0_Status; 695 T0 = env->CP0_Status;
@@ -755,20 +706,6 @@ void op_ei (void) @@ -755,20 +706,6 @@ void op_ei (void)
755 FORCE_RET(); 706 FORCE_RET();
756 } 707 }
757 708
758 -void op_trap (void)  
759 -{  
760 - if (T0) {  
761 - CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);  
762 - }  
763 - FORCE_RET();  
764 -}  
765 -  
766 -void op_debug (void)  
767 -{  
768 - CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);  
769 - FORCE_RET();  
770 -}  
771 -  
772 void debug_pre_eret (void); 709 void debug_pre_eret (void);
773 void debug_post_eret (void); 710 void debug_post_eret (void);
774 void op_eret (void) 711 void op_eret (void)
@@ -842,19 +779,6 @@ void op_rdhwr_ccres(void) @@ -842,19 +779,6 @@ void op_rdhwr_ccres(void)
842 FORCE_RET(); 779 FORCE_RET();
843 } 780 }
844 781
845 -void op_save_state (void)  
846 -{  
847 - env->hflags = PARAM1;  
848 - FORCE_RET();  
849 -}  
850 -  
851 -void op_wait (void)  
852 -{  
853 - env->halted = 1;  
854 - CALL_FROM_TB1(do_raise_exception, EXCP_HLT);  
855 - FORCE_RET();  
856 -}  
857 -  
858 /* Bitfield operations. */ 782 /* Bitfield operations. */
859 void op_ext(void) 783 void op_ext(void)
860 { 784 {
target-mips/op_helper.c
@@ -1401,6 +1401,12 @@ void do_pmon (int function) @@ -1401,6 +1401,12 @@ void do_pmon (int function)
1401 } 1401 }
1402 } 1402 }
1403 1403
  1404 +void do_wait (void)
  1405 +{
  1406 + env->halted = 1;
  1407 + do_raise_exception(EXCP_HLT);
  1408 +}
  1409 +
1404 #if !defined(CONFIG_USER_ONLY) 1410 #if !defined(CONFIG_USER_ONLY)
1405 1411
1406 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); 1412 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
target-mips/translate.c
@@ -789,7 +789,11 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc) @@ -789,7 +789,11 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
789 ctx->saved_pc = ctx->pc; 789 ctx->saved_pc = ctx->pc;
790 } 790 }
791 if (ctx->hflags != ctx->saved_hflags) { 791 if (ctx->hflags != ctx->saved_hflags) {
792 - gen_op_save_state(ctx->hflags); 792 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  793 +
  794 + tcg_gen_movi_i32(r_tmp, ctx->hflags);
  795 + tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
  796 + tcg_temp_free(r_tmp);
793 ctx->saved_hflags = ctx->hflags; 797 ctx->saved_hflags = ctx->hflags;
794 switch (ctx->hflags & MIPS_HFLAG_BMASK) { 798 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
795 case MIPS_HFLAG_BR: 799 case MIPS_HFLAG_BR:
@@ -2238,7 +2242,13 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2238,7 +2242,13 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2238 } 2242 }
2239 } 2243 }
2240 save_cpu_state(ctx, 1); 2244 save_cpu_state(ctx, 1);
2241 - gen_op_trap(); 2245 + {
  2246 + int l1 = gen_new_label();
  2247 +
  2248 + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
  2249 + tcg_gen_helper_0_1i(do_raise_exception, EXCP_TRAP);
  2250 + gen_set_label(l1);
  2251 + }
2242 ctx->bstate = BS_STOP; 2252 ctx->bstate = BS_STOP;
2243 } 2253 }
2244 2254
@@ -5316,25 +5326,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5316,25 +5326,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5316 opn = "tlbwi"; 5326 opn = "tlbwi";
5317 if (!env->tlb->do_tlbwi) 5327 if (!env->tlb->do_tlbwi)
5318 goto die; 5328 goto die;
5319 - gen_op_tlbwi(); 5329 + tcg_gen_helper_0_0(env->tlb->do_tlbwi);
5320 break; 5330 break;
5321 case OPC_TLBWR: 5331 case OPC_TLBWR:
5322 opn = "tlbwr"; 5332 opn = "tlbwr";
5323 if (!env->tlb->do_tlbwr) 5333 if (!env->tlb->do_tlbwr)
5324 goto die; 5334 goto die;
5325 - gen_op_tlbwr(); 5335 + tcg_gen_helper_0_0(env->tlb->do_tlbwr);
5326 break; 5336 break;
5327 case OPC_TLBP: 5337 case OPC_TLBP:
5328 opn = "tlbp"; 5338 opn = "tlbp";
5329 if (!env->tlb->do_tlbp) 5339 if (!env->tlb->do_tlbp)
5330 goto die; 5340 goto die;
5331 - gen_op_tlbp(); 5341 + tcg_gen_helper_0_0(env->tlb->do_tlbp);
5332 break; 5342 break;
5333 case OPC_TLBR: 5343 case OPC_TLBR:
5334 opn = "tlbr"; 5344 opn = "tlbr";
5335 if (!env->tlb->do_tlbr) 5345 if (!env->tlb->do_tlbr)
5336 goto die; 5346 goto die;
5337 - gen_op_tlbr(); 5347 + tcg_gen_helper_0_0(env->tlb->do_tlbr);
5338 break; 5348 break;
5339 case OPC_ERET: 5349 case OPC_ERET:
5340 opn = "eret"; 5350 opn = "eret";
@@ -5362,7 +5372,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5362,7 +5372,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5362 ctx->pc += 4; 5372 ctx->pc += 4;
5363 save_cpu_state(ctx, 1); 5373 save_cpu_state(ctx, 1);
5364 ctx->pc -= 4; 5374 ctx->pc -= 4;
5365 - gen_op_wait(); 5375 + tcg_gen_helper_0_0(do_wait);
5366 ctx->bstate = BS_EXCP; 5376 ctx->bstate = BS_EXCP;
5367 break; 5377 break;
5368 default: 5378 default:
@@ -6617,7 +6627,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6617,7 +6627,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6617 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond)); 6627 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
6618 tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1); 6628 tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
6619 tcg_temp_free(r_tmp); 6629 tcg_temp_free(r_tmp);
6620 - gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK); 6630 + {
  6631 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
  6632 +
  6633 + tcg_gen_movi_i32(r_tmp2, ctx->hflags & ~MIPS_HFLAG_BMASK);
  6634 + tcg_gen_st_i32(r_tmp2, cpu_env, offsetof(CPUState, hflags));
  6635 + tcg_temp_free(r_tmp2);
  6636 + }
6621 gen_goto_tb(ctx, 1, ctx->pc + 4); 6637 gen_goto_tb(ctx, 1, ctx->pc + 4);
6622 gen_set_label(l1); 6638 gen_set_label(l1);
6623 } 6639 }
@@ -6671,7 +6687,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6671,7 +6687,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6671 MIPS_INVAL("PMON / selsl"); 6687 MIPS_INVAL("PMON / selsl");
6672 generate_exception(ctx, EXCP_RI); 6688 generate_exception(ctx, EXCP_RI);
6673 #else 6689 #else
6674 - gen_op_pmon(sa); 6690 + tcg_gen_helper_0_1i(do_pmon, sa);
6675 #endif 6691 #endif
6676 break; 6692 break;
6677 case OPC_SYSCALL: 6693 case OPC_SYSCALL:
@@ -6827,7 +6843,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6827,7 +6843,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6827 break; 6843 break;
6828 case 29: 6844 case 29:
6829 #if defined (CONFIG_USER_ONLY) 6845 #if defined (CONFIG_USER_ONLY)
6830 - gen_op_tls_value(); 6846 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, tls_value));
6831 break; 6847 break;
6832 #endif 6848 #endif
6833 default: /* Invalid */ 6849 default: /* Invalid */
@@ -7243,7 +7259,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -7243,7 +7259,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7243 if (env->breakpoints[j] == ctx.pc) { 7259 if (env->breakpoints[j] == ctx.pc) {
7244 save_cpu_state(&ctx, 1); 7260 save_cpu_state(&ctx, 1);
7245 ctx.bstate = BS_BRANCH; 7261 ctx.bstate = BS_BRANCH;
7246 - gen_op_debug(); 7262 + tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG);
7247 /* Include the breakpoint location or the tb won't 7263 /* Include the breakpoint location or the tb won't
7248 * be flushed when it must be. */ 7264 * be flushed when it must be. */
7249 ctx.pc += 4; 7265 ctx.pc += 4;
@@ -7285,7 +7301,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -7285,7 +7301,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7285 } 7301 }
7286 if (env->singlestep_enabled) { 7302 if (env->singlestep_enabled) {
7287 save_cpu_state(&ctx, ctx.bstate == BS_NONE); 7303 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
7288 - gen_op_debug(); 7304 + tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG);
7289 } else { 7305 } else {
7290 switch (ctx.bstate) { 7306 switch (ctx.bstate) {
7291 case BS_STOP: 7307 case BS_STOP: