gwj / at91sam9263 · Commits

Commit 089af991182fb44915c30075ea4e202ad268afcb

Authored by bellard
1 parent 3476562d

RTL8029 IDs support (Warner Losh) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1647 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 22 additions and 0 deletions
hw/ne2000.c
  View file @089af99
@@ -47,7 +47,9 @@ @@ -47,7 +47,9 @@
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ 47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ 48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ 49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
  50 +#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
50 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ 51 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
  52 +#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
51 #define EN0_RSR 0x0c /* rx status reg RD */ 53 #define EN0_RSR 0x0c /* rx status reg RD */
52 #define EN0_RXCR 0x0c /* RX configuration reg WR */ 54 #define EN0_RXCR 0x0c /* RX configuration reg WR */
53 #define EN0_TXCR 0x0d /* TX configuration reg WR */ 55 #define EN0_TXCR 0x0d /* TX configuration reg WR */
@@ -64,6 +66,11 @@ @@ -64,6 +66,11 @@
64 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ 66 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
65 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ 67 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
66 68
  69 +#define EN3_CONFIG0 0x33
  70 +#define EN3_CONFIG1 0x34
  71 +#define EN3_CONFIG2 0x35
  72 +#define EN3_CONFIG3 0x36
  73 +
67 /* Register accessed at EN_CMD, the 8390 base addr. */ 74 /* Register accessed at EN_CMD, the 8390 base addr. */
68 #define E8390_STOP 0x01 /* Stop and reset the chip */ 75 #define E8390_STOP 0x01 /* Stop and reset the chip */
69 #define E8390_START 0x02 /* Start the chip, clear reset */ 76 #define E8390_START 0x02 /* Start the chip, clear reset */
@@ -447,6 +454,21 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) @@ -447,6 +454,21 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
447 case EN2_STOPPG: 454 case EN2_STOPPG:
448 ret = s->stop >> 8; 455 ret = s->stop >> 8;
449 break; 456 break;
  457 + case EN0_RTL8029ID0:
  458 + ret = 0x50;
  459 + break;
  460 + case EN0_RTL8029ID1:
  461 + ret = 0x43;
  462 + break;
  463 + case EN3_CONFIG0:
  464 + ret = 0; /* 10baseT media */
  465 + break;
  466 + case EN3_CONFIG2:
  467 + ret = 0x40; /* 10baseT active */
  468 + break;
  469 + case EN3_CONFIG3:
  470 + ret = 0x40; /* Full duplex */
  471 + break;
450 default: 472 default:
451 ret = 0x00; 473 ret = 0x00;
452 break; 474 break;