gwj / at91sam9263 · Commits

Commit 082c6681b6c4af0035d9dad34a4a784be8c21dbe

Authored by j_mayer
1 parent add78955

Remove shared macro used to define PowerPC implementations instructions sets: 

tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 489 additions and 174 deletions
target-ppc/cpu.h
  View file @082c668
@@ -1040,9 +1040,11 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1040,9 +1040,11 @@ static inline int cpu_mmu_index (CPUState *env)
1040 #define SPR_RCPU_MI_RBA2 (0x302) 1040 #define SPR_RCPU_MI_RBA2 (0x302)
1041 #define SPR_MPC_MI_AP (0x302) 1041 #define SPR_MPC_MI_AP (0x302)
1042 #define SPR_PERF3 (0x303) 1042 #define SPR_PERF3 (0x303)
  1043 +#define SPR_620_PMC1R (0x303)
1043 #define SPR_RCPU_MI_RBA3 (0x303) 1044 #define SPR_RCPU_MI_RBA3 (0x303)
1044 #define SPR_MPC_MI_EPN (0x303) 1045 #define SPR_MPC_MI_EPN (0x303)
1045 #define SPR_PERF4 (0x304) 1046 #define SPR_PERF4 (0x304)
  1047 +#define SPR_620_PMC2R (0x304)
1046 #define SPR_PERF5 (0x305) 1048 #define SPR_PERF5 (0x305)
1047 #define SPR_MPC_MI_TWC (0x305) 1049 #define SPR_MPC_MI_TWC (0x305)
1048 #define SPR_PERF6 (0x306) 1050 #define SPR_PERF6 (0x306)
@@ -1058,6 +1060,7 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1058,6 +1060,7 @@ static inline int cpu_mmu_index (CPUState *env)
1058 #define SPR_RCPU_L2U_RBA2 (0x30A) 1060 #define SPR_RCPU_L2U_RBA2 (0x30A)
1059 #define SPR_MPC_MD_AP (0x30A) 1061 #define SPR_MPC_MD_AP (0x30A)
1060 #define SPR_PERFB (0x30B) 1062 #define SPR_PERFB (0x30B)
  1063 +#define SPR_620_MMCR0R (0x30B)
1061 #define SPR_RCPU_L2U_RBA3 (0x30B) 1064 #define SPR_RCPU_L2U_RBA3 (0x30B)
1062 #define SPR_MPC_MD_EPN (0x30B) 1065 #define SPR_MPC_MD_EPN (0x30B)
1063 #define SPR_PERFC (0x30C) 1066 #define SPR_PERFC (0x30C)
@@ -1072,7 +1075,9 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1072,7 +1075,9 @@ static inline int cpu_mmu_index (CPUState *env)
1072 #define SPR_UPERF1 (0x311) 1075 #define SPR_UPERF1 (0x311)
1073 #define SPR_UPERF2 (0x312) 1076 #define SPR_UPERF2 (0x312)
1074 #define SPR_UPERF3 (0x313) 1077 #define SPR_UPERF3 (0x313)
  1078 +#define SPR_620_PMC1W (0x313)
1075 #define SPR_UPERF4 (0x314) 1079 #define SPR_UPERF4 (0x314)
  1080 +#define SPR_620_PMC2W (0x314)
1076 #define SPR_UPERF5 (0x315) 1081 #define SPR_UPERF5 (0x315)
1077 #define SPR_UPERF6 (0x316) 1082 #define SPR_UPERF6 (0x316)
1078 #define SPR_UPERF7 (0x317) 1083 #define SPR_UPERF7 (0x317)
@@ -1080,6 +1085,7 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1080,6 +1085,7 @@ static inline int cpu_mmu_index (CPUState *env)
1080 #define SPR_UPERF9 (0x319) 1085 #define SPR_UPERF9 (0x319)
1081 #define SPR_UPERFA (0x31A) 1086 #define SPR_UPERFA (0x31A)
1082 #define SPR_UPERFB (0x31B) 1087 #define SPR_UPERFB (0x31B)
  1088 +#define SPR_620_MMCR0W (0x31B)
1083 #define SPR_UPERFC (0x31C) 1089 #define SPR_UPERFC (0x31C)
1084 #define SPR_UPERFD (0x31D) 1090 #define SPR_UPERFD (0x31D)
1085 #define SPR_UPERFE (0x31E) 1091 #define SPR_UPERFE (0x31E)
@@ -1245,13 +1251,14 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1245,13 +1251,14 @@ static inline int cpu_mmu_index (CPUState *env)
1245 #define SPR_LDSTCR (0x3F8) 1251 #define SPR_LDSTCR (0x3F8)
1246 #define SPR_L2PMCR (0x3F8) 1252 #define SPR_L2PMCR (0x3F8)
1247 #define SPR_750_HID2 (0x3F8) 1253 #define SPR_750_HID2 (0x3F8)
1248 -#define SPR_620_HID8 (0x3F8) 1254 +#define SPR_620_BUSCSR (0x3F8)
1249 #define SPR_Exxx_L1FINV0 (0x3F8) 1255 #define SPR_Exxx_L1FINV0 (0x3F8)
1250 #define SPR_L2CR (0x3F9) 1256 #define SPR_L2CR (0x3F9)
1251 -#define SPR_620_HID9 (0x3F9) 1257 +#define SPR_620_L2CR (0x3F9)
1252 #define SPR_L3CR (0x3FA) 1258 #define SPR_L3CR (0x3FA)
1253 #define SPR_IABR2 (0x3FA) 1259 #define SPR_IABR2 (0x3FA)
1254 #define SPR_40x_DCCR (0x3FA) 1260 #define SPR_40x_DCCR (0x3FA)
  1261 +#define SPR_620_L2SR (0x3FA)
1255 #define SPR_ICTC (0x3FB) 1262 #define SPR_ICTC (0x3FB)
1256 #define SPR_40x_ICCR (0x3FB) 1263 #define SPR_40x_ICCR (0x3FB)
1257 #define SPR_THRM1 (0x3FC) 1264 #define SPR_THRM1 (0x3FC)
target-ppc/translate_init.c
  View file @082c668
@@ -281,13 +281,11 @@ static void spr_write_sdr1 (void *opaque, int sprn) @@ -281,13 +281,11 @@ static void spr_write_sdr1 (void *opaque, int sprn)
281 /* 64 bits PowerPC specific SPRs */ 281 /* 64 bits PowerPC specific SPRs */
282 /* ASR */ 282 /* ASR */
283 #if defined(TARGET_PPC64) 283 #if defined(TARGET_PPC64)
284 -__attribute__ (( unused ))  
285 static void spr_read_asr (void *opaque, int sprn) 284 static void spr_read_asr (void *opaque, int sprn)
286 { 285 {
287 gen_op_load_asr(); 286 gen_op_load_asr();
288 } 287 }
289 288
290 -__attribute__ (( unused ))  
291 static void spr_write_asr (void *opaque, int sprn) 289 static void spr_write_asr (void *opaque, int sprn)
292 { 290 {
293 gen_op_store_asr(); 291 gen_op_store_asr();
@@ -924,11 +922,6 @@ static void gen_spr_604 (CPUPPCState *env) @@ -924,11 +922,6 @@ static void gen_spr_604 (CPUPPCState *env)
924 &spr_read_generic, &spr_write_generic, 922 &spr_read_generic, &spr_write_generic,
925 0x00000000); 923 0x00000000);
926 /* XXX : not implemented */ 924 /* XXX : not implemented */
927 - spr_register(env, SPR_MMCR1, "MMCR1",  
928 - SPR_NOACCESS, SPR_NOACCESS,  
929 - &spr_read_generic, &spr_write_generic,  
930 - 0x00000000);  
931 - /* XXX : not implemented */  
932 spr_register(env, SPR_PMC1, "PMC1", 925 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS, 926 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic, 927 &spr_read_generic, &spr_write_generic,
@@ -939,16 +932,6 @@ static void gen_spr_604 (CPUPPCState *env) @@ -939,16 +932,6 @@ static void gen_spr_604 (CPUPPCState *env)
939 &spr_read_generic, &spr_write_generic, 932 &spr_read_generic, &spr_write_generic,
940 0x00000000); 933 0x00000000);
941 /* XXX : not implemented */ 934 /* XXX : not implemented */
942 - spr_register(env, SPR_PMC3, "PMC3",  
943 - SPR_NOACCESS, SPR_NOACCESS,  
944 - &spr_read_generic, &spr_write_generic,  
945 - 0x00000000);  
946 - /* XXX : not implemented */  
947 - spr_register(env, SPR_PMC4, "PMC4",  
948 - SPR_NOACCESS, SPR_NOACCESS,  
949 - &spr_read_generic, &spr_write_generic,  
950 - 0x00000000);  
951 - /* XXX : not implemented */  
952 spr_register(env, SPR_SIAR, "SIAR", 935 spr_register(env, SPR_SIAR, "SIAR",
953 SPR_NOACCESS, SPR_NOACCESS, 936 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS, 937 &spr_read_generic, SPR_NOACCESS,
@@ -2008,6 +1991,70 @@ static void gen_spr_compress (CPUPPCState *env) @@ -2008,6 +1991,70 @@ static void gen_spr_compress (CPUPPCState *env)
2008 /* SPR specific to PowerPC 620 */ 1991 /* SPR specific to PowerPC 620 */
2009 static void gen_spr_620 (CPUPPCState *env) 1992 static void gen_spr_620 (CPUPPCState *env)
2010 { 1993 {
  1994 + /* Processor identification */
  1995 + spr_register(env, SPR_PIR, "PIR",
  1996 + SPR_NOACCESS, SPR_NOACCESS,
  1997 + &spr_read_generic, &spr_write_pir,
  1998 + 0x00000000);
  1999 + spr_register(env, SPR_ASR, "ASR",
  2000 + SPR_NOACCESS, SPR_NOACCESS,
  2001 + &spr_read_asr, &spr_write_asr,
  2002 + 0x00000000);
  2003 + /* Breakpoints */
  2004 + /* XXX : not implemented */
  2005 + spr_register(env, SPR_IABR, "IABR",
  2006 + SPR_NOACCESS, SPR_NOACCESS,
  2007 + &spr_read_generic, &spr_write_generic,
  2008 + 0x00000000);
  2009 + /* XXX : not implemented */
  2010 + spr_register(env, SPR_DABR, "DABR",
  2011 + SPR_NOACCESS, SPR_NOACCESS,
  2012 + &spr_read_generic, &spr_write_generic,
  2013 + 0x00000000);
  2014 + /* XXX : not implemented */
  2015 + spr_register(env, SPR_SIAR, "SIAR",
  2016 + SPR_NOACCESS, SPR_NOACCESS,
  2017 + &spr_read_generic, SPR_NOACCESS,
  2018 + 0x00000000);
  2019 + /* XXX : not implemented */
  2020 + spr_register(env, SPR_SDA, "SDA",
  2021 + SPR_NOACCESS, SPR_NOACCESS,
  2022 + &spr_read_generic, SPR_NOACCESS,
  2023 + 0x00000000);
  2024 + /* XXX : not implemented */
  2025 + spr_register(env, SPR_620_PMC1R, "PMC1",
  2026 + SPR_NOACCESS, SPR_NOACCESS,
  2027 + &spr_read_generic, SPR_NOACCESS,
  2028 + 0x00000000);
  2029 + spr_register(env, SPR_620_PMC1W, "PMC1",
  2030 + SPR_NOACCESS, SPR_NOACCESS,
  2031 + SPR_NOACCESS, &spr_write_generic,
  2032 + 0x00000000);
  2033 + /* XXX : not implemented */
  2034 + spr_register(env, SPR_620_PMC2R, "PMC2",
  2035 + SPR_NOACCESS, SPR_NOACCESS,
  2036 + &spr_read_generic, SPR_NOACCESS,
  2037 + 0x00000000);
  2038 + spr_register(env, SPR_620_PMC2W, "PMC2",
  2039 + SPR_NOACCESS, SPR_NOACCESS,
  2040 + SPR_NOACCESS, &spr_write_generic,
  2041 + 0x00000000);
  2042 + /* XXX : not implemented */
  2043 + spr_register(env, SPR_620_MMCR0R, "MMCR0",
  2044 + SPR_NOACCESS, SPR_NOACCESS,
  2045 + &spr_read_generic, SPR_NOACCESS,
  2046 + 0x00000000);
  2047 + spr_register(env, SPR_620_MMCR0W, "MMCR0",
  2048 + SPR_NOACCESS, SPR_NOACCESS,
  2049 + SPR_NOACCESS, &spr_write_generic,
  2050 + 0x00000000);
  2051 + /* External access control */
  2052 + /* XXX : not implemented */
  2053 + spr_register(env, SPR_EAR, "EAR",
  2054 + SPR_NOACCESS, SPR_NOACCESS,
  2055 + &spr_read_generic, &spr_write_generic,
  2056 + 0x00000000);
  2057 +#if 0 // XXX: check this
2011 /* XXX : not implemented */ 2058 /* XXX : not implemented */
2012 spr_register(env, SPR_620_PMR0, "PMR0", 2059 spr_register(env, SPR_620_PMR0, "PMR0",
2013 SPR_NOACCESS, SPR_NOACCESS, 2060 SPR_NOACCESS, SPR_NOACCESS,
@@ -2088,13 +2135,19 @@ static void gen_spr_620 (CPUPPCState *env) @@ -2088,13 +2135,19 @@ static void gen_spr_620 (CPUPPCState *env)
2088 SPR_NOACCESS, SPR_NOACCESS, 2135 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic, 2136 &spr_read_generic, &spr_write_generic,
2090 0x00000000); 2137 0x00000000);
  2138 +#endif
2091 /* XXX : not implemented */ 2139 /* XXX : not implemented */
2092 - spr_register(env, SPR_620_HID8, "HID8", 2140 + spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2093 SPR_NOACCESS, SPR_NOACCESS, 2141 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic, 2142 &spr_read_generic, &spr_write_generic,
2095 0x00000000); 2143 0x00000000);
2096 /* XXX : not implemented */ 2144 /* XXX : not implemented */
2097 - spr_register(env, SPR_620_HID9, "HID9", 2145 + spr_register(env, SPR_620_L2CR, "L2CR",
  2146 + SPR_NOACCESS, SPR_NOACCESS,
  2147 + &spr_read_generic, &spr_write_generic,
  2148 + 0x00000000);
  2149 + /* XXX : not implemented */
  2150 + spr_register(env, SPR_620_L2SR, "L2SR",
2098 SPR_NOACCESS, SPR_NOACCESS, 2151 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic, 2152 &spr_read_generic, &spr_write_generic,
2100 0x00000000); 2153 0x00000000);
@@ -2704,6 +2757,7 @@ static void init_excp_601 (CPUPPCState *env) @@ -2704,6 +2757,7 @@ static void init_excp_601 (CPUPPCState *env)
2704 static void init_excp_602 (CPUPPCState *env) 2757 static void init_excp_602 (CPUPPCState *env)
2705 { 2758 {
2706 #if !defined(CONFIG_USER_ONLY) 2759 #if !defined(CONFIG_USER_ONLY)
  2760 + /* XXX: exception prefix has a special behavior on 602 */
2707 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2761 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2708 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2762 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2709 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2763 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
@@ -2715,7 +2769,6 @@ static void init_excp_602 (CPUPPCState *env) @@ -2715,7 +2769,6 @@ static void init_excp_602 (CPUPPCState *env)
2715 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2769 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2716 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2770 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2717 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2771 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2718 - env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;  
2719 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2772 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2720 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2773 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2721 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2774 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
@@ -2784,9 +2837,7 @@ static void init_excp_620 (CPUPPCState *env) @@ -2784,9 +2837,7 @@ static void init_excp_620 (CPUPPCState *env)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2837 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2838 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2839 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2787 - env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;  
2788 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2840 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2789 - env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;  
2790 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2791 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2792 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
@@ -2794,7 +2845,6 @@ static void init_excp_620 (CPUPPCState *env) @@ -2794,7 +2845,6 @@ static void init_excp_620 (CPUPPCState *env)
2794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2796 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2847 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2797 - env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;  
2798 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2848 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2849 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2850 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
@@ -2987,14 +3037,13 @@ static int check_pow_hid0 (CPUPPCState *env) @@ -2987,14 +3037,13 @@ static int check_pow_hid0 (CPUPPCState *env)
2987 /*****************************************************************************/ 3037 /*****************************************************************************/
2988 /* PowerPC implementations definitions */ 3038 /* PowerPC implementations definitions */
2989 3039
2990 -/* PowerPC 40x instruction set */  
2991 -#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \  
2992 - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)  
2993 -  
2994 /* PowerPC 401 */ 3040 /* PowerPC 401 */
2995 -#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3041 +#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
  3042 + PPC_WRTEE | PPC_DCR | \
  3043 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3044 + PPC_CACHE_DCBZ | \
2996 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3045 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2997 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3046 + PPC_4xx_COMMON | PPC_40x_EXCP)
2998 #define POWERPC_MSRM_401 (0x00000000000FD201ULL) 3047 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2999 #define POWERPC_MMU_401 (POWERPC_MMU_REAL) 3048 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3000 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x) 3049 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
@@ -3017,11 +3066,13 @@ static void init_proc_401 (CPUPPCState *env) @@ -3017,11 +3066,13 @@ static void init_proc_401 (CPUPPCState *env)
3017 } 3066 }
3018 3067
3019 /* PowerPC 401x2 */ 3068 /* PowerPC 401x2 */
3020 -#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3069 +#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  3070 + PPC_DCR | PPC_WRTEE | \
  3071 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3072 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3021 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3073 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3022 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ 3074 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3023 - PPC_CACHE_DCBA | PPC_MFTB | \  
3024 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3075 + PPC_4xx_COMMON | PPC_40x_EXCP)
3025 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) 3076 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3026 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z) 3077 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3027 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x) 3078 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
@@ -3051,11 +3102,13 @@ static void init_proc_401x2 (CPUPPCState *env) @@ -3051,11 +3102,13 @@ static void init_proc_401x2 (CPUPPCState *env)
3051 } 3102 }
3052 3103
3053 /* PowerPC 401x3 */ 3104 /* PowerPC 401x3 */
3054 -#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3105 +#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  3106 + PPC_DCR | PPC_WRTEE | \
  3107 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3108 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3055 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3109 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3056 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ 3110 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3057 - PPC_CACHE_DCBA | PPC_MFTB | \  
3058 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3111 + PPC_4xx_COMMON | PPC_40x_EXCP)
3059 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) 3112 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3060 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z) 3113 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3061 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x) 3114 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
@@ -3081,11 +3134,13 @@ static void init_proc_401x3 (CPUPPCState *env) @@ -3081,11 +3134,13 @@ static void init_proc_401x3 (CPUPPCState *env)
3081 } 3134 }
3082 3135
3083 /* IOP480 */ 3136 /* IOP480 */
3084 -#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3137 +#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
  3138 + PPC_DCR | PPC_WRTEE | \
  3139 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3140 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3085 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3141 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3086 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ 3142 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3087 - PPC_CACHE_DCBA | \  
3088 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3143 + PPC_4xx_COMMON | PPC_40x_EXCP)
3089 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) 3144 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3090 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z) 3145 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3091 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x) 3146 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
@@ -3115,9 +3170,12 @@ static void init_proc_IOP480 (CPUPPCState *env) @@ -3115,9 +3170,12 @@ static void init_proc_IOP480 (CPUPPCState *env)
3115 } 3170 }
3116 3171
3117 /* PowerPC 403 */ 3172 /* PowerPC 403 */
3118 -#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3173 +#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
  3174 + PPC_DCR | PPC_WRTEE | \
  3175 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3176 + PPC_CACHE_DCBZ | \
3119 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3177 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3120 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3178 + PPC_4xx_COMMON | PPC_40x_EXCP)
3121 #define POWERPC_MSRM_403 (0x000000000007D00DULL) 3179 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3122 #define POWERPC_MMU_403 (POWERPC_MMU_REAL) 3180 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3123 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x) 3181 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
@@ -3145,10 +3203,13 @@ static void init_proc_403 (CPUPPCState *env) @@ -3145,10 +3203,13 @@ static void init_proc_403 (CPUPPCState *env)
3145 } 3203 }
3146 3204
3147 /* PowerPC 403 GCX */ 3205 /* PowerPC 403 GCX */
3148 -#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ 3206 +#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
  3207 + PPC_DCR | PPC_WRTEE | \
  3208 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3209 + PPC_CACHE_DCBZ | \
3149 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 3210 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3150 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ 3211 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3151 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) 3212 + PPC_4xx_COMMON | PPC_40x_EXCP)
3152 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL) 3213 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3153 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z) 3214 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3154 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x) 3215 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
@@ -3190,12 +3251,13 @@ static void init_proc_403GCX (CPUPPCState *env) @@ -3190,12 +3251,13 @@ static void init_proc_403GCX (CPUPPCState *env)
3190 } 3251 }
3191 3252
3192 /* PowerPC 405 */ 3253 /* PowerPC 405 */
3193 -#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \  
3194 - PPC_MFTB | \  
3195 - PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \ 3254 +#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  3255 + PPC_DCR | PPC_WRTEE | \
  3256 + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
  3257 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3258 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3196 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ 3259 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3197 - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \  
3198 - PPC_405_MAC) 3260 + PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3199 #define POWERPC_MSRM_405 (0x000000000006E630ULL) 3261 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3200 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx) 3262 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3201 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x) 3263 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
@@ -3236,10 +3298,13 @@ static void init_proc_405 (CPUPPCState *env) @@ -3236,10 +3298,13 @@ static void init_proc_405 (CPUPPCState *env)
3236 } 3298 }
3237 3299
3238 /* PowerPC 440 EP */ 3300 /* PowerPC 440 EP */
3239 -#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \  
3240 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ 3301 +#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
  3302 + PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
  3303 + PPC_CACHE | PPC_CACHE_ICBI | \
  3304 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3305 + PPC_MEM_TLBSYNC | \
3241 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ 3306 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3242 - PPC_440_SPEC | PPC_RFMCI) 3307 + PPC_440_SPEC)
3243 #define POWERPC_MSRM_440EP (0x000000000006D630ULL) 3308 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3244 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE) 3309 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3245 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE) 3310 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
@@ -3313,11 +3378,13 @@ static void init_proc_440EP (CPUPPCState *env) @@ -3313,11 +3378,13 @@ static void init_proc_440EP (CPUPPCState *env)
3313 } 3378 }
3314 3379
3315 /* PowerPC 440 GP */ 3380 /* PowerPC 440 GP */
3316 -#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \  
3317 - PPC_DCR | PPC_DCRX | \  
3318 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \  
3319 - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \  
3320 - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) 3381 +#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
  3382 + PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
  3383 + PPC_CACHE | PPC_CACHE_ICBI | \
  3384 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3385 + PPC_MEM_TLBSYNC | PPC_TLBIVA | \
  3386 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3387 + PPC_440_SPEC)
3321 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL) 3388 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3322 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE) 3389 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3323 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE) 3390 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
@@ -3373,8 +3440,11 @@ static void init_proc_440GP (CPUPPCState *env) @@ -3373,8 +3440,11 @@ static void init_proc_440GP (CPUPPCState *env)
3373 } 3440 }
3374 3441
3375 /* PowerPC 440x4 */ 3442 /* PowerPC 440x4 */
3376 -#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \  
3377 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ 3443 +#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
  3444 + PPC_DCR | PPC_WRTEE | \
  3445 + PPC_CACHE | PPC_CACHE_ICBI | \
  3446 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3447 + PPC_MEM_TLBSYNC | \
3378 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ 3448 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3379 PPC_440_SPEC) 3449 PPC_440_SPEC)
3380 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL) 3450 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
@@ -3432,10 +3502,13 @@ static void init_proc_440x4 (CPUPPCState *env) @@ -3432,10 +3502,13 @@ static void init_proc_440x4 (CPUPPCState *env)
3432 } 3502 }
3433 3503
3434 /* PowerPC 440x5 */ 3504 /* PowerPC 440x5 */
3435 -#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \  
3436 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ 3505 +#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
  3506 + PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
  3507 + PPC_CACHE | PPC_CACHE_ICBI | \
  3508 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3509 + PPC_MEM_TLBSYNC | \
3437 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ 3510 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3438 - PPC_440_SPEC | PPC_RFMCI) 3511 + PPC_440_SPEC)
3439 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL) 3512 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3440 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE) 3513 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3441 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE) 3514 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
@@ -3509,11 +3582,14 @@ static void init_proc_440x5 (CPUPPCState *env) @@ -3509,11 +3582,14 @@ static void init_proc_440x5 (CPUPPCState *env)
3509 } 3582 }
3510 3583
3511 /* PowerPC 460 (guessed) */ 3584 /* PowerPC 460 (guessed) */
3512 -#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \ 3585 +#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3513 PPC_DCR | PPC_DCRX | PPC_DCRUX | \ 3586 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3514 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \  
3515 - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \  
3516 - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) 3587 + PPC_WRTEE | PPC_MFAPIDI | \
  3588 + PPC_CACHE | PPC_CACHE_ICBI | \
  3589 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3590 + PPC_MEM_TLBSYNC | PPC_TLBIVA | \
  3591 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3592 + PPC_440_SPEC)
3517 #define POWERPC_MSRM_460 (0x000000000006FF30ULL) 3593 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3518 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE) 3594 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3519 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE) 3595 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
@@ -3592,14 +3668,17 @@ static void init_proc_460 (CPUPPCState *env) @@ -3592,14 +3668,17 @@ static void init_proc_460 (CPUPPCState *env)
3592 } 3668 }
3593 3669
3594 /* PowerPC 460F (guessed) */ 3670 /* PowerPC 460F (guessed) */
3595 -#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \  
3596 - PPC_DCR | PPC_DCRX | PPC_DCRUX | \  
3597 - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \  
3598 - PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \  
3599 - PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ 3671 +#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
  3672 + PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
  3673 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3600 PPC_FLOAT_STFIWX | \ 3674 PPC_FLOAT_STFIWX | \
3601 - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \  
3602 - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) 3675 + PPC_DCR | PPC_DCRX | PPC_DCRUX | \
  3676 + PPC_WRTEE | PPC_MFAPIDI | \
  3677 + PPC_CACHE | PPC_CACHE_ICBI | \
  3678 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
  3679 + PPC_MEM_TLBSYNC | PPC_TLBIVA | \
  3680 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3681 + PPC_440_SPEC)
3603 #define POWERPC_MSRM_460 (0x000000000006FF30ULL) 3682 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3604 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE) 3683 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3605 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE) 3684 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
@@ -3732,7 +3811,13 @@ static void init_proc_MPC8xx (CPUPPCState *env) @@ -3732,7 +3811,13 @@ static void init_proc_MPC8xx (CPUPPCState *env)
3732 3811
3733 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3812 /* Freescale 82xx cores (aka PowerQUICC-II) */
3734 /* PowerPC G2 */ 3813 /* PowerPC G2 */
3735 -#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) 3814 +#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  3815 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  3816 + PPC_FLOAT_STFIWX | \
  3817 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  3818 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3819 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  3820 + PPC_SEGMENT | PPC_EXTERN)
3736 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL) 3821 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3737 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx) 3822 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3738 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2) 3823 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
@@ -3777,7 +3862,13 @@ static void init_proc_G2 (CPUPPCState *env) @@ -3777,7 +3862,13 @@ static void init_proc_G2 (CPUPPCState *env)
3777 } 3862 }
3778 3863
3779 /* PowerPC G2LE */ 3864 /* PowerPC G2LE */
3780 -#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) 3865 +#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  3866 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  3867 + PPC_FLOAT_STFIWX | \
  3868 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  3869 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3870 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  3871 + PPC_SEGMENT | PPC_EXTERN)
3781 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL) 3872 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3782 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx) 3873 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3783 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2) 3874 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
@@ -3831,11 +3922,13 @@ static void init_proc_G2LE (CPUPPCState *env) @@ -3831,11 +3922,13 @@ static void init_proc_G2LE (CPUPPCState *env)
3831 * tlbivax 3922 * tlbivax
3832 * all SPE multiply-accumulate instructions 3923 * all SPE multiply-accumulate instructions
3833 */ 3924 */
3834 -#define POWERPC_INSNS_e200 (POWERPC_INSNS_EMB | PPC_ISEL | \ 3925 +#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
3835 PPC_SPE | PPC_SPEFPU | \ 3926 PPC_SPE | PPC_SPEFPU | \
  3927 + PPC_WRTEE | PPC_RFDI | \
  3928 + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
  3929 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3836 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ 3930 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3837 - PPC_CACHE_DCBA | PPC_CACHE_LOCK | \  
3838 - PPC_BOOKE | PPC_RFDI) 3931 + PPC_BOOKE)
3839 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL) 3932 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3840 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL) 3933 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3841 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE) 3934 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
@@ -3949,7 +4042,13 @@ static void init_proc_e200 (CPUPPCState *env) @@ -3949,7 +4042,13 @@ static void init_proc_e200 (CPUPPCState *env)
3949 } 4042 }
3950 4043
3951 /* e300 core */ 4044 /* e300 core */
3952 -#define POWERPC_INSNS_e300 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) 4045 +#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4046 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4047 + PPC_FLOAT_STFIWX | \
  4048 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4049 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4050 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  4051 + PPC_SEGMENT | PPC_EXTERN)
3953 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL) 4052 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
3954 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx) 4053 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
3955 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603) 4054 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
@@ -3988,11 +4087,13 @@ static void init_proc_e300 (CPUPPCState *env) @@ -3988,11 +4087,13 @@ static void init_proc_e300 (CPUPPCState *env)
3988 } 4087 }
3989 4088
3990 /* e500 core */ 4089 /* e500 core */
3991 -#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | PPC_ISEL | \ 4090 +#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
3992 PPC_SPE | PPC_SPEFPU | \ 4091 PPC_SPE | PPC_SPEFPU | \
  4092 + PPC_WRTEE | PPC_RFDI | \
  4093 + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
  4094 + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3993 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ 4095 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3994 - PPC_CACHE_DCBA | PPC_CACHE_LOCK | \  
3995 - PPC_BOOKE | PPC_RFDI) 4096 + PPC_BOOKE)
3996 #define POWERPC_MSRM_e500 (0x000000000606FF30ULL) 4097 #define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
3997 #define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL) 4098 #define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
3998 #define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE) 4099 #define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
@@ -4109,16 +4210,6 @@ static void init_proc_e500 (CPUPPCState *env) @@ -4109,16 +4210,6 @@ static void init_proc_e500 (CPUPPCState *env)
4109 } 4210 }
4110 4211
4111 /* Non-embedded PowerPC */ 4212 /* Non-embedded PowerPC */
4112 -/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */  
4113 -#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \  
4114 - PPC_CACHE | PPC_CACHE_ICBI | \  
4115 - PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)  
4116 -/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */  
4117 -#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \  
4118 - PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \  
4119 - PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \  
4120 - PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \  
4121 - PPC_SEGMENT)  
4122 4213
4123 /* POWER : same as 601, without mfmsr, mfsr */ 4214 /* POWER : same as 601, without mfmsr, mfsr */
4124 #if defined(TODO) 4215 #if defined(TODO)
@@ -4128,9 +4219,13 @@ static void init_proc_e500 (CPUPPCState *env) @@ -4128,9 +4219,13 @@ static void init_proc_e500 (CPUPPCState *env)
4128 #endif /* TODO */ 4219 #endif /* TODO */
4129 4220
4130 /* PowerPC 601 */ 4221 /* PowerPC 601 */
4131 -#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \  
4132 - PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR) 4222 +#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
  4223 + PPC_FLOAT | \
  4224 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4225 + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
  4226 + PPC_SEGMENT | PPC_EXTERN)
4133 #define POWERPC_MSRM_601 (0x000000000000FD70ULL) 4227 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
  4228 +#define POWERPC_MSRR_601 (0x0000000000001040ULL)
4134 //#define POWERPC_MMU_601 (POWERPC_MMU_601) 4229 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4135 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601) 4230 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4136 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx) 4231 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
@@ -4163,31 +4258,53 @@ static void init_proc_601 (CPUPPCState *env) @@ -4163,31 +4258,53 @@ static void init_proc_601 (CPUPPCState *env)
4163 SPR_NOACCESS, SPR_NOACCESS, 4258 SPR_NOACCESS, SPR_NOACCESS,
4164 &spr_read_generic, &spr_write_generic, 4259 &spr_read_generic, &spr_write_generic,
4165 0x00000000); 4260 0x00000000);
4166 - /* XXX : not implemented */  
4167 - spr_register(env, SPR_601_HID15, "HID15",  
4168 - SPR_NOACCESS, SPR_NOACCESS,  
4169 - &spr_read_generic, &spr_write_generic,  
4170 - 0x00000000);  
4171 /* Memory management */ 4261 /* Memory management */
4172 -#if !defined(CONFIG_USER_ONLY)  
4173 - env->nb_tlb = 64;  
4174 - env->nb_ways = 2;  
4175 - env->id_tlbs = 0;  
4176 -#endif  
4177 init_excp_601(env); 4262 init_excp_601(env);
4178 - env->dcache_line_size = 64; 4263 + /* XXX: beware that dcache line size is 64
  4264 + * but dcbz uses 32 bytes "sectors"
  4265 + * XXX: this breaks clcs instruction !
  4266 + */
  4267 + env->dcache_line_size = 32;
4179 env->icache_line_size = 64; 4268 env->icache_line_size = 64;
4180 /* Allocate hardware IRQ controller */ 4269 /* Allocate hardware IRQ controller */
4181 ppc6xx_irq_init(env); 4270 ppc6xx_irq_init(env);
4182 } 4271 }
4183 4272
  4273 +/* PowerPC 601v */
  4274 +#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
  4275 + PPC_FLOAT | \
  4276 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4277 + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
  4278 + PPC_SEGMENT | PPC_EXTERN)
  4279 +#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
  4280 +#define POWERPC_MSRR_601v (0x0000000000001040ULL)
  4281 +#define POWERPC_MMU_601v (POWERPC_MMU_601)
  4282 +#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
  4283 +#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
  4284 +#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
  4285 +#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
  4286 +#define check_pow_601v check_pow_none
  4287 +
  4288 +static void init_proc_601v (CPUPPCState *env)
  4289 +{
  4290 + init_proc_601(env);
  4291 + /* XXX : not implemented */
  4292 + spr_register(env, SPR_601_HID15, "HID15",
  4293 + SPR_NOACCESS, SPR_NOACCESS,
  4294 + &spr_read_generic, &spr_write_generic,
  4295 + 0x00000000);
  4296 +}
  4297 +
4184 /* PowerPC 602 */ 4298 /* PowerPC 602 */
4185 -#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \  
4186 - PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \  
4187 - PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \  
4188 - PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\ 4299 +#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4300 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4301 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4302 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4303 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4304 + PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4189 PPC_SEGMENT | PPC_602_SPEC) 4305 PPC_SEGMENT | PPC_602_SPEC)
4190 -#define POWERPC_MSRM_602 (0x000000000033FF73ULL) 4306 +#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
  4307 +/* XXX: 602 MMU is quite specific. Should add a special case */
4191 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx) 4308 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4192 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602) 4309 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4193 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx) 4310 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
@@ -4224,7 +4341,13 @@ static void init_proc_602 (CPUPPCState *env) @@ -4224,7 +4341,13 @@ static void init_proc_602 (CPUPPCState *env)
4224 } 4341 }
4225 4342
4226 /* PowerPC 603 */ 4343 /* PowerPC 603 */
4227 -#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) 4344 +#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4345 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4346 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4347 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4348 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4349 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  4350 + PPC_SEGMENT | PPC_EXTERN)
4228 #define POWERPC_MSRM_603 (0x000000000007FF73ULL) 4351 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4229 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx) 4352 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4230 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603) 4353 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
@@ -4262,7 +4385,13 @@ static void init_proc_603 (CPUPPCState *env) @@ -4262,7 +4385,13 @@ static void init_proc_603 (CPUPPCState *env)
4262 } 4385 }
4263 4386
4264 /* PowerPC 603e */ 4387 /* PowerPC 603e */
4265 -#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN) 4388 +#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4389 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4390 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4391 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4392 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4393 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  4394 + PPC_SEGMENT | PPC_EXTERN)
4266 #define POWERPC_MSRM_603E (0x000000000007FF73ULL) 4395 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4267 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx) 4396 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4268 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E) 4397 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
@@ -4305,7 +4434,13 @@ static void init_proc_603E (CPUPPCState *env) @@ -4305,7 +4434,13 @@ static void init_proc_603E (CPUPPCState *env)
4305 } 4434 }
4306 4435
4307 /* PowerPC 604 */ 4436 /* PowerPC 604 */
4308 -#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN) 4437 +#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4438 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4439 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4440 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4441 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4442 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4443 + PPC_SEGMENT | PPC_EXTERN)
4309 #define POWERPC_MSRM_604 (0x000000000005FF77ULL) 4444 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4310 #define POWERPC_MMU_604 (POWERPC_MMU_32B) 4445 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4311 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604) 4446 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
@@ -4327,6 +4462,59 @@ static void init_proc_604 (CPUPPCState *env) @@ -4327,6 +4462,59 @@ static void init_proc_604 (CPUPPCState *env)
4327 SPR_NOACCESS, SPR_NOACCESS, 4462 SPR_NOACCESS, SPR_NOACCESS,
4328 &spr_read_generic, &spr_write_generic, 4463 &spr_read_generic, &spr_write_generic,
4329 0x00000000); 4464 0x00000000);
  4465 + /* Memory management */
  4466 + gen_low_BATs(env);
  4467 + init_excp_604(env);
  4468 + env->dcache_line_size = 32;
  4469 + env->icache_line_size = 32;
  4470 + /* Allocate hardware IRQ controller */
  4471 + ppc6xx_irq_init(env);
  4472 +}
  4473 +
  4474 +/* PowerPC 604E */
  4475 +#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4476 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4477 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4478 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4479 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4480 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4481 + PPC_SEGMENT | PPC_EXTERN)
  4482 +#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
  4483 +#define POWERPC_MMU_604E (POWERPC_MMU_32B)
  4484 +#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
  4485 +#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
  4486 +#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
  4487 +#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  4488 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  4489 +#define check_pow_604E check_pow_nocheck
  4490 +
  4491 +static void init_proc_604E (CPUPPCState *env)
  4492 +{
  4493 + gen_spr_ne_601(env);
  4494 + gen_spr_604(env);
  4495 + /* XXX : not implemented */
  4496 + spr_register(env, SPR_MMCR1, "MMCR1",
  4497 + SPR_NOACCESS, SPR_NOACCESS,
  4498 + &spr_read_generic, &spr_write_generic,
  4499 + 0x00000000);
  4500 + /* XXX : not implemented */
  4501 + spr_register(env, SPR_PMC3, "PMC3",
  4502 + SPR_NOACCESS, SPR_NOACCESS,
  4503 + &spr_read_generic, &spr_write_generic,
  4504 + 0x00000000);
  4505 + /* XXX : not implemented */
  4506 + spr_register(env, SPR_PMC4, "PMC4",
  4507 + SPR_NOACCESS, SPR_NOACCESS,
  4508 + &spr_read_generic, &spr_write_generic,
  4509 + 0x00000000);
  4510 + /* Time base */
  4511 + gen_tbl(env);
  4512 + /* Hardware implementation registers */
  4513 + /* XXX : not implemented */
  4514 + spr_register(env, SPR_HID0, "HID0",
  4515 + SPR_NOACCESS, SPR_NOACCESS,
  4516 + &spr_read_generic, &spr_write_generic,
  4517 + 0x00000000);
4330 /* XXX : not implemented */ 4518 /* XXX : not implemented */
4331 spr_register(env, SPR_HID1, "HID1", 4519 spr_register(env, SPR_HID1, "HID1",
4332 SPR_NOACCESS, SPR_NOACCESS, 4520 SPR_NOACCESS, SPR_NOACCESS,
@@ -4342,7 +4530,14 @@ static void init_proc_604 (CPUPPCState *env) @@ -4342,7 +4530,14 @@ static void init_proc_604 (CPUPPCState *env)
4342 } 4530 }
4343 4531
4344 /* PowerPC 740/750 (aka G3) */ 4532 /* PowerPC 740/750 (aka G3) */
4345 -#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN) 4533 +#define POWERPC_INSNS_7x0 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4534 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4535 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4536 + PPC_FLOAT_STFIWX | \
  4537 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4538 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4539 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4540 + PPC_SEGMENT | PPC_EXTERN)
4346 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL) 4541 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
4347 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B) 4542 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
4348 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0) 4543 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
@@ -4381,7 +4576,14 @@ static void init_proc_7x0 (CPUPPCState *env) @@ -4381,7 +4576,14 @@ static void init_proc_7x0 (CPUPPCState *env)
4381 } 4576 }
4382 4577
4383 /* PowerPC 750FX/GX */ 4578 /* PowerPC 750FX/GX */
4384 -#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN) 4579 +#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4580 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4581 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4582 + PPC_FLOAT_STFIWX | \
  4583 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4584 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4585 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4586 + PPC_SEGMENT | PPC_EXTERN)
4385 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL) 4587 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
4386 #define POWERPC_MMU_750fx (POWERPC_MMU_32B) 4588 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4387 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0) 4589 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
@@ -4427,7 +4629,14 @@ static void init_proc_750fx (CPUPPCState *env) @@ -4427,7 +4629,14 @@ static void init_proc_750fx (CPUPPCState *env)
4427 } 4629 }
4428 4630
4429 /* PowerPC 745/755 */ 4631 /* PowerPC 745/755 */
4430 -#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB) 4632 +#define POWERPC_INSNS_7x5 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4633 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4634 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4635 + PPC_FLOAT_STFIWX | \
  4636 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4637 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4638 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  4639 + PPC_SEGMENT | PPC_EXTERN)
4431 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL) 4640 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
4432 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx) 4641 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
4433 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5) 4642 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
@@ -4486,8 +4695,16 @@ static void init_proc_7x5 (CPUPPCState *env) @@ -4486,8 +4695,16 @@ static void init_proc_7x5 (CPUPPCState *env)
4486 } 4695 }
4487 4696
4488 /* PowerPC 7400 (aka G4) */ 4697 /* PowerPC 7400 (aka G4) */
4489 -#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4490 - PPC_EXTERN | PPC_MEM_TLBIA | \ 4698 +#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4699 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4700 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4701 + PPC_FLOAT_STFIWX | \
  4702 + PPC_CACHE | PPC_CACHE_ICBI | \
  4703 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  4704 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4705 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4706 + PPC_MEM_TLBIA | \
  4707 + PPC_SEGMENT | PPC_EXTERN | \
4491 PPC_ALTIVEC) 4708 PPC_ALTIVEC)
4492 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL) 4709 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
4493 #define POWERPC_MMU_7400 (POWERPC_MMU_32B) 4710 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
@@ -4519,8 +4736,16 @@ static void init_proc_7400 (CPUPPCState *env) @@ -4519,8 +4736,16 @@ static void init_proc_7400 (CPUPPCState *env)
4519 } 4736 }
4520 4737
4521 /* PowerPC 7410 (aka G4) */ 4738 /* PowerPC 7410 (aka G4) */
4522 -#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4523 - PPC_EXTERN | PPC_MEM_TLBIA | \ 4739 +#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4740 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4741 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4742 + PPC_FLOAT_STFIWX | \
  4743 + PPC_CACHE | PPC_CACHE_ICBI | \
  4744 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  4745 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4746 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4747 + PPC_MEM_TLBIA | \
  4748 + PPC_SEGMENT | PPC_EXTERN | \
4524 PPC_ALTIVEC) 4749 PPC_ALTIVEC)
4525 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL) 4750 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
4526 #define POWERPC_MMU_7410 (POWERPC_MMU_32B) 4751 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
@@ -4564,8 +4789,16 @@ static void init_proc_7410 (CPUPPCState *env) @@ -4564,8 +4789,16 @@ static void init_proc_7410 (CPUPPCState *env)
4564 } 4789 }
4565 4790
4566 /* PowerPC 7440 (aka G4) */ 4791 /* PowerPC 7440 (aka G4) */
4567 -#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4568 - PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ 4792 +#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4793 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4794 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4795 + PPC_FLOAT_STFIWX | \
  4796 + PPC_CACHE | PPC_CACHE_ICBI | \
  4797 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  4798 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4799 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4800 + PPC_MEM_TLBIA | PPC_74xx_TLB | \
  4801 + PPC_SEGMENT | PPC_EXTERN | \
4569 PPC_ALTIVEC) 4802 PPC_ALTIVEC)
4570 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL) 4803 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
4571 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx) 4804 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
@@ -4636,8 +4869,16 @@ static void init_proc_7440 (CPUPPCState *env) @@ -4636,8 +4869,16 @@ static void init_proc_7440 (CPUPPCState *env)
4636 } 4869 }
4637 4870
4638 /* PowerPC 7450 (aka G4) */ 4871 /* PowerPC 7450 (aka G4) */
4639 -#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4640 - PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ 4872 +#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4873 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4874 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4875 + PPC_FLOAT_STFIWX | \
  4876 + PPC_CACHE | PPC_CACHE_ICBI | \
  4877 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  4878 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4879 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4880 + PPC_MEM_TLBIA | PPC_74xx_TLB | \
  4881 + PPC_SEGMENT | PPC_EXTERN | \
4641 PPC_ALTIVEC) 4882 PPC_ALTIVEC)
4642 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL) 4883 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
4643 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx) 4884 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
@@ -4710,8 +4951,16 @@ static void init_proc_7450 (CPUPPCState *env) @@ -4710,8 +4951,16 @@ static void init_proc_7450 (CPUPPCState *env)
4710 } 4951 }
4711 4952
4712 /* PowerPC 7445 (aka G4) */ 4953 /* PowerPC 7445 (aka G4) */
4713 -#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4714 - PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ 4954 +#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4955 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4956 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  4957 + PPC_FLOAT_STFIWX | \
  4958 + PPC_CACHE | PPC_CACHE_ICBI | \
  4959 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  4960 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4961 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4962 + PPC_MEM_TLBIA | PPC_74xx_TLB | \
  4963 + PPC_SEGMENT | PPC_EXTERN | \
4715 PPC_ALTIVEC) 4964 PPC_ALTIVEC)
4716 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL) 4965 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
4717 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx) 4966 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
@@ -4816,8 +5065,16 @@ static void init_proc_7445 (CPUPPCState *env) @@ -4816,8 +5065,16 @@ static void init_proc_7445 (CPUPPCState *env)
4816 } 5065 }
4817 5066
4818 /* PowerPC 7455 (aka G4) */ 5067 /* PowerPC 7455 (aka G4) */
4819 -#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \  
4820 - PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \ 5068 +#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5069 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5070 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5071 + PPC_FLOAT_STFIWX | \
  5072 + PPC_CACHE | PPC_CACHE_ICBI | \
  5073 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  5074 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5075 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  5076 + PPC_MEM_TLBIA | PPC_74xx_TLB | \
  5077 + PPC_SEGMENT | PPC_EXTERN | \
4821 PPC_ALTIVEC) 5078 PPC_ALTIVEC)
4822 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL) 5079 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4823 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx) 5080 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
@@ -4924,12 +5181,14 @@ static void init_proc_7455 (CPUPPCState *env) @@ -4924,12 +5181,14 @@ static void init_proc_7455 (CPUPPCState *env)
4924 } 5181 }
4925 5182
4926 #if defined (TARGET_PPC64) 5183 #if defined (TARGET_PPC64)
4927 -#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \  
4928 - PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \  
4929 - PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \  
4930 - PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)  
4931 /* PowerPC 970 */ 5184 /* PowerPC 970 */
4932 -#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ 5185 +#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5186 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5187 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5188 + PPC_FLOAT_STFIWX | \
  5189 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
  5190 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5191 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4933 PPC_64B | PPC_ALTIVEC | \ 5192 PPC_64B | PPC_ALTIVEC | \
4934 PPC_SEGMENT_64B | PPC_SLBI) 5193 PPC_SEGMENT_64B | PPC_SLBI)
4935 #define POWERPC_MSRM_970 (0x900000000204FF36ULL) 5194 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
@@ -5010,7 +5269,13 @@ static void init_proc_970 (CPUPPCState *env) @@ -5010,7 +5269,13 @@ static void init_proc_970 (CPUPPCState *env)
5010 } 5269 }
5011 5270
5012 /* PowerPC 970FX (aka G5) */ 5271 /* PowerPC 970FX (aka G5) */
5013 -#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ 5272 +#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5273 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5274 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5275 + PPC_FLOAT_STFIWX | \
  5276 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
  5277 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5278 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5014 PPC_64B | PPC_ALTIVEC | \ 5279 PPC_64B | PPC_ALTIVEC | \
5015 PPC_SEGMENT_64B | PPC_SLBI) 5280 PPC_SEGMENT_64B | PPC_SLBI)
5016 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL) 5281 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
@@ -5085,7 +5350,13 @@ static void init_proc_970FX (CPUPPCState *env) @@ -5085,7 +5350,13 @@ static void init_proc_970FX (CPUPPCState *env)
5085 } 5350 }
5086 5351
5087 /* PowerPC 970 GX */ 5352 /* PowerPC 970 GX */
5088 -#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ 5353 +#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5354 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5355 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5356 + PPC_FLOAT_STFIWX | \
  5357 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
  5358 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5359 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5089 PPC_64B | PPC_ALTIVEC | \ 5360 PPC_64B | PPC_ALTIVEC | \
5090 PPC_SEGMENT_64B | PPC_SLBI) 5361 PPC_SEGMENT_64B | PPC_SLBI)
5091 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL) 5362 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
@@ -5160,7 +5431,13 @@ static void init_proc_970GX (CPUPPCState *env) @@ -5160,7 +5431,13 @@ static void init_proc_970GX (CPUPPCState *env)
5160 } 5431 }
5161 5432
5162 /* PowerPC 970 MP */ 5433 /* PowerPC 970 MP */
5163 -#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ 5434 +#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5435 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5436 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5437 + PPC_FLOAT_STFIWX | \
  5438 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
  5439 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5440 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5164 PPC_64B | PPC_ALTIVEC | \ 5441 PPC_64B | PPC_ALTIVEC | \
5165 PPC_SEGMENT_64B | PPC_SLBI) 5442 PPC_SEGMENT_64B | PPC_SLBI)
5166 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL) 5443 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
@@ -5235,7 +5512,14 @@ static void init_proc_970MP (CPUPPCState *env) @@ -5235,7 +5512,14 @@ static void init_proc_970MP (CPUPPCState *env)
5235 } 5512 }
5236 5513
5237 /* PowerPC 620 */ 5514 /* PowerPC 620 */
5238 -#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \ 5515 +#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5516 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5517 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5518 + PPC_FLOAT_STFIWX | \
  5519 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  5520 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5521 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  5522 + PPC_SEGMENT | PPC_EXTERN | \
5239 PPC_64B | PPC_SLBI) 5523 PPC_64B | PPC_SLBI)
5240 #define POWERPC_MSRM_620 (0x800000000005FF77ULL) 5524 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
5241 //#define POWERPC_MMU_620 (POWERPC_MMU_620) 5525 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
@@ -5261,7 +5545,6 @@ static void init_proc_620 (CPUPPCState *env) @@ -5261,7 +5545,6 @@ static void init_proc_620 (CPUPPCState *env)
5261 0x00000000); 5545 0x00000000);
5262 /* Memory management */ 5546 /* Memory management */
5263 gen_low_BATs(env); 5547 gen_low_BATs(env);
5264 - gen_high_BATs(env);  
5265 init_excp_620(env); 5548 init_excp_620(env);
5266 env->dcache_line_size = 64; 5549 env->dcache_line_size = 64;
5267 env->icache_line_size = 64; 5550 env->icache_line_size = 64;
@@ -5938,12 +6221,13 @@ enum { @@ -5938,12 +6221,13 @@ enum {
5938 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */ 6221 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5939 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */ 6222 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5940 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12 6223 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
5941 - /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */  
5942 - /* XXX: missing 0x80030102 */  
5943 - /* XXX: missing 0x80020101 */  
5944 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */ 6224 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5945 - CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */ 6225 + CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
5946 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */ 6226 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
  6227 +#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
  6228 + CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
  6229 + CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
  6230 + CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
5947 /* 64 bits PowerPC */ 6231 /* 64 bits PowerPC */
5948 #if defined(TARGET_PPC64) 6232 #if defined(TARGET_PPC64)
5949 CPU_POWERPC_620 = 0x00140000, 6233 CPU_POWERPC_620 = 0x00140000,
@@ -6714,7 +6998,7 @@ static const ppc_def_t ppc_defs[] = { @@ -6714,7 +6998,7 @@ static const ppc_def_t ppc_defs[] = {
6714 /* MPC8240 */ 6998 /* MPC8240 */
6715 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E), 6999 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
6716 /* PowerPC G2 microcontrollers */ 7000 /* PowerPC G2 microcontrollers */
6717 -#if 0 7001 +#if defined(TODO)
6718 /* MPC5121 */ 7002 /* MPC5121 */
6719 POWERPC_DEF_SVR("MPC5121", 7003 POWERPC_DEF_SVR("MPC5121",
6720 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE), 7004 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
@@ -7295,18 +7579,20 @@ static const ppc_def_t ppc_defs[] = { @@ -7295,18 +7579,20 @@ static const ppc_def_t ppc_defs[] = {
7295 /* PowerPC 601 */ 7579 /* PowerPC 601 */
7296 POWERPC_DEF("601", CPU_POWERPC_601, 601), 7580 POWERPC_DEF("601", CPU_POWERPC_601, 601),
7297 /* PowerPC 601v0 */ 7581 /* PowerPC 601v0 */
7298 - POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601), 7582 + POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
7299 /* PowerPC 601v1 */ 7583 /* PowerPC 601v1 */
7300 - POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601), 7584 + POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
  7585 + /* PowerPC 601v */
  7586 + POWERPC_DEF("601v", CPU_POWERPC_601, 601v),
7301 /* PowerPC 601v2 */ 7587 /* PowerPC 601v2 */
7302 - POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601), 7588 + POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
7303 /* PowerPC 602 */ 7589 /* PowerPC 602 */
7304 POWERPC_DEF("602", CPU_POWERPC_602, 602), 7590 POWERPC_DEF("602", CPU_POWERPC_602, 602),
7305 /* PowerPC 603 */ 7591 /* PowerPC 603 */
7306 POWERPC_DEF("603", CPU_POWERPC_603, 603), 7592 POWERPC_DEF("603", CPU_POWERPC_603, 603),
7307 /* Code name for PowerPC 603 */ 7593 /* Code name for PowerPC 603 */
7308 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603), 7594 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
7309 - /* PowerPC 603e */ 7595 + /* PowerPC 603e (aka PID6) */
7310 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E), 7596 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
7311 /* Code name for PowerPC 603e */ 7597 /* Code name for PowerPC 603e */
7312 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E), 7598 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
@@ -7326,7 +7612,7 @@ static const ppc_def_t ppc_defs[] = { @@ -7326,7 +7612,7 @@ static const ppc_def_t ppc_defs[] = {
7326 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E), 7612 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
7327 /* PowerPC 603e v4.1 */ 7613 /* PowerPC 603e v4.1 */
7328 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E), 7614 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
7329 - /* PowerPC 603e */ 7615 + /* PowerPC 603e (aka PID7) */
7330 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E), 7616 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
7331 /* PowerPC 603e7t */ 7617 /* PowerPC 603e7t */
7332 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E), 7618 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
@@ -7338,38 +7624,41 @@ static const ppc_def_t ppc_defs[] = { @@ -7338,38 +7624,41 @@ static const ppc_def_t ppc_defs[] = {
7338 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E), 7624 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
7339 /* PowerPC 603e7v2 */ 7625 /* PowerPC 603e7v2 */
7340 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E), 7626 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
7341 - /* PowerPC 603p */  
7342 - /* to be checked */  
7343 - POWERPC_DEF("603p", CPU_POWERPC_603P, 603),  
7344 - /* PowerPC 603r */ 7627 + /* PowerPC 603p (aka PID7v) */
  7628 + POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
  7629 + /* PowerPC 603r (aka PID7t) */
7345 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E), 7630 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
7346 /* Code name for PowerPC 603r */ 7631 /* Code name for PowerPC 603r */
7347 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E), 7632 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
7348 /* PowerPC 604 */ 7633 /* PowerPC 604 */
7349 POWERPC_DEF("604", CPU_POWERPC_604, 604), 7634 POWERPC_DEF("604", CPU_POWERPC_604, 604),
7350 - /* PowerPC 604e */  
7351 - /* XXX: code names "Sirocco" "Mach 5" */  
7352 - POWERPC_DEF("604e", CPU_POWERPC_604E, 604), 7635 + /* PowerPC 604e (aka PID9) */
  7636 + POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
  7637 + /* Code name for PowerPC 604e */
  7638 + POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
7353 /* PowerPC 604e v1.0 */ 7639 /* PowerPC 604e v1.0 */
7354 - POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604), 7640 + POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
7355 /* PowerPC 604e v2.2 */ 7641 /* PowerPC 604e v2.2 */
7356 - POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604), 7642 + POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
7357 /* PowerPC 604e v2.4 */ 7643 /* PowerPC 604e v2.4 */
7358 - POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604),  
7359 - /* PowerPC 604r */  
7360 - POWERPC_DEF("604r", CPU_POWERPC_604R, 604), 7644 + POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
  7645 + /* PowerPC 604r (aka PIDA) */
  7646 + POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
  7647 + /* Code name for PowerPC 604r */
  7648 + POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
7361 #if defined(TODO) 7649 #if defined(TODO)
7362 /* PowerPC 604ev */ 7650 /* PowerPC 604ev */
7363 - POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604), 7651 + POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
7364 #endif 7652 #endif
7365 /* PowerPC 7xx family */ 7653 /* PowerPC 7xx family */
7366 /* Generic PowerPC 740 (G3) */ 7654 /* Generic PowerPC 740 (G3) */
7367 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0), 7655 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
  7656 + /* Code name for PowerPC 740 */
  7657 + POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
7368 /* Generic PowerPC 750 (G3) */ 7658 /* Generic PowerPC 750 (G3) */
7369 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0), 7659 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
7370 - /* Code name for generic PowerPC 740/750 (G3) */  
7371 - POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),  
7372 - /* XXX: 750 codename "Typhoon" */ 7660 + /* Code name for PowerPC 750 */
  7661 + POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 7x0),
7373 /* PowerPC 740/750 is also known as G3 */ 7662 /* PowerPC 740/750 is also known as G3 */
7374 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0), 7663 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
7375 /* PowerPC 740 v2.0 (G3) */ 7664 /* PowerPC 740 v2.0 (G3) */
@@ -7411,17 +7700,17 @@ static const ppc_def_t ppc_defs[] = { @@ -7411,17 +7700,17 @@ static const ppc_def_t ppc_defs[] = {
7411 /* PowerPC 750CXe (G3 embedded) */ 7700 /* PowerPC 750CXe (G3 embedded) */
7412 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0), 7701 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
7413 /* PowerPC 750CXe v2.1 (G3 embedded) */ 7702 /* PowerPC 750CXe v2.1 (G3 embedded) */
7414 - POWERPC_DEF("750cxe_v21", CPU_POWERPC_750CXE_v21, 7x0), 7703 + POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 7x0),
7415 /* PowerPC 750CXe v2.2 (G3 embedded) */ 7704 /* PowerPC 750CXe v2.2 (G3 embedded) */
7416 - POWERPC_DEF("750cxe_v22", CPU_POWERPC_750CXE_v22, 7x0), 7705 + POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 7x0),
7417 /* PowerPC 750CXe v2.3 (G3 embedded) */ 7706 /* PowerPC 750CXe v2.3 (G3 embedded) */
7418 - POWERPC_DEF("750cxe_v23", CPU_POWERPC_750CXE_v23, 7x0), 7707 + POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 7x0),
7419 /* PowerPC 750CXe v2.4 (G3 embedded) */ 7708 /* PowerPC 750CXe v2.4 (G3 embedded) */
7420 - POWERPC_DEF("750cxe_v24", CPU_POWERPC_750CXE_v24, 7x0), 7709 + POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 7x0),
7421 /* PowerPC 750CXe v2.4b (G3 embedded) */ 7710 /* PowerPC 750CXe v2.4b (G3 embedded) */
7422 - POWERPC_DEF("750cxe_v24b", CPU_POWERPC_750CXE_v24b, 7x0), 7711 + POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 7x0),
7423 /* PowerPC 750CXe v3.1 (G3 embedded) */ 7712 /* PowerPC 750CXe v3.1 (G3 embedded) */
7424 - POWERPC_DEF("750cxe_v31", CPU_POWERPC_750CXE_v31, 7x0), 7713 + POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 7x0),
7425 /* PowerPC 750CXe v3.1b (G3 embedded) */ 7714 /* PowerPC 750CXe v3.1b (G3 embedded) */
7426 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0), 7715 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
7427 /* PowerPC 750CXr (G3 embedded) */ 7716 /* PowerPC 750CXr (G3 embedded) */
@@ -7623,8 +7912,6 @@ static const ppc_def_t ppc_defs[] = { @@ -7623,8 +7912,6 @@ static const ppc_def_t ppc_defs[] = {
7623 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445), 7912 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
7624 /* PowerPC 7457 v1.0 (G4) */ 7913 /* PowerPC 7457 v1.0 (G4) */
7625 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455), 7914 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
7626 - /* Code name for PowerPC 7447A/7457A */  
7627 - POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),  
7628 /* PowerPC 7447 v1.1 (G4) */ 7915 /* PowerPC 7447 v1.1 (G4) */
7629 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445), 7916 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
7630 /* PowerPC 7457 v1.1 (G4) */ 7917 /* PowerPC 7457 v1.1 (G4) */
@@ -7633,16 +7920,37 @@ static const ppc_def_t ppc_defs[] = { @@ -7633,16 +7920,37 @@ static const ppc_def_t ppc_defs[] = {
7633 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445), 7920 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
7634 /* PowerPC 7457 v1.2 (G4) */ 7921 /* PowerPC 7457 v1.2 (G4) */
7635 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455), 7922 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
  7923 + /* PowerPC 7447A (G4) */
  7924 + POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
  7925 + /* PowerPC 7457A (G4) */
  7926 + POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
  7927 + /* PowerPC 7447A v1.0 (G4) */
  7928 + POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
  7929 + /* PowerPC 7457A v1.0 (G4) */
  7930 + POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
  7931 + /* Code name for PowerPC 7447A/7457A */
  7932 + POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
  7933 + /* PowerPC 7447A v1.1 (G4) */
  7934 + POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
  7935 + /* PowerPC 7457A v1.1 (G4) */
  7936 + POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
  7937 + /* PowerPC 7447A v1.2 (G4) */
  7938 + POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
  7939 + /* PowerPC 7457A v1.2 (G4) */
  7940 + POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
7636 /* 64 bits PowerPC */ 7941 /* 64 bits PowerPC */
7637 #if defined (TARGET_PPC64) 7942 #if defined (TARGET_PPC64)
7638 /* PowerPC 620 */ 7943 /* PowerPC 620 */
7639 - /* XXX: code name "Trident" */  
7640 POWERPC_DEF("620", CPU_POWERPC_620, 620), 7944 POWERPC_DEF("620", CPU_POWERPC_620, 620),
  7945 + /* Code name for PowerPC 620 */
  7946 + POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
7641 #if defined (TODO) 7947 #if defined (TODO)
7642 /* PowerPC 630 (POWER3) */ 7948 /* PowerPC 630 (POWER3) */
7643 - /* XXX: code names: "Boxer" "Dino" */  
7644 POWERPC_DEF("630", CPU_POWERPC_630, 630), 7949 POWERPC_DEF("630", CPU_POWERPC_630, 630),
7645 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630), 7950 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
  7951 + /* Code names for POWER3 */
  7952 + POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
  7953 + POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
7646 #endif 7954 #endif
7647 #if defined (TODO) 7955 #if defined (TODO)
7648 /* PowerPC 631 (Power 3+) */ 7956 /* PowerPC 631 (Power 3+) */