gwj / at91sam9263 · Commits

Commit 0650f1ab3042f05e9bf8ed9fe3d4dc130b38f162

Authored by aliguori
1 parent 2c99f725

Add additional CPU flag definitions 

Some x86 CPU definitions that KVM needs

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5625 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 8 additions and 1 deletions
target-i386/cpu.h
  View file @0650f1a
... ... @@ -159,9 +159,11 @@
159 159 #define HF_MP_MASK (1 << HF_MP_SHIFT)
160 160 #define HF_EM_MASK (1 << HF_EM_SHIFT)
161 161 #define HF_TS_MASK (1 << HF_TS_SHIFT)
  162 +#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
162 163 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
163 164 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
164 165 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
  166 +#define HF_VM_MASK (1 << HF_VM_SHIFT)
165 167 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
166 168 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
167 169 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
... ... @@ -178,6 +180,9 @@
178 180 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
179 181 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
180 182  
  183 +#define CR0_PE_SHIFT 0
  184 +#define CR0_MP_SHIFT 1
  185 +
181 186 #define CR0_PE_MASK (1 << 0)
182 187 #define CR0_MP_MASK (1 << 1)
183 188 #define CR0_EM_MASK (1 << 2)
... ... @@ -196,7 +201,8 @@
196 201 #define CR4_PAE_MASK (1 << 5)
197 202 #define CR4_PGE_MASK (1 << 7)
198 203 #define CR4_PCE_MASK (1 << 8)
199   -#define CR4_OSFXSR_MASK (1 << 9)
  204 +#define CR4_OSFXSR_SHIFT 9
  205 +#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
200 206 #define CR4_OSXMMEXCPT_MASK (1 << 10)
201 207  
202 208 #define PG_PRESENT_BIT 0
... ... @@ -229,6 +235,7 @@
229 235 #define PG_ERROR_RSVD_MASK 0x08
230 236 #define PG_ERROR_I_D_MASK 0x10
231 237  
  238 +#define MSR_IA32_TSC 0x10
232 239 #define MSR_IA32_APICBASE 0x1b
233 240 #define MSR_IA32_APICBASE_BSP (1<<8)
234 241 #define MSR_IA32_APICBASE_ENABLE (1<<11)
... ...