gwj / at91sam9263 · Commits

Commit 05ba7d5f3476de8b573aed43229bbcf0ffda4b69

Authored by edgar_igl
1 parent 786c02f1

A first small step to convert the CRIS translator to TCG. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4057 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 312 additions and 344 deletions
target-cris/translate.c
  View file @05ba7d5
1 1 /*
2 2 * CRIS emulation for qemu: main translation routines.
3 3 *
4   - * Copyright (c) 2007 AXIS Communications AB
  4 + * Copyright (c) 2008 AXIS Communications AB
5 5 * Written by Edgar E. Iglesias.
6 6 *
7 7 * This library is free software; you can redistribute it and/or
... ... @@ -19,28 +19,6 @@
19 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 20 */
21 21  
22   -/*
23   - * This file implements a CRIS decoder-stage in SW. The decoder translates the
24   - * guest (CRIS) machine-code into host machine code via dyngen using the
25   - * micro-operations described in op.c
26   - *
27   - * The micro-operations for CRIS translation implement a RISC style ISA.
28   - * Note that the micro-operations typically order their operands
29   - * starting with the dst. CRIS asm, does the opposite.
30   - *
31   - * For example the following CRIS code:
32   - * add.d [$r0], $r1
33   - *
34   - * translates into:
35   - *
36   - * gen_movl_T0_reg(0); // Fetch $r0 into T0
37   - * gen_load_T0_T0(); // Load T0, @T0
38   - * gen_movl_reg_T0(1); // Writeback T0 into $r1
39   - *
40   - * The actual names for the micro-code generators vary but the example
41   - * illustrates the point.
42   - */
43   -
44 22 #include <stdarg.h>
45 23 #include <stdlib.h>
46 24 #include <stdio.h>
... ... @@ -52,6 +30,7 @@
52 30 #include "exec-all.h"
53 31 #include "disas.h"
54 32 #include "tcg-op.h"
  33 +#include "helper.h"
55 34 #include "crisv32-decode.h"
56 35  
57 36 #define CRIS_STATS 0
... ... @@ -82,6 +61,8 @@
82 61 #define CC_MASK_NZVC 0xf
83 62 #define CC_MASK_RNZV 0x10e
84 63  
  64 +TCGv cpu_env, cpu_T[2];
  65 +
85 66 /* This is the state at translation time. */
86 67 typedef struct DisasContext {
87 68 CPUState *env;
... ... @@ -128,92 +109,6 @@ static void gen_BUG(DisasContext *dc, char *file, int line)
128 109 cris_prepare_jmp (dc, 0x70000000 + line);
129 110 }
130 111  
131   -/* Table to generate quick moves from T0 onto any register. */
132   -static GenOpFunc *gen_movl_reg_T0[16] =
133   -{
134   - gen_op_movl_r0_T0, gen_op_movl_r1_T0,
135   - gen_op_movl_r2_T0, gen_op_movl_r3_T0,
136   - gen_op_movl_r4_T0, gen_op_movl_r5_T0,
137   - gen_op_movl_r6_T0, gen_op_movl_r7_T0,
138   - gen_op_movl_r8_T0, gen_op_movl_r9_T0,
139   - gen_op_movl_r10_T0, gen_op_movl_r11_T0,
140   - gen_op_movl_r12_T0, gen_op_movl_r13_T0,
141   - gen_op_movl_r14_T0, gen_op_movl_r15_T0,
142   -};
143   -static GenOpFunc *gen_movl_T0_reg[16] =
144   -{
145   - gen_op_movl_T0_r0, gen_op_movl_T0_r1,
146   - gen_op_movl_T0_r2, gen_op_movl_T0_r3,
147   - gen_op_movl_T0_r4, gen_op_movl_T0_r5,
148   - gen_op_movl_T0_r6, gen_op_movl_T0_r7,
149   - gen_op_movl_T0_r8, gen_op_movl_T0_r9,
150   - gen_op_movl_T0_r10, gen_op_movl_T0_r11,
151   - gen_op_movl_T0_r12, gen_op_movl_T0_r13,
152   - gen_op_movl_T0_r14, gen_op_movl_T0_r15,
153   -};
154   -
155   -static void noop_write(void) {
156   - /* nop. */
157   -}
158   -
159   -static void gen_vr_read(void) {
160   - gen_op_movl_T0_im(32);
161   -}
162   -
163   -static void gen_movl_T0_p0(void) {
164   - gen_op_movl_T0_im(0);
165   -}
166   -
167   -static void gen_ccs_read(void) {
168   - gen_op_movl_T0_p13();
169   -}
170   -
171   -static void gen_ccs_write(void) {
172   - gen_op_movl_p13_T0();
173   -}
174   -
175   -/* Table to generate quick moves from T0 onto any register. */
176   -static GenOpFunc *gen_movl_preg_T0[16] =
177   -{
178   - noop_write, /* bz, not writeable. */
179   - noop_write, /* vr, not writeable. */
180   - gen_op_movl_p2_T0, gen_op_movl_p3_T0,
181   - noop_write, /* wz, not writeable. */
182   - gen_op_movl_p5_T0,
183   - gen_op_movl_p6_T0, gen_op_movl_p7_T0,
184   - noop_write, /* dz, not writeable. */
185   - gen_op_movl_p9_T0,
186   - gen_op_movl_p10_T0, gen_op_movl_p11_T0,
187   - gen_op_movl_p12_T0,
188   - gen_ccs_write, /* ccs needs special treatment. */
189   - gen_op_movl_p14_T0, gen_op_movl_p15_T0,
190   -};
191   -static GenOpFunc *gen_movl_T0_preg[16] =
192   -{
193   - gen_movl_T0_p0,
194   - gen_vr_read,
195   - gen_op_movl_T0_p2, gen_op_movl_T0_p3,
196   - gen_op_movl_T0_p4, gen_op_movl_T0_p5,
197   - gen_op_movl_T0_p6, gen_op_movl_T0_p7,
198   - gen_op_movl_T0_p8, gen_op_movl_T0_p9,
199   - gen_op_movl_T0_p10, gen_op_movl_T0_p11,
200   - gen_op_movl_T0_p12,
201   - gen_ccs_read, /* ccs needs special treatment. */
202   - gen_op_movl_T0_p14, gen_op_movl_T0_p15,
203   -};
204   -
205   -/* We need this table to handle moves with implicit width. */
206   -int preg_sizes[] = {
207   - 1, /* bz. */
208   - 1, /* vr. */
209   - 4, /* pid. */
210   - 1, /* srs. */
211   - 2, /* wz. */
212   - 4, 4, 4,
213   - 4, 4, 4, 4,
214   - 4, 4, 4, 4,
215   -};
216   -
217 112 #ifdef CONFIG_USER_ONLY
218 113 #define GEN_OP_LD(width, reg) \
219 114 void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \
... ... @@ -245,18 +140,112 @@ GEN_OP_ST(w, T0)
245 140 GEN_OP_LD(l, T0)
246 141 GEN_OP_ST(l, T0)
247 142  
  143 +/* We need this table to handle preg-moves with implicit width. */
  144 +int preg_sizes[] = {
  145 + 1, /* bz. */
  146 + 1, /* vr. */
  147 + 4, /* pid. */
  148 + 1, /* srs. */
  149 + 2, /* wz. */
  150 + 4, 4, 4,
  151 + 4, 4, 4, 4,
  152 + 4, 4, 4, 4,
  153 +};
  154 +
  155 +#define t_gen_mov_TN_env(tn, member) \
  156 + _t_gen_mov_TN_env((tn), offsetof(CPUState, (member)))
  157 +#define t_gen_mov_env_TN(member, tn) \
  158 + _t_gen_mov_env_TN(offsetof(CPUState, (member)), (tn))
  159 +
  160 +#define t_gen_mov_TN_reg(tn, regno) \
  161 + _t_gen_mov_TN_env((tn), offsetof(CPUState, regs[regno]))
  162 +#define t_gen_mov_reg_TN(regno, tn) \
  163 + _t_gen_mov_env_TN(offsetof(CPUState, regs[regno]), (tn))
  164 +
  165 +static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
  166 +{
  167 + tcg_gen_ld_tl(tn, cpu_env, offset);
  168 +}
  169 +static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
  170 +{
  171 + tcg_gen_st_tl(tn, cpu_env, offset);
  172 +}
  173 +
  174 +static inline void t_gen_mov_TN_preg(TCGv tn, int r)
  175 +{
  176 + if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
  177 + tcg_gen_mov_tl(tn, tcg_const_i32(0));
  178 + else if (r == PR_VR)
  179 + tcg_gen_mov_tl(tn, tcg_const_i32(32));
  180 + else
  181 + tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, pregs[r]));
  182 +}
  183 +static inline void t_gen_mov_preg_TN(int r, TCGv tn)
  184 +{
  185 + if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
  186 + return;
  187 + else
  188 + tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, pregs[r]));
  189 +}
  190 +
  191 +static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
  192 +{
  193 + tcg_gen_movi_tl(tn, val);
  194 +}
  195 +
  196 +static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
  197 +{
  198 + int l1;
  199 +
  200 + l1 = gen_new_label();
  201 + /* Speculative shift. */
  202 + tcg_gen_shl_tl(d, a, b);
  203 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  204 + /* Clear dst if shift operands were to large. */
  205 + tcg_gen_movi_tl(d, 0);
  206 + gen_set_label(l1);
  207 +}
  208 +
  209 +static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
  210 +{
  211 + int l1;
  212 +
  213 + l1 = gen_new_label();
  214 + /* Speculative shift. */
  215 + tcg_gen_shr_tl(d, a, b);
  216 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  217 + /* Clear dst if shift operands were to large. */
  218 + tcg_gen_movi_tl(d, 0);
  219 + gen_set_label(l1);
  220 +}
  221 +
  222 +static void t_gen_asr(TCGv d, TCGv a, TCGv b)
  223 +{
  224 + int l1;
  225 +
  226 + l1 = gen_new_label();
  227 + /* Speculative shift. */
  228 + tcg_gen_sar_tl(d, a, b);
  229 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  230 + /* Clear dst if shift operands were to large. */
  231 + tcg_gen_movi_tl(d, 0);
  232 + tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_i32(0x80000000), l1);
  233 + tcg_gen_movi_tl(d, 0xffffffff);
  234 + gen_set_label(l1);
  235 +}
  236 +
248 237 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
249 238 {
250 239 TranslationBlock *tb;
251 240 tb = dc->tb;
252 241 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
253   -#if 0
254   - /* XXX: this code is not finished */
255   - tcg_gen_goto_tb(n);
256   -#endif
257   - tcg_gen_exit_tb(0);
  242 + tcg_gen_goto_tb(n);
  243 + tcg_gen_movi_tl(cpu_T[0], dest);
  244 + gen_op_movl_pc_T0();
  245 + tcg_gen_exit_tb((long)tb + n);
258 246 } else {
259   - tcg_gen_exit_tb(0);
  247 + gen_op_movl_pc_T0();
  248 + tcg_gen_exit_tb(0);
260 249 }
261 250 }
262 251  
... ... @@ -273,10 +262,22 @@ static int sign_extend(unsigned int val, unsigned int width)
273 262 return sval;
274 263 }
275 264  
  265 +static inline void cris_clear_x_flag(DisasContext *dc)
  266 +{
  267 + TCGv ccs;
  268 +
  269 + ccs = tcg_temp_new(TCG_TYPE_TL);
  270 +
  271 + t_gen_mov_TN_preg(ccs, PR_CCS);
  272 + tcg_gen_andi_i32(ccs, ccs, ~X_FLAG);
  273 + t_gen_mov_preg_TN(PR_CCS, ccs);
  274 + dc->flagx_live = 1;
  275 + dc->flags_x = 0;
  276 +}
  277 +
276 278 static void cris_evaluate_flags(DisasContext *dc)
277 279 {
278 280 if (!dc->flags_live) {
279   -
280 281 switch (dc->cc_op)
281 282 {
282 283 case CC_OP_MCP:
... ... @@ -373,7 +374,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
373 374 switch (op)
374 375 {
375 376 case CC_OP_ADD:
376   - gen_op_addl_T0_T1();
  377 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
377 378 /* Extended arithmetics. */
378 379 if (!dc->flagx_live)
379 380 gen_op_addxl_T0_C();
... ... @@ -381,18 +382,18 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
381 382 gen_op_addxl_T0_C();
382 383 break;
383 384 case CC_OP_ADDC:
384   - gen_op_addl_T0_T1();
  385 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
385 386 gen_op_addl_T0_C();
386 387 break;
387 388 case CC_OP_MCP:
388   - gen_op_addl_T0_T1();
  389 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
389 390 gen_op_addl_T0_R();
390 391 break;
391 392 case CC_OP_SUB:
392   - gen_op_negl_T1_T1();
393   - gen_op_addl_T0_T1();
  393 + tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
  394 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
394 395 /* CRIS flag evaluation needs ~src. */
395   - gen_op_negl_T1_T1();
  396 + tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
396 397 gen_op_not_T1_T1();
397 398  
398 399 /* Extended arithmetics. */
... ... @@ -402,28 +403,30 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
402 403 gen_op_subxl_T0_C();
403 404 break;
404 405 case CC_OP_MOVE:
405   - gen_op_movl_T0_T1();
  406 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
406 407 break;
407 408 case CC_OP_OR:
408   - gen_op_orl_T0_T1();
  409 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
409 410 break;
410 411 case CC_OP_AND:
411   - gen_op_andl_T0_T1();
  412 + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
412 413 break;
413 414 case CC_OP_XOR:
414   - gen_op_xorl_T0_T1();
  415 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
415 416 break;
416 417 case CC_OP_LSL:
417   - gen_op_lsll_T0_T1();
  418 + t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
418 419 break;
419 420 case CC_OP_LSR:
420   - gen_op_lsrl_T0_T1();
  421 + t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
421 422 break;
422 423 case CC_OP_ASR:
423   - gen_op_asrl_T0_T1();
  424 + t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
424 425 break;
425 426 case CC_OP_NEG:
426   - gen_op_negl_T0_T1();
  427 + /* TCG-FIXME: this is not optimal. Many archs have
  428 + fast neg insns. */
  429 + tcg_gen_sub_tl(cpu_T[0], tcg_const_i32(0), cpu_T[1]);
427 430 /* Extended arithmetics. */
428 431 gen_op_subxl_T0_C();
429 432 break;
... ... @@ -447,10 +450,11 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
447 450 gen_op_bound_T0_T1();
448 451 break;
449 452 case CC_OP_CMP:
450   - gen_op_negl_T1_T1();
451   - gen_op_addl_T0_T1();
  453 + tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
  454 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  455 + /* CRIS flag evaluation needs ~src. */
  456 + tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
452 457 /* CRIS flag evaluation needs ~src. */
453   - gen_op_negl_T1_T1();
454 458 gen_op_not_T1_T1();
455 459  
456 460 /* Extended arithmetics. */
... ... @@ -467,23 +471,24 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
467 471 gen_op_update_cc_src_T1();
468 472  
469 473 if (size == 1)
470   - gen_op_andl_T0_im(0xff);
  474 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
471 475 else if (size == 2)
472   - gen_op_andl_T0_im(0xffff);
  476 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  477 +
473 478 /* Writeback. */
474 479 if (writeback) {
475 480 if (size == 4)
476   - gen_movl_reg_T0[rd]();
  481 + t_gen_mov_reg_TN(rd, cpu_T[0]);
477 482 else {
478   - gen_op_movl_T1_T0();
479   - gen_movl_T0_reg[rd]();
  483 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
  484 + t_gen_mov_TN_reg(cpu_T[0], rd);
480 485 if (size == 1)
481   - gen_op_andl_T0_im(~0xff);
  486 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
482 487 else
483   - gen_op_andl_T0_im(~0xffff);
484   - gen_op_orl_T0_T1();
485   - gen_movl_reg_T0[rd]();
486   - gen_op_movl_T0_T1();
  488 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
  489 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  490 + t_gen_mov_reg_TN(rd, cpu_T[0]);
  491 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
487 492 }
488 493 }
489 494 if (dc->update_cc)
... ... @@ -674,53 +679,21 @@ void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
674 679 gen_op_stl_T0_T1(dc);
675 680 }
676 681  
677   -/* sign extend T1 according to size. */
678   -static void gen_sext_T1_T0(int size)
679   -{
680   - if (size == 1)
681   - gen_op_extb_T1_T0();
682   - else if (size == 2)
683   - gen_op_extw_T1_T0();
684   -}
685   -
686   -static void gen_sext_T1_T1(int size)
687   -{
688   - if (size == 1)
689   - gen_op_extb_T1_T1();
690   - else if (size == 2)
691   - gen_op_extw_T1_T1();
692   -}
693   -
694   -static void gen_sext_T0_T0(int size)
695   -{
696   - if (size == 1)
697   - gen_op_extb_T0_T0();
698   - else if (size == 2)
699   - gen_op_extw_T0_T0();
700   -}
701   -
702   -static void gen_zext_T0_T0(int size)
703   -{
704   - if (size == 1)
705   - gen_op_zextb_T0_T0();
706   - else if (size == 2)
707   - gen_op_zextw_T0_T0();
708   -}
709   -
710   -static void gen_zext_T1_T0(int size)
  682 +static inline void t_gen_sext(TCGv d, TCGv s, int size)
711 683 {
712 684 if (size == 1)
713   - gen_op_zextb_T1_T0();
  685 + tcg_gen_ext8s_i32(d, s);
714 686 else if (size == 2)
715   - gen_op_zextw_T1_T0();
  687 + tcg_gen_ext16s_i32(d, s);
716 688 }
717 689  
718   -static void gen_zext_T1_T1(int size)
  690 +static inline void t_gen_zext(TCGv d, TCGv s, int size)
719 691 {
  692 + /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
720 693 if (size == 1)
721   - gen_op_zextb_T1_T1();
  694 + tcg_gen_andi_i32(d, s, 0xff);
722 695 else if (size == 2)
723   - gen_op_zextw_T1_T1();
  696 + tcg_gen_andi_i32(d, s, 0xffff);
724 697 }
725 698  
726 699 #if DISAS_CRIS
... ... @@ -758,21 +731,20 @@ static void do_postinc (DisasContext *dc, int size)
758 731 {
759 732 if (!dc->postinc)
760 733 return;
761   - gen_movl_T0_reg[dc->op1]();
  734 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
762 735 gen_op_addl_T0_im(size);
763   - gen_movl_reg_T0[dc->op1]();
  736 + t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
764 737 }
765 738  
766 739  
767 740 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
768 741 int size, int s_ext)
769 742 {
770   - gen_movl_T0_reg[rs]();
771   - gen_op_movl_T1_T0();
  743 + t_gen_mov_TN_reg(cpu_T[1], rs);
772 744 if (s_ext)
773   - gen_sext_T1_T1(size);
  745 + t_gen_sext(cpu_T[1], cpu_T[1], size);
774 746 else
775   - gen_zext_T1_T1(size);
  747 + t_gen_zext(cpu_T[1], cpu_T[1], size);
776 748 }
777 749  
778 750 /* Prepare T0 and T1 for a register alu operation.
... ... @@ -783,11 +755,11 @@ static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
783 755 {
784 756 dec_prep_move_r(dc, rs, rd, size, s_ext);
785 757  
786   - gen_movl_T0_reg[rd]();
  758 + t_gen_mov_TN_reg(cpu_T[0], rd);
787 759 if (s_ext)
788   - gen_sext_T0_T0(size);
  760 + t_gen_sext(cpu_T[0], cpu_T[0], size);
789 761 else
790   - gen_zext_T0_T0(size);
  762 + t_gen_zext(cpu_T[0], cpu_T[0], size);
791 763 }
792 764  
793 765 /* Prepare T0 and T1 for a memory + alu operation.
... ... @@ -823,20 +795,20 @@ static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
823 795 }
824 796 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
825 797 imm, rd, s_ext, memsize));
826   - gen_op_movl_T1_im (imm);
  798 + tcg_gen_movi_tl(cpu_T[1], imm);
827 799 dc->postinc = 0;
828 800 } else {
829   - gen_movl_T0_reg[rs]();
  801 + t_gen_mov_TN_reg(cpu_T[0], rs);
830 802 gen_load_T0_T0(dc, memsize, 0);
831   - gen_op_movl_T1_T0();
  803 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
832 804 if (s_ext)
833   - gen_sext_T1_T1(memsize);
  805 + t_gen_sext(cpu_T[1], cpu_T[1], memsize);
834 806 else
835   - gen_zext_T1_T1(memsize);
  807 + t_gen_zext(cpu_T[1], cpu_T[1], memsize);
836 808 }
837 809  
838 810 /* put dest in T0. */
839   - gen_movl_T0_reg[rd]();
  811 + t_gen_mov_TN_reg(cpu_T[0], rd);
840 812 return insn_len;
841 813 }
842 814  
... ... @@ -882,8 +854,8 @@ static unsigned int dec_addoq(DisasContext *dc)
882 854 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
883 855 cris_cc_mask(dc, 0);
884 856 /* Fetch register operand, */
885   - gen_movl_T0_reg[dc->op2]();
886   - gen_op_movl_T1_im(imm);
  857 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  858 + tcg_gen_movi_tl(cpu_T[1], imm);
887 859 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
888 860 return 2;
889 861 }
... ... @@ -895,8 +867,8 @@ static unsigned int dec_addq(DisasContext *dc)
895 867  
896 868 cris_cc_mask(dc, CC_MASK_NZVC);
897 869 /* Fetch register operand, */
898   - gen_movl_T0_reg[dc->op2]();
899   - gen_op_movl_T1_im(dc->op1);
  870 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  871 + tcg_gen_movi_tl(cpu_T[1], dc->op1);
900 872 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
901 873 return 2;
902 874 }
... ... @@ -908,10 +880,9 @@ static unsigned int dec_moveq(DisasContext *dc)
908 880 imm = sign_extend(dc->op1, 5);
909 881 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
910 882  
911   - cris_cc_mask(dc, 0);
912   - gen_op_movl_T1_im(imm);
913   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
914   -
  883 + t_gen_mov_reg_TN(dc->op2, tcg_const_i32(imm));
  884 + if (!dc->flagx_live || dc->flags_x)
  885 + cris_clear_x_flag(dc);
915 886 return 2;
916 887 }
917 888 static unsigned int dec_subq(DisasContext *dc)
... ... @@ -922,8 +893,8 @@ static unsigned int dec_subq(DisasContext *dc)
922 893  
923 894 cris_cc_mask(dc, CC_MASK_NZVC);
924 895 /* Fetch register operand, */
925   - gen_movl_T0_reg[dc->op2]();
926   - gen_op_movl_T1_im(dc->op1);
  896 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  897 + t_gen_mov_TN_im(cpu_T[1], dc->op1);
927 898 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
928 899 return 2;
929 900 }
... ... @@ -935,8 +906,8 @@ static unsigned int dec_cmpq(DisasContext *dc)
935 906  
936 907 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
937 908 cris_cc_mask(dc, CC_MASK_NZVC);
938   - gen_movl_T0_reg[dc->op2]();
939   - gen_op_movl_T1_im(imm);
  909 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  910 + t_gen_mov_TN_im(cpu_T[1], imm);
940 911 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
941 912 return 2;
942 913 }
... ... @@ -948,8 +919,8 @@ static unsigned int dec_andq(DisasContext *dc)
948 919  
949 920 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
950 921 cris_cc_mask(dc, CC_MASK_NZ);
951   - gen_movl_T0_reg[dc->op2]();
952   - gen_op_movl_T1_im(imm);
  922 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  923 + t_gen_mov_TN_im(cpu_T[1], imm);
953 924 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
954 925 return 2;
955 926 }
... ... @@ -960,8 +931,8 @@ static unsigned int dec_orq(DisasContext *dc)
960 931 imm = sign_extend(dc->op1, 5);
961 932 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
962 933 cris_cc_mask(dc, CC_MASK_NZ);
963   - gen_movl_T0_reg[dc->op2]();
964   - gen_op_movl_T1_im(imm);
  934 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  935 + t_gen_mov_TN_im(cpu_T[1], imm);
965 936 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
966 937 return 2;
967 938 }
... ... @@ -970,8 +941,8 @@ static unsigned int dec_btstq(DisasContext *dc)
970 941 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
971 942 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
972 943 cris_cc_mask(dc, CC_MASK_NZ);
973   - gen_movl_T0_reg[dc->op2]();
974   - gen_op_movl_T1_im(dc->op1);
  944 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  945 + t_gen_mov_TN_im(cpu_T[1], dc->op1);
975 946 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
976 947  
977 948 cris_update_cc_op(dc, CC_OP_FLAGS);
... ... @@ -984,8 +955,8 @@ static unsigned int dec_asrq(DisasContext *dc)
984 955 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
985 956 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
986 957 cris_cc_mask(dc, CC_MASK_NZ);
987   - gen_movl_T0_reg[dc->op2]();
988   - gen_op_movl_T1_im(dc->op1);
  958 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  959 + t_gen_mov_TN_im(cpu_T[1], dc->op1);
989 960 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
990 961 return 2;
991 962 }
... ... @@ -995,8 +966,8 @@ static unsigned int dec_lslq(DisasContext *dc)
995 966 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
996 967  
997 968 cris_cc_mask(dc, CC_MASK_NZ);
998   - gen_movl_T0_reg[dc->op2]();
999   - gen_op_movl_T1_im(dc->op1);
  969 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  970 + t_gen_mov_TN_im(cpu_T[1], dc->op1);
1000 971 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1001 972 return 2;
1002 973 }
... ... @@ -1006,8 +977,8 @@ static unsigned int dec_lsrq(DisasContext *dc)
1006 977 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1007 978  
1008 979 cris_cc_mask(dc, CC_MASK_NZ);
1009   - gen_movl_T0_reg[dc->op2]();
1010   - gen_op_movl_T1_im(dc->op1);
  980 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  981 + t_gen_mov_TN_im(cpu_T[1], dc->op1);
1011 982 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1012 983 return 2;
1013 984 }
... ... @@ -1075,7 +1046,7 @@ static unsigned int dec_lsl_r(DisasContext *dc)
1075 1046 memsize_char(size), dc->op1, dc->op2));
1076 1047 cris_cc_mask(dc, CC_MASK_NZ);
1077 1048 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1078   - gen_op_andl_T1_im(63);
  1049 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1079 1050 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1080 1051 return 2;
1081 1052 }
... ... @@ -1088,7 +1059,7 @@ static unsigned int dec_lsr_r(DisasContext *dc)
1088 1059 memsize_char(size), dc->op1, dc->op2));
1089 1060 cris_cc_mask(dc, CC_MASK_NZ);
1090 1061 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1091   - gen_op_andl_T1_im(63);
  1062 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1092 1063 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1093 1064 return 2;
1094 1065 }
... ... @@ -1101,7 +1072,7 @@ static unsigned int dec_asr_r(DisasContext *dc)
1101 1072 memsize_char(size), dc->op1, dc->op2));
1102 1073 cris_cc_mask(dc, CC_MASK_NZ);
1103 1074 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1104   - gen_op_andl_T1_im(63);
  1075 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1105 1076 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1106 1077 return 2;
1107 1078 }
... ... @@ -1114,7 +1085,7 @@ static unsigned int dec_muls_r(DisasContext *dc)
1114 1085 memsize_char(size), dc->op1, dc->op2));
1115 1086 cris_cc_mask(dc, CC_MASK_NZV);
1116 1087 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1117   - gen_sext_T0_T0(size);
  1088 + t_gen_sext(cpu_T[0], cpu_T[0], size);
1118 1089 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1119 1090 return 2;
1120 1091 }
... ... @@ -1127,7 +1098,7 @@ static unsigned int dec_mulu_r(DisasContext *dc)
1127 1098 memsize_char(size), dc->op1, dc->op2));
1128 1099 cris_cc_mask(dc, CC_MASK_NZV);
1129 1100 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1130   - gen_zext_T0_T0(size);
  1101 + t_gen_zext(cpu_T[0], cpu_T[0], size);
1131 1102 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1132 1103 return 2;
1133 1104 }
... ... @@ -1137,9 +1108,8 @@ static unsigned int dec_dstep_r(DisasContext *dc)
1137 1108 {
1138 1109 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1139 1110 cris_cc_mask(dc, CC_MASK_NZ);
1140   - gen_movl_T0_reg[dc->op1]();
1141   - gen_op_movl_T1_T0();
1142   - gen_movl_T0_reg[dc->op2]();
  1111 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
  1112 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1143 1113 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1144 1114 return 2;
1145 1115 }
... ... @@ -1165,7 +1135,7 @@ static unsigned int dec_bound_r(DisasContext *dc)
1165 1135 /* TODO: needs optmimization. */
1166 1136 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1167 1137 /* rd should be 4. */
1168   - gen_movl_T0_reg[dc->op2]();
  1138 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1169 1139 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1170 1140 return 2;
1171 1141 }
... ... @@ -1220,9 +1190,8 @@ static unsigned int dec_mcp_r(DisasContext *dc)
1220 1190 dc->op2, dc->op1));
1221 1191 cris_evaluate_flags(dc);
1222 1192 cris_cc_mask(dc, CC_MASK_RNZV);
1223   - gen_movl_T0_preg[dc->op2]();
1224   - gen_op_movl_T1_T0();
1225   - gen_movl_T0_reg[dc->op1]();
  1193 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
  1194 + t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1226 1195 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1227 1196 return 2;
1228 1197 }
... ... @@ -1250,7 +1219,7 @@ static unsigned int dec_swap_r(DisasContext *dc)
1250 1219 swapmode_name(dc->op2, modename), dc->op1));
1251 1220  
1252 1221 cris_cc_mask(dc, CC_MASK_NZ);
1253   - gen_movl_T0_reg[dc->op1]();
  1222 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1254 1223 if (dc->op2 & 8)
1255 1224 gen_op_not_T0_T0();
1256 1225 if (dc->op2 & 4)
... ... @@ -1281,9 +1250,9 @@ static unsigned int dec_addi_r(DisasContext *dc)
1281 1250 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1282 1251 cris_cc_mask(dc, 0);
1283 1252 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1284   - gen_op_lsll_T0_im(dc->zzsize);
1285   - gen_op_addl_T0_T1();
1286   - gen_movl_reg_T0[dc->op1]();
  1253 + t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
  1254 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  1255 + t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1287 1256 return 2;
1288 1257 }
1289 1258  
... ... @@ -1293,9 +1262,10 @@ static unsigned int dec_addi_acr(DisasContext *dc)
1293 1262 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1294 1263 cris_cc_mask(dc, 0);
1295 1264 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1296   - gen_op_lsll_T0_im(dc->zzsize);
1297   - gen_op_addl_T0_T1();
1298   - gen_movl_reg_T0[R_ACR]();
  1265 + t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
  1266 +
  1267 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  1268 + t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1299 1269 return 2;
1300 1270 }
1301 1271  
... ... @@ -1358,9 +1328,9 @@ static unsigned int dec_movs_r(DisasContext *dc)
1358 1328 dc->op1, dc->op2));
1359 1329  
1360 1330 cris_cc_mask(dc, CC_MASK_NZ);
1361   - gen_movl_T0_reg[dc->op1]();
  1331 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1362 1332 /* Size can only be qi or hi. */
1363   - gen_sext_T1_T0(size);
  1333 + t_gen_sext(cpu_T[1], cpu_T[0], size);
1364 1334 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1365 1335 return 2;
1366 1336 }
... ... @@ -1374,13 +1344,14 @@ static unsigned int dec_addu_r(DisasContext *dc)
1374 1344 dc->op1, dc->op2));
1375 1345  
1376 1346 cris_cc_mask(dc, CC_MASK_NZVC);
1377   - gen_movl_T0_reg[dc->op1]();
  1347 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1378 1348 /* Size can only be qi or hi. */
1379   - gen_zext_T1_T0(size);
1380   - gen_movl_T0_reg[dc->op2]();
  1349 + t_gen_zext(cpu_T[1], cpu_T[1], size);
  1350 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1381 1351 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1382 1352 return 2;
1383 1353 }
  1354 +
1384 1355 /* Sign extension. From size to dword. */
1385 1356 static unsigned int dec_adds_r(DisasContext *dc)
1386 1357 {
... ... @@ -1390,10 +1361,11 @@ static unsigned int dec_adds_r(DisasContext *dc)
1390 1361 dc->op1, dc->op2));
1391 1362  
1392 1363 cris_cc_mask(dc, CC_MASK_NZVC);
1393   - gen_movl_T0_reg[dc->op1]();
  1364 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1394 1365 /* Size can only be qi or hi. */
1395   - gen_sext_T1_T0(size);
1396   - gen_movl_T0_reg[dc->op2]();
  1366 + t_gen_sext(cpu_T[1], cpu_T[1], size);
  1367 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  1368 +
1397 1369 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1398 1370 return 2;
1399 1371 }
... ... @@ -1407,10 +1379,10 @@ static unsigned int dec_subu_r(DisasContext *dc)
1407 1379 dc->op1, dc->op2));
1408 1380  
1409 1381 cris_cc_mask(dc, CC_MASK_NZVC);
1410   - gen_movl_T0_reg[dc->op1]();
  1382 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1411 1383 /* Size can only be qi or hi. */
1412   - gen_zext_T1_T0(size);
1413   - gen_movl_T0_reg[dc->op2]();
  1384 + t_gen_zext(cpu_T[1], cpu_T[1], size);
  1385 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1414 1386 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1415 1387 return 2;
1416 1388 }
... ... @@ -1424,10 +1396,10 @@ static unsigned int dec_subs_r(DisasContext *dc)
1424 1396 dc->op1, dc->op2));
1425 1397  
1426 1398 cris_cc_mask(dc, CC_MASK_NZVC);
1427   - gen_movl_T0_reg[dc->op1]();
  1399 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1428 1400 /* Size can only be qi or hi. */
1429   - gen_sext_T1_T0(size);
1430   - gen_movl_T0_reg[dc->op2]();
  1401 + t_gen_sext(cpu_T[1], cpu_T[1], size);
  1402 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1431 1403 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1432 1404 return 2;
1433 1405 }
... ... @@ -1469,29 +1441,34 @@ static unsigned int dec_move_rs(DisasContext *dc)
1469 1441 {
1470 1442 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1471 1443 cris_cc_mask(dc, 0);
1472   - gen_movl_T0_reg[dc->op1]();
  1444 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1473 1445 gen_op_movl_sreg_T0(dc->op2);
1474 1446  
1475   - if (dc->op2 == 5) /* srs is checked at runtime. */
  1447 +#if !defined(CONFIG_USER_ONLY)
  1448 + if (dc->op2 == 6)
  1449 + gen_op_movl_tlb_hi_T0();
  1450 + else if (dc->op2 == 5) { /* srs is checked at runtime. */
  1451 + tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
1476 1452 gen_op_movl_tlb_lo_T0();
  1453 + }
  1454 +#endif
1477 1455 return 2;
1478 1456 }
1479 1457 static unsigned int dec_move_sr(DisasContext *dc)
1480 1458 {
1481   - DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op1, dc->op2));
  1459 + DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1482 1460 cris_cc_mask(dc, 0);
1483   - gen_op_movl_T0_sreg(dc->op1);
1484   - gen_op_movl_T1_T0();
1485   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  1461 + gen_op_movl_T0_sreg(dc->op2);
  1462 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
  1463 + crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1486 1464 return 2;
1487 1465 }
1488 1466 static unsigned int dec_move_rp(DisasContext *dc)
1489 1467 {
1490 1468 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1491 1469 cris_cc_mask(dc, 0);
1492   - gen_movl_T0_reg[dc->op1]();
1493   - gen_op_movl_T1_T0();
1494   - gen_movl_preg_T0[dc->op2]();
  1470 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
  1471 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1495 1472 return 2;
1496 1473 }
1497 1474 static unsigned int dec_move_pr(DisasContext *dc)
... ... @@ -1501,11 +1478,9 @@ static unsigned int dec_move_pr(DisasContext *dc)
1501 1478 /* Support register 0 is hardwired to zero.
1502 1479 Treat it specially. */
1503 1480 if (dc->op2 == 0)
1504   - gen_op_movl_T1_im(0);
1505   - else {
1506   - gen_movl_T0_preg[dc->op2]();
1507   - gen_op_movl_T1_T0();
1508   - }
  1481 + tcg_gen_movi_tl(cpu_T[1], 0);
  1482 + else
  1483 + t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1509 1484 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1510 1485 return 2;
1511 1486 }
... ... @@ -1688,8 +1663,8 @@ static unsigned int dec_test_m(DisasContext *dc)
1688 1663 cris_cc_mask(dc, CC_MASK_NZ);
1689 1664 gen_op_clrf(3);
1690 1665 insn_len = dec_prep_alu_m(dc, 0, memsize);
1691   - gen_op_swp_T0_T1();
1692   - gen_op_movl_T1_im(0);
  1666 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  1667 + tcg_gen_movi_tl(cpu_T[1], 0);
1693 1668 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1694 1669 do_postinc(dc, memsize);
1695 1670 return insn_len;
... ... @@ -1819,8 +1794,7 @@ static unsigned int dec_move_mp(DisasContext *dc)
1819 1794  
1820 1795 cris_cc_mask(dc, 0);
1821 1796 insn_len = dec_prep_alu_m(dc, 0, memsize);
1822   - gen_op_movl_T0_T1();
1823   - gen_movl_preg_T0[dc->op2]();
  1797 + t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
1824 1798  
1825 1799 do_postinc(dc, memsize);
1826 1800 return insn_len;
... ... @@ -1838,21 +1812,13 @@ static unsigned int dec_move_pm(DisasContext *dc)
1838 1812  
1839 1813 cris_cc_mask(dc, 0);
1840 1814 /* prepare store. Address in T0, value in T1. */
1841   - /* Support register 0 is hardwired to zero.
1842   - Treat it specially. */
1843   - if (dc->op2 == 0)
1844   - gen_op_movl_T1_im(0);
1845   - else
1846   - {
1847   - gen_movl_T0_preg[dc->op2]();
1848   - gen_op_movl_T1_T0();
1849   - }
1850   - gen_movl_T0_reg[dc->op1]();
  1815 + t_gen_mov_TN_preg(cpu_T[1], dc->op2);
  1816 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1851 1817 gen_store_T0_T1(dc, memsize);
1852 1818 if (dc->postinc)
1853 1819 {
1854   - gen_op_addl_T0_im(memsize);
1855   - gen_movl_reg_T0[dc->op1]();
  1820 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
  1821 + t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1856 1822 }
1857 1823 return 2;
1858 1824 }
... ... @@ -1865,21 +1831,18 @@ static unsigned int dec_movem_mr(DisasContext *dc)
1865 1831 dc->postinc ? "+]" : "]", dc->op2));
1866 1832  
1867 1833 cris_cc_mask(dc, 0);
1868   - /* fetch the address into T1. */
1869   - gen_movl_T0_reg[dc->op1]();
1870   - gen_op_movl_T1_T0();
  1834 + /* fetch the address into T0 and T1. */
  1835 + t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1871 1836 for (i = 0; i <= dc->op2; i++) {
1872 1837 /* Perform the load onto regnum i. Always dword wide. */
  1838 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1873 1839 gen_load_T0_T0(dc, 4, 0);
1874   - gen_movl_reg_T0[i]();
1875   - /* Update the address. */
1876   - gen_op_addl_T1_im(4);
1877   - gen_op_movl_T0_T1();
1878   - }
1879   - if (dc->postinc) {
1880   - /* writeback the updated pointer value. */
1881   - gen_movl_reg_T0[dc->op1]();
  1840 + t_gen_mov_reg_TN(i, cpu_T[0]);
  1841 + tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
1882 1842 }
  1843 + /* writeback the updated pointer value. */
  1844 + if (dc->postinc)
  1845 + t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
1883 1846 return 2;
1884 1847 }
1885 1848  
... ... @@ -1893,22 +1856,20 @@ static unsigned int dec_movem_rm(DisasContext *dc)
1893 1856 cris_cc_mask(dc, 0);
1894 1857 for (i = 0; i <= dc->op2; i++) {
1895 1858 /* Fetch register i into T1. */
1896   - gen_movl_T0_reg[i]();
1897   - gen_op_movl_T1_T0();
1898   -
  1859 + t_gen_mov_TN_reg(cpu_T[1], i);
1899 1860 /* Fetch the address into T0. */
1900   - gen_movl_T0_reg[dc->op1]();
  1861 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1901 1862 /* Displace it. */
1902   - gen_op_addl_T0_im(i * 4);
1903   -
  1863 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
1904 1864 /* Perform the store. */
1905 1865 gen_store_T0_T1(dc, 4);
1906 1866 }
1907 1867 if (dc->postinc) {
1908   - /* Update the address. */
1909   - gen_op_addl_T0_im(4);
  1868 + /* T0 should point to the last written addr, advance one more
  1869 + step. */
  1870 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
1910 1871 /* writeback the updated pointer value. */
1911   - gen_movl_reg_T0[dc->op1]();
  1872 + t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1912 1873 }
1913 1874 return 2;
1914 1875 }
... ... @@ -1924,25 +1885,23 @@ static unsigned int dec_move_rm(DisasContext *dc)
1924 1885  
1925 1886 cris_cc_mask(dc, 0);
1926 1887 /* prepare store. */
1927   - gen_movl_T0_reg[dc->op2]();
1928   - gen_op_movl_T1_T0();
1929   - gen_movl_T0_reg[dc->op1]();
  1888 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
  1889 + t_gen_mov_TN_reg(cpu_T[1], dc->op2);
1930 1890 gen_store_T0_T1(dc, memsize);
1931 1891 if (dc->postinc)
1932 1892 {
1933   - gen_op_addl_T0_im(memsize);
1934   - gen_movl_reg_T0[dc->op1]();
  1893 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
  1894 + t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1935 1895 }
1936 1896 return 2;
1937 1897 }
1938 1898  
1939   -
1940 1899 static unsigned int dec_lapcq(DisasContext *dc)
1941 1900 {
1942 1901 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
1943 1902 dc->pc + dc->op1*2, dc->op2));
1944 1903 cris_cc_mask(dc, 0);
1945   - gen_op_movl_T1_im(dc->pc + dc->op1*2);
  1904 + tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
1946 1905 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1947 1906 return 2;
1948 1907 }
... ... @@ -1951,16 +1910,14 @@ static unsigned int dec_lapc_im(DisasContext *dc)
1951 1910 {
1952 1911 unsigned int rd;
1953 1912 int32_t imm;
1954   - int insn_len = 6;
1955 1913  
1956 1914 rd = dc->op2;
1957 1915  
1958 1916 cris_cc_mask(dc, 0);
1959 1917 imm = ldl_code(dc->pc + 2);
1960 1918 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
1961   - gen_op_movl_T0_im (dc->pc + imm);
1962   - gen_movl_reg_T0[rd] ();
1963   - return insn_len;
  1919 + t_gen_mov_reg_TN(rd, tcg_const_i32(dc->pc + imm));
  1920 + return 6;
1964 1921 }
1965 1922  
1966 1923 /* Jump to special reg. */
... ... @@ -1969,7 +1926,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
1969 1926 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
1970 1927 cris_cc_mask(dc, 0);
1971 1928 /* Store the return address in Pd. */
1972   - gen_movl_T0_preg[dc->op2]();
  1929 + t_gen_mov_TN_preg(cpu_T[0], dc->op2);
1973 1930 gen_op_movl_btarget_T0();
1974 1931 cris_prepare_dyn_jmp(dc);
1975 1932 return 2;
... ... @@ -1981,10 +1938,10 @@ static unsigned int dec_jas_r(DisasContext *dc)
1981 1938 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
1982 1939 cris_cc_mask(dc, 0);
1983 1940 /* Stor the return address in Pd. */
1984   - gen_movl_T0_reg[dc->op1]();
  1941 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1985 1942 gen_op_movl_btarget_T0();
1986   - gen_op_movl_T0_im(dc->pc + 4);
1987   - gen_movl_preg_T0[dc->op2]();
  1943 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
  1944 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1988 1945 cris_prepare_dyn_jmp(dc);
1989 1946 return 2;
1990 1947 }
... ... @@ -1998,10 +1955,10 @@ static unsigned int dec_jas_im(DisasContext *dc)
1998 1955 DIS(fprintf (logfile, "jas 0x%x\n", imm));
1999 1956 cris_cc_mask(dc, 0);
2000 1957 /* Stor the return address in Pd. */
2001   - gen_op_movl_T0_im(imm);
  1958 + tcg_gen_movi_tl(cpu_T[0], imm);
2002 1959 gen_op_movl_btarget_T0();
2003   - gen_op_movl_T0_im(dc->pc + 8);
2004   - gen_movl_preg_T0[dc->op2]();
  1960 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
  1961 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2005 1962 cris_prepare_dyn_jmp(dc);
2006 1963 return 6;
2007 1964 }
... ... @@ -2015,10 +1972,10 @@ static unsigned int dec_jasc_im(DisasContext *dc)
2015 1972 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2016 1973 cris_cc_mask(dc, 0);
2017 1974 /* Stor the return address in Pd. */
2018   - gen_op_movl_T0_im(imm);
  1975 + tcg_gen_movi_tl(cpu_T[0], imm);
2019 1976 gen_op_movl_btarget_T0();
2020   - gen_op_movl_T0_im(dc->pc + 8 + 4);
2021   - gen_movl_preg_T0[dc->op2]();
  1977 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
  1978 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2022 1979 cris_prepare_dyn_jmp(dc);
2023 1980 return 6;
2024 1981 }
... ... @@ -2028,10 +1985,10 @@ static unsigned int dec_jasc_r(DisasContext *dc)
2028 1985 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2029 1986 cris_cc_mask(dc, 0);
2030 1987 /* Stor the return address in Pd. */
2031   - gen_movl_T0_reg[dc->op1]();
  1988 + t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2032 1989 gen_op_movl_btarget_T0();
2033   - gen_op_movl_T0_im(dc->pc + 4 + 4);
2034   - gen_movl_preg_T0[dc->op2]();
  1990 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
  1991 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2035 1992 cris_prepare_dyn_jmp(dc);
2036 1993 return 2;
2037 1994 }
... ... @@ -2064,10 +2021,10 @@ static unsigned int dec_bas_im(DisasContext *dc)
2064 2021 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2065 2022 cris_cc_mask(dc, 0);
2066 2023 /* Stor the return address in Pd. */
2067   - gen_op_movl_T0_im(dc->pc + simm);
  2024 + tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2068 2025 gen_op_movl_btarget_T0();
2069   - gen_op_movl_T0_im(dc->pc + 8);
2070   - gen_movl_preg_T0[dc->op2]();
  2026 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
  2027 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2071 2028 cris_prepare_dyn_jmp(dc);
2072 2029 return 6;
2073 2030 }
... ... @@ -2080,10 +2037,10 @@ static unsigned int dec_basc_im(DisasContext *dc)
2080 2037 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2081 2038 cris_cc_mask(dc, 0);
2082 2039 /* Stor the return address in Pd. */
2083   - gen_op_movl_T0_im(dc->pc + simm);
  2040 + tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2084 2041 gen_op_movl_btarget_T0();
2085   - gen_op_movl_T0_im(dc->pc + 12);
2086   - gen_movl_preg_T0[dc->op2]();
  2042 + tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
  2043 + t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2087 2044 cris_prepare_dyn_jmp(dc);
2088 2045 return 6;
2089 2046 }
... ... @@ -2096,7 +2053,7 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
2096 2053 cris_cc_mask(dc, 0);
2097 2054  
2098 2055 if (dc->op2 == 15) /* ignore halt. */
2099   - goto done;
  2056 + return 2;
2100 2057  
2101 2058 switch (dc->op2 & 7) {
2102 2059 case 2:
... ... @@ -2110,7 +2067,7 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
2110 2067 break;
2111 2068 case 6:
2112 2069 /* break. */
2113   - gen_op_movl_T0_im(dc->pc);
  2070 + tcg_gen_movi_tl(cpu_T[0], dc->pc);
2114 2071 gen_op_movl_pc_T0();
2115 2072 /* Breaks start at 16 in the exception vector. */
2116 2073 gen_op_break_im(dc->op1 + 16);
... ... @@ -2122,7 +2079,6 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
2122 2079 break;
2123 2080  
2124 2081 }
2125   - done:
2126 2082 return 2;
2127 2083 }
2128 2084  
... ... @@ -2296,7 +2252,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
2296 2252 for(j = 0; j < env->nb_breakpoints; j++) {
2297 2253 if (env->breakpoints[j] == dc->pc) {
2298 2254 cris_evaluate_flags (dc);
2299   - gen_op_movl_T0_im((long)dc->pc);
  2255 + tcg_gen_movi_tl(cpu_T[0], dc->pc);
2300 2256 gen_op_movl_pc_T0();
2301 2257 gen_op_debug();
2302 2258 dc->is_jmp = DISAS_UPDATE;
... ... @@ -2305,7 +2261,6 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
2305 2261 }
2306 2262 }
2307 2263  
2308   -
2309 2264 /* generate intermediate code for basic block 'tb'. */
2310 2265 struct DisasContext ctx;
2311 2266 static int
... ... @@ -2356,11 +2311,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2356 2311 if (!dc->flagx_live
2357 2312 || (dc->flagx_live &&
2358 2313 !(dc->cc_op == CC_OP_FLAGS && dc->flags_x))) {
2359   - gen_movl_T0_preg[PR_CCS]();
2360   - gen_op_andl_T0_im(~X_FLAG);
2361   - gen_movl_preg_T0[PR_CCS]();
2362   - dc->flagx_live = 1;
2363   - dc->flags_x = 0;
  2314 + cris_clear_x_flag(dc);
2364 2315 }
2365 2316  
2366 2317 /* Check for delayed branches here. If we do it before
... ... @@ -2488,6 +2439,10 @@ void cpu_dump_state (CPUState *env, FILE *f,
2488 2439  
2489 2440 }
2490 2441  
  2442 +static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
  2443 +{
  2444 +}
  2445 +
2491 2446 CPUCRISState *cpu_cris_init (const char *cpu_model)
2492 2447 {
2493 2448 CPUCRISState *env;
... ... @@ -2496,6 +2451,19 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
2496 2451 if (!env)
2497 2452 return NULL;
2498 2453 cpu_exec_init(env);
  2454 +
  2455 + tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
  2456 + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  2457 +#if TARGET_LONG_BITS > HOST_LONG_BITS
  2458 + cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
  2459 + TCG_AREG0, offsetof(CPUState, t0), "T0");
  2460 + cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
  2461 + TCG_AREG0, offsetof(CPUState, t1), "T1");
  2462 +#else
  2463 + cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
  2464 + cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
  2465 +#endif
  2466 +
2499 2467 cpu_reset(env);
2500 2468 return env;
2501 2469 }
... ...