gwj / at91sam9263 · Commits

Commit 05b4ff435717e6b8355f6cd73ea17f2d9eaa9a55

Authored by ths
1 parent 9566782b

Implement some more Gallileo registers. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2953 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 336 additions and 17 deletions
hw/gt64xxx.c
  View file @05b4ff4
... ... @@ -23,9 +23,18 @@
23 23 */
24 24  
25 25 #include "vl.h"
  26 +
26 27 typedef target_phys_addr_t pci_addr_t;
27 28 #include "pci_host.h"
28 29  
  30 +//#define DEBUG
  31 +
  32 +#ifdef DEBUG
  33 +#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  34 +#else
  35 +#define dprintf(fmt, ...)
  36 +#endif
  37 +
29 38 #define GT_REGS (0x1000 >> 2)
30 39  
31 40 /* CPU Configuration */
... ... @@ -45,8 +54,6 @@ typedef target_phys_addr_t pci_addr_t;
45 54 #define GT_PCI0IOHD (0x050 >> 2)
46 55 #define GT_PCI0M0LD (0x058 >> 2)
47 56 #define GT_PCI0M0HD (0x060 >> 2)
48   -#define GT_ISD (0x068 >> 2)
49   -
50 57 #define GT_PCI0M1LD (0x080 >> 2)
51 58 #define GT_PCI0M1HD (0x088 >> 2)
52 59 #define GT_PCI1IOLD (0x090 >> 2)
... ... @@ -55,8 +62,7 @@ typedef target_phys_addr_t pci_addr_t;
55 62 #define GT_PCI1M0HD (0x0a8 >> 2)
56 63 #define GT_PCI1M1LD (0x0b0 >> 2)
57 64 #define GT_PCI1M1HD (0x0b8 >> 2)
58   -#define GT_PCI1M1LD (0x0b0 >> 2)
59   -#define GT_PCI1M1HD (0x0b8 >> 2)
  65 +#define GT_ISD (0x068 >> 2)
60 66  
61 67 #define GT_SCS10AR (0x0d0 >> 2)
62 68 #define GT_SCS32AR (0x0d8 >> 2)
... ... @@ -330,6 +336,45 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
330 336 /* Read-only registers, do nothing */
331 337 break;
332 338  
  339 + /* SDRAM and Device Address Decode */
  340 + case GT_SCS0LD:
  341 + case GT_SCS0HD:
  342 + case GT_SCS1LD:
  343 + case GT_SCS1HD:
  344 + case GT_SCS2LD:
  345 + case GT_SCS2HD:
  346 + case GT_SCS3LD:
  347 + case GT_SCS3HD:
  348 + case GT_CS0LD:
  349 + case GT_CS0HD:
  350 + case GT_CS1LD:
  351 + case GT_CS1HD:
  352 + case GT_CS2LD:
  353 + case GT_CS2HD:
  354 + case GT_CS3LD:
  355 + case GT_CS3HD:
  356 + case GT_BOOTLD:
  357 + case GT_BOOTHD:
  358 + case GT_ADERR:
  359 + /* SDRAM Configuration */
  360 + case GT_SDRAM_CFG:
  361 + case GT_SDRAM_OPMODE:
  362 + case GT_SDRAM_BM:
  363 + case GT_SDRAM_ADDRDECODE:
  364 + /* Accept and ignore SDRAM interleave configuration */
  365 + s->regs[saddr] = val;
  366 + break;
  367 +
  368 + /* Device Parameters */
  369 + case GT_DEV_B0:
  370 + case GT_DEV_B1:
  371 + case GT_DEV_B2:
  372 + case GT_DEV_B3:
  373 + case GT_DEV_BOOT:
  374 + /* Not implemented */
  375 + dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
  376 + break;
  377 +
333 378 /* ECC */
334 379 case GT_ECC_ERRDATALO:
335 380 case GT_ECC_ERRDATAHI:
... ... @@ -339,16 +384,131 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
339 384 /* Read-only registers, do nothing */
340 385 break;
341 386  
  387 + /* DMA Record */
  388 + case GT_DMA0_CNT:
  389 + case GT_DMA1_CNT:
  390 + case GT_DMA2_CNT:
  391 + case GT_DMA3_CNT:
  392 + case GT_DMA0_SA:
  393 + case GT_DMA1_SA:
  394 + case GT_DMA2_SA:
  395 + case GT_DMA3_SA:
  396 + case GT_DMA0_DA:
  397 + case GT_DMA1_DA:
  398 + case GT_DMA2_DA:
  399 + case GT_DMA3_DA:
  400 + case GT_DMA0_NEXT:
  401 + case GT_DMA1_NEXT:
  402 + case GT_DMA2_NEXT:
  403 + case GT_DMA3_NEXT:
  404 + case GT_DMA0_CUR:
  405 + case GT_DMA1_CUR:
  406 + case GT_DMA2_CUR:
  407 + case GT_DMA3_CUR:
  408 + /* Not implemented */
  409 + dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  410 + break;
  411 +
  412 + /* DMA Channel Control */
  413 + case GT_DMA0_CTRL:
  414 + case GT_DMA1_CTRL:
  415 + case GT_DMA2_CTRL:
  416 + case GT_DMA3_CTRL:
  417 + /* Not implemented */
  418 + dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  419 + break;
  420 +
  421 + /* DMA Arbiter */
  422 + case GT_DMA_ARB:
  423 + /* Not implemented */
  424 + dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
  425 + break;
  426 +
  427 + /* Timer/Counter */
  428 + case GT_TC0:
  429 + case GT_TC1:
  430 + case GT_TC2:
  431 + case GT_TC3:
  432 + case GT_TC_CONTROL:
  433 + /* Not implemented */
  434 + dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
  435 + break;
  436 +
342 437 /* PCI Internal */
343 438 case GT_PCI0_CMD:
344 439 case GT_PCI1_CMD:
345 440 s->regs[saddr] = val & 0x0401fc0f;
346 441 break;
  442 + case GT_PCI0_TOR:
  443 + case GT_PCI0_BS_SCS10:
  444 + case GT_PCI0_BS_SCS32:
  445 + case GT_PCI0_BS_CS20:
  446 + case GT_PCI0_BS_CS3BT:
  447 + case GT_PCI1_IACK:
  448 + case GT_PCI0_IACK:
  449 + case GT_PCI0_BARE:
  450 + case GT_PCI0_PREFMBR:
  451 + case GT_PCI0_SCS10_BAR:
  452 + case GT_PCI0_SCS32_BAR:
  453 + case GT_PCI0_CS20_BAR:
  454 + case GT_PCI0_CS3BT_BAR:
  455 + case GT_PCI0_SSCS10_BAR:
  456 + case GT_PCI0_SSCS32_BAR:
  457 + case GT_PCI0_SCS3BT_BAR:
  458 + case GT_PCI1_TOR:
  459 + case GT_PCI1_BS_SCS10:
  460 + case GT_PCI1_BS_SCS32:
  461 + case GT_PCI1_BS_CS20:
  462 + case GT_PCI1_BS_CS3BT:
  463 + case GT_PCI1_BARE:
  464 + case GT_PCI1_PREFMBR:
  465 + case GT_PCI1_SCS10_BAR:
  466 + case GT_PCI1_SCS32_BAR:
  467 + case GT_PCI1_CS20_BAR:
  468 + case GT_PCI1_CS3BT_BAR:
  469 + case GT_PCI1_SSCS10_BAR:
  470 + case GT_PCI1_SSCS32_BAR:
  471 + case GT_PCI1_SCS3BT_BAR:
  472 + case GT_PCI1_CFGADDR:
  473 + case GT_PCI1_CFGDATA:
  474 + /* not implemented */
  475 + break;
347 476 case GT_PCI0_CFGADDR:
348 477 s->pci->config_reg = val & 0x80fffffc;
349 478 break;
350 479 case GT_PCI0_CFGDATA:
351   - pci_host_data_writel(s->pci, 0, val);
  480 + if (s->pci->config_reg & (1u << 31))
  481 + pci_host_data_writel(s->pci, 0, val);
  482 + break;
  483 +
  484 + /* Interrupts */
  485 + case GT_INTRCAUSE:
  486 + /* not really implemented */
  487 + s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
  488 + s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
  489 + dprintf("INTRCAUSE %x\n", val);
  490 + break;
  491 + case GT_INTRMASK:
  492 + s->regs[saddr] = val & 0x3c3ffffe;
  493 + dprintf("INTRMASK %x\n", val);
  494 + break;
  495 + case GT_PCI0_ICMASK:
  496 + s->regs[saddr] = val & 0x03fffffe;
  497 + dprintf("ICMASK %x\n", val);
  498 + break;
  499 + case GT_PCI0_SERR0MASK:
  500 + s->regs[saddr] = val & 0x0000003f;
  501 + dprintf("SERR0MASK %x\n", val);
  502 + break;
  503 +
  504 + /* Reserved when only PCI_0 is configured. */
  505 + case GT_HINTRCAUSE:
  506 + case GT_CPU_INTSEL:
  507 + case GT_PCI0_INTSEL:
  508 + case GT_HINTRMASK:
  509 + case GT_PCI0_HICMASK:
  510 + case GT_PCI1_SERR1MASK:
  511 + /* not implemented */
352 512 break;
353 513  
354 514 /* SDRAM Parameters */
... ... @@ -362,9 +522,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
362 522 break;
363 523  
364 524 default:
365   -#if 0
366   - printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
367   -#endif
  525 + dprintf ("Bad register offset 0x%x\n", (int)addr);
368 526 break;
369 527 }
370 528 }
... ... @@ -420,6 +578,18 @@ static uint32_t gt64120_readl (void *opaque,
420 578 break;
421 579  
422 580 case GT_CPU:
  581 + case GT_SCS10LD:
  582 + case GT_SCS10HD:
  583 + case GT_SCS32LD:
  584 + case GT_SCS32HD:
  585 + case GT_CS20LD:
  586 + case GT_CS20HD:
  587 + case GT_CS3BOOTLD:
  588 + case GT_CS3BOOTHD:
  589 + case GT_SCS10AR:
  590 + case GT_SCS32AR:
  591 + case GT_CS20R:
  592 + case GT_CS3BOOTR:
423 593 case GT_PCI0IOLD:
424 594 case GT_PCI0M0LD:
425 595 case GT_PCI0M1LD:
... ... @@ -432,14 +602,13 @@ static uint32_t gt64120_readl (void *opaque,
432 602 case GT_PCI1IOHD:
433 603 case GT_PCI1M0HD:
434 604 case GT_PCI1M1HD:
435   - case GT_PCI0_CMD:
436   - case GT_PCI1_CMD:
437 605 case GT_PCI0IOREMAP:
438 606 case GT_PCI0M0REMAP:
439 607 case GT_PCI0M1REMAP:
440 608 case GT_PCI1IOREMAP:
441 609 case GT_PCI1M0REMAP:
442 610 case GT_PCI1M1REMAP:
  611 + case GT_ISD:
443 612 val = s->regs[saddr];
444 613 break;
445 614 case GT_PCI0_IACK:
... ... @@ -447,6 +616,37 @@ static uint32_t gt64120_readl (void *opaque,
447 616 val = pic_read_irq(isa_pic);
448 617 break;
449 618  
  619 + /* SDRAM and Device Address Decode */
  620 + case GT_SCS0LD:
  621 + case GT_SCS0HD:
  622 + case GT_SCS1LD:
  623 + case GT_SCS1HD:
  624 + case GT_SCS2LD:
  625 + case GT_SCS2HD:
  626 + case GT_SCS3LD:
  627 + case GT_SCS3HD:
  628 + case GT_CS0LD:
  629 + case GT_CS0HD:
  630 + case GT_CS1LD:
  631 + case GT_CS1HD:
  632 + case GT_CS2LD:
  633 + case GT_CS2HD:
  634 + case GT_CS3LD:
  635 + case GT_CS3HD:
  636 + case GT_BOOTLD:
  637 + case GT_BOOTHD:
  638 + case GT_ADERR:
  639 + val = s->regs[saddr];
  640 + break;
  641 +
  642 + /* SDRAM Configuration */
  643 + case GT_SDRAM_CFG:
  644 + case GT_SDRAM_OPMODE:
  645 + case GT_SDRAM_BM:
  646 + case GT_SDRAM_ADDRDECODE:
  647 + val = s->regs[saddr];
  648 + break;
  649 +
450 650 /* SDRAM Parameters */
451 651 case GT_SDRAM_B0:
452 652 case GT_SDRAM_B1:
... ... @@ -457,27 +657,146 @@ static uint32_t gt64120_readl (void *opaque,
457 657 val = s->regs[saddr];
458 658 break;
459 659  
  660 + /* Device Parameters */
  661 + case GT_DEV_B0:
  662 + case GT_DEV_B1:
  663 + case GT_DEV_B2:
  664 + case GT_DEV_B3:
  665 + case GT_DEV_BOOT:
  666 + val = s->regs[saddr];
  667 + break;
  668 +
  669 + /* DMA Record */
  670 + case GT_DMA0_CNT:
  671 + case GT_DMA1_CNT:
  672 + case GT_DMA2_CNT:
  673 + case GT_DMA3_CNT:
  674 + case GT_DMA0_SA:
  675 + case GT_DMA1_SA:
  676 + case GT_DMA2_SA:
  677 + case GT_DMA3_SA:
  678 + case GT_DMA0_DA:
  679 + case GT_DMA1_DA:
  680 + case GT_DMA2_DA:
  681 + case GT_DMA3_DA:
  682 + case GT_DMA0_NEXT:
  683 + case GT_DMA1_NEXT:
  684 + case GT_DMA2_NEXT:
  685 + case GT_DMA3_NEXT:
  686 + case GT_DMA0_CUR:
  687 + case GT_DMA1_CUR:
  688 + case GT_DMA2_CUR:
  689 + case GT_DMA3_CUR:
  690 + val = s->regs[saddr];
  691 + break;
  692 +
  693 + /* DMA Channel Control */
  694 + case GT_DMA0_CTRL:
  695 + case GT_DMA1_CTRL:
  696 + case GT_DMA2_CTRL:
  697 + case GT_DMA3_CTRL:
  698 + val = s->regs[saddr];
  699 + break;
  700 +
  701 + /* DMA Arbiter */
  702 + case GT_DMA_ARB:
  703 + val = s->regs[saddr];
  704 + break;
  705 +
  706 + /* Timer/Counter */
  707 + case GT_TC0:
  708 + case GT_TC1:
  709 + case GT_TC2:
  710 + case GT_TC3:
  711 + case GT_TC_CONTROL:
  712 + val = s->regs[saddr];
  713 + break;
  714 +
460 715 /* PCI Internal */
461 716 case GT_PCI0_CFGADDR:
462 717 val = s->pci->config_reg;
463 718 break;
464 719 case GT_PCI0_CFGDATA:
465   - val = pci_host_data_readl(s->pci, 0);
  720 + if (!(s->pci->config_reg & (1u << 31)))
  721 + val = 0xffffffff;
  722 + else
  723 + val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
  724 + break;
  725 +
  726 + case GT_PCI0_CMD:
  727 + case GT_PCI0_TOR:
  728 + case GT_PCI0_BS_SCS10:
  729 + case GT_PCI0_BS_SCS32:
  730 + case GT_PCI0_BS_CS20:
  731 + case GT_PCI0_BS_CS3BT:
  732 + case GT_PCI1_IACK:
  733 + case GT_PCI0_BARE:
  734 + case GT_PCI0_PREFMBR:
  735 + case GT_PCI0_SCS10_BAR:
  736 + case GT_PCI0_SCS32_BAR:
  737 + case GT_PCI0_CS20_BAR:
  738 + case GT_PCI0_CS3BT_BAR:
  739 + case GT_PCI0_SSCS10_BAR:
  740 + case GT_PCI0_SSCS32_BAR:
  741 + case GT_PCI0_SCS3BT_BAR:
  742 + case GT_PCI1_CMD:
  743 + case GT_PCI1_TOR:
  744 + case GT_PCI1_BS_SCS10:
  745 + case GT_PCI1_BS_SCS32:
  746 + case GT_PCI1_BS_CS20:
  747 + case GT_PCI1_BS_CS3BT:
  748 + case GT_PCI1_BARE:
  749 + case GT_PCI1_PREFMBR:
  750 + case GT_PCI1_SCS10_BAR:
  751 + case GT_PCI1_SCS32_BAR:
  752 + case GT_PCI1_CS20_BAR:
  753 + case GT_PCI1_CS3BT_BAR:
  754 + case GT_PCI1_SSCS10_BAR:
  755 + case GT_PCI1_SSCS32_BAR:
  756 + case GT_PCI1_SCS3BT_BAR:
  757 + case GT_PCI1_CFGADDR:
  758 + case GT_PCI1_CFGDATA:
  759 + val = s->regs[saddr];
  760 + break;
  761 +
  762 + /* Interrupts */
  763 + case GT_INTRCAUSE:
  764 + val = s->regs[saddr];
  765 + dprintf("INTRCAUSE %x\n", val);
  766 + break;
  767 + case GT_INTRMASK:
  768 + val = s->regs[saddr];
  769 + dprintf("INTRMASK %x\n", val);
  770 + break;
  771 + case GT_PCI0_ICMASK:
  772 + val = s->regs[saddr];
  773 + dprintf("ICMASK %x\n", val);
  774 + break;
  775 + case GT_PCI0_SERR0MASK:
  776 + val = s->regs[saddr];
  777 + dprintf("SERR0MASK %x\n", val);
  778 + break;
  779 +
  780 + /* Reserved when only PCI_0 is configured. */
  781 + case GT_HINTRCAUSE:
  782 + case GT_CPU_INTSEL:
  783 + case GT_PCI0_INTSEL:
  784 + case GT_HINTRMASK:
  785 + case GT_PCI0_HICMASK:
  786 + case GT_PCI1_SERR1MASK:
  787 + val = s->regs[saddr];
466 788 break;
467 789  
468 790 default:
469 791 val = s->regs[saddr];
470   -#if 0
471   - printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
472   -#endif
  792 + dprintf ("Bad register offset 0x%x\n", (int)addr);
473 793 break;
474 794 }
475 795  
476 796 #ifdef TARGET_WORDS_BIGENDIAN
477   - return bswap32(val);
478   -#else
479   - return val;
  797 + val = bswap32(val);
480 798 #endif
  799 + return val;
481 800 }
482 801  
483 802 static CPUWriteMemoryFunc *gt64120_write[] = {
... ...