gwj / at91sam9263 · Commits

Commit 02f4f6c24c8adab07ecef71af173212b5718b39e

Authored by aurel32
1 parent 89b190a2

[ppc] Convert gen_set_{T0,T1} to TCG 

The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 9 additions and 29 deletions
target-ppc/translate.c
  View file @02f4f6c
@@ -80,26 +80,6 @@ static uint16_t *gen_fprf_buf[OPC_BUF_SIZE]; @@ -80,26 +80,6 @@ static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
80 static uint16_t **gen_fprf_ptr; 80 static uint16_t **gen_fprf_ptr;
81 #endif 81 #endif
82 82
83 -static always_inline void gen_set_T0 (target_ulong val)  
84 -{  
85 -#if defined(TARGET_PPC64)  
86 - if (val >> 32)  
87 - gen_op_set_T0_64(val >> 32, val);  
88 - else  
89 -#endif  
90 - gen_op_set_T0(val);  
91 -}  
92 -  
93 -static always_inline void gen_set_T1 (target_ulong val)  
94 -{  
95 -#if defined(TARGET_PPC64)  
96 - if (val >> 32)  
97 - gen_op_set_T1_64(val >> 32, val);  
98 - else  
99 -#endif  
100 - gen_op_set_T1(val);  
101 -}  
102 -  
103 #define GEN8(func, NAME) \ 83 #define GEN8(func, NAME) \
104 static GenOpFunc *NAME ## _table [8] = { \ 84 static GenOpFunc *NAME ## _table [8] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ 85 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
@@ -1004,7 +984,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1004,7 +984,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1004 984
1005 if (rA(ctx->opcode) == 0) { 985 if (rA(ctx->opcode) == 0) {
1006 /* li case */ 986 /* li case */
1007 - gen_set_T0(simm); 987 + tcg_gen_movi_tl(cpu_T[0], simm);
1008 } else { 988 } else {
1009 gen_op_load_gpr_T0(rA(ctx->opcode)); 989 gen_op_load_gpr_T0(rA(ctx->opcode));
1010 if (likely(simm != 0)) 990 if (likely(simm != 0))
@@ -1060,7 +1040,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1060,7 +1040,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1060 1040
1061 if (rA(ctx->opcode) == 0) { 1041 if (rA(ctx->opcode) == 0) {
1062 /* lis case */ 1042 /* lis case */
1063 - gen_set_T0(simm << 16); 1043 + tcg_gen_movi_tl(cpu_T[0], simm << 16);
1064 } else { 1044 } else {
1065 gen_op_load_gpr_T0(rA(ctx->opcode)); 1045 gen_op_load_gpr_T0(rA(ctx->opcode));
1066 if (likely(simm != 0)) 1046 if (likely(simm != 0))
@@ -1161,7 +1141,7 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) @@ -1161,7 +1141,7 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1161 uint32_t mask; 1141 uint32_t mask;
1162 1142
1163 if (rA(ctx->opcode) == 0) { 1143 if (rA(ctx->opcode) == 0) {
1164 - gen_set_T0(0); 1144 + tcg_gen_movi_tl(cpu_T[0], 0);
1165 } else { 1145 } else {
1166 gen_op_load_gpr_T1(rA(ctx->opcode)); 1146 gen_op_load_gpr_T1(rA(ctx->opcode));
1167 } 1147 }
@@ -2100,7 +2080,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, @@ -2100,7 +2080,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
2100 2080
2101 simm &= ~maskl; 2081 simm &= ~maskl;
2102 if (rA(ctx->opcode) == 0) { 2082 if (rA(ctx->opcode) == 0) {
2103 - gen_set_T0(simm); 2083 + tcg_gen_movi_tl(cpu_T[0], simm);
2104 } else { 2084 } else {
2105 gen_op_load_gpr_T0(rA(ctx->opcode)); 2085 gen_op_load_gpr_T0(rA(ctx->opcode));
2106 if (likely(simm != 0)) 2086 if (likely(simm != 0))
@@ -2823,7 +2803,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n, @@ -2823,7 +2803,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2823 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && 2803 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2824 likely(!ctx->singlestep_enabled)) { 2804 likely(!ctx->singlestep_enabled)) {
2825 tcg_gen_goto_tb(n); 2805 tcg_gen_goto_tb(n);
2826 - gen_set_T1(dest); 2806 + tcg_gen_movi_tl(cpu_T[1], dest);
2827 #if defined(TARGET_PPC64) 2807 #if defined(TARGET_PPC64)
2828 if (ctx->sf_mode) 2808 if (ctx->sf_mode)
2829 gen_op_b_T1_64(); 2809 gen_op_b_T1_64();
@@ -2832,7 +2812,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n, @@ -2832,7 +2812,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2832 gen_op_b_T1(); 2812 gen_op_b_T1();
2833 tcg_gen_exit_tb((long)tb + n); 2813 tcg_gen_exit_tb((long)tb + n);
2834 } else { 2814 } else {
2835 - gen_set_T1(dest); 2815 + tcg_gen_movi_tl(cpu_T[1], dest);
2836 #if defined(TARGET_PPC64) 2816 #if defined(TARGET_PPC64)
2837 if (ctx->sf_mode) 2817 if (ctx->sf_mode)
2838 gen_op_b_T1_64(); 2818 gen_op_b_T1_64();
@@ -3185,7 +3165,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) @@ -3185,7 +3165,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3185 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) 3165 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3186 { 3166 {
3187 gen_op_load_gpr_T0(rA(ctx->opcode)); 3167 gen_op_load_gpr_T0(rA(ctx->opcode));
3188 - gen_set_T1(SIMM(ctx->opcode)); 3168 + tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3189 /* Update the nip since this might generate a trap exception */ 3169 /* Update the nip since this might generate a trap exception */
3190 gen_update_nip(ctx, ctx->nip); 3170 gen_update_nip(ctx, ctx->nip);
3191 gen_op_tw(TO(ctx->opcode)); 3171 gen_op_tw(TO(ctx->opcode));
@@ -3206,7 +3186,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) @@ -3206,7 +3186,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3206 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) 3186 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3207 { 3187 {
3208 gen_op_load_gpr_T0(rA(ctx->opcode)); 3188 gen_op_load_gpr_T0(rA(ctx->opcode));
3209 - gen_set_T1(SIMM(ctx->opcode)); 3189 + tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3210 /* Update the nip since this might generate a trap exception */ 3190 /* Update the nip since this might generate a trap exception */
3211 gen_update_nip(ctx, ctx->nip); 3191 gen_update_nip(ctx, ctx->nip);
3212 gen_op_td(TO(ctx->opcode)); 3192 gen_op_td(TO(ctx->opcode));
@@ -5335,7 +5315,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) @@ -5335,7 +5315,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5335 target_long simm = rB(ctx->opcode); 5315 target_long simm = rB(ctx->opcode);
5336 5316
5337 if (rA(ctx->opcode) == 0) { 5317 if (rA(ctx->opcode) == 0) {
5338 - gen_set_T0(simm << sh); 5318 + tcg_gen_movi_tl(cpu_T[0], simm << sh);
5339 } else { 5319 } else {
5340 gen_op_load_gpr_T0(rA(ctx->opcode)); 5320 gen_op_load_gpr_T0(rA(ctx->opcode));
5341 if (likely(simm != 0)) 5321 if (likely(simm != 0))