gwj / at91sam9263 · Commits

Commit 02aab46a362acd041006776e322a85a7753e4c14

Authored by bellard
1 parent aab33094

endianness fix 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1588 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 54 additions and 26 deletions
target-sparc/op_helper.c
  View file @02aab46
... ... @@ -256,11 +256,18 @@ void helper_ld_asi(int asi, int size, int sign)
256 256 }
257 257 break;
258 258 case 0x20 ... 0x2f: /* MMU passthrough */
259   - cpu_physical_memory_read(T0, (void *) &ret, size);
260   - if (size == 4)
261   - tswap32s(&ret);
262   - else if (size == 2)
263   - tswap16s((uint16_t *)&ret);
  259 + switch(size) {
  260 + case 1:
  261 + ret = ldub_phys(T0);
  262 + break;
  263 + case 2:
  264 + ret = lduw_phys(T0 & ~1);
  265 + break;
  266 + default:
  267 + case 4:
  268 + ret = ldl_phys(T0 & ~3);
  269 + break;
  270 + }
264 271 break;
265 272 default:
266 273 ret = 0;
... ... @@ -369,12 +376,18 @@ void helper_st_asi(int asi, int size, int sign)
369 376 return;
370 377 case 0x20 ... 0x2f: /* MMU passthrough */
371 378 {
372   - uint32_t temp = T1;
373   - if (size == 4)
374   - tswap32s(&temp);
375   - else if (size == 2)
376   - tswap16s((uint16_t *)&temp);
377   - cpu_physical_memory_write(T0, (void *) &temp, size);
  379 + switch(size) {
  380 + case 1:
  381 + stb_phys(T0, T1);
  382 + break;
  383 + case 2:
  384 + stw_phys(T0 & ~1, T1);
  385 + break;
  386 + case 4:
  387 + default:
  388 + stl_phys(T0 & ~3, T1);
  389 + break;
  390 + }
378 391 }
379 392 return;
380 393 default:
... ... @@ -395,13 +408,21 @@ void helper_ld_asi(int asi, int size, int sign)
395 408 case 0x14: // Bypass
396 409 case 0x15: // Bypass, non-cacheable
397 410 {
398   - cpu_physical_memory_read(T0, (void *) &ret, size);
399   - if (size == 8)
400   - tswap64s(&ret);
401   - if (size == 4)
402   - tswap32s((uint32_t *)&ret);
403   - else if (size == 2)
404   - tswap16s((uint16_t *)&ret);
  411 + switch(size) {
  412 + case 1:
  413 + ret = ldub_phys(T0);
  414 + break;
  415 + case 2:
  416 + ret = lduw_phys(T0 & ~1);
  417 + break;
  418 + case 4:
  419 + ret = ldl_phys(T0 & ~3);
  420 + break;
  421 + default:
  422 + case 8:
  423 + ret = ldq_phys(T0 & ~7);
  424 + break;
  425 + }
405 426 break;
406 427 }
407 428 case 0x04: // Nucleus
... ... @@ -503,14 +524,21 @@ void helper_st_asi(int asi, int size, int sign)
503 524 case 0x14: // Bypass
504 525 case 0x15: // Bypass, non-cacheable
505 526 {
506   - target_ulong temp = T1;
507   - if (size == 8)
508   - tswap64s(&temp);
509   - else if (size == 4)
510   - tswap32s((uint32_t *)&temp);
511   - else if (size == 2)
512   - tswap16s((uint16_t *)&temp);
513   - cpu_physical_memory_write(T0, (void *) &temp, size);
  527 + switch(size) {
  528 + case 1:
  529 + stb_phys(T0, T1);
  530 + break;
  531 + case 2:
  532 + stw_phys(T0 & ~1, T1);
  533 + break;
  534 + case 4:
  535 + stl_phys(T0 & ~3, T1);
  536 + break;
  537 + case 8:
  538 + default:
  539 + stq_phys(T0 & ~7, T1);
  540 + break;
  541 + }
514 542 }
515 543 return;
516 544 case 0x04: // Nucleus
... ...