gwj / at91sam9263 · Commits

Commit 023d8ca21fab3cb29be506946476ffc16c479a17

Authored by aurel32
1 parent 5dafc53f

target-alpha: factorize load/store code 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5353 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 65 additions and 134 deletions
target-alpha/translate.c
  View file @023d8ca
@@ -256,7 +256,7 @@ static always_inline void gen_invalid (DisasContext *ctx) @@ -256,7 +256,7 @@ static always_inline void gen_invalid (DisasContext *ctx)
256 gen_excp(ctx, EXCP_OPCDEC, 0); 256 gen_excp(ctx, EXCP_OPCDEC, 0);
257 } 257 }
258 258
259 -static always_inline void gen_load_mem (DisasContext *ctx, 259 +static always_inline void gen_load_mem_dyngen (DisasContext *ctx,
260 void (*gen_load_op)(DisasContext *ctx), 260 void (*gen_load_op)(DisasContext *ctx),
261 int ra, int rb, int32_t disp16, 261 int ra, int rb, int32_t disp16,
262 int clear) 262 int clear)
@@ -277,7 +277,31 @@ static always_inline void gen_load_mem (DisasContext *ctx, @@ -277,7 +277,31 @@ static always_inline void gen_load_mem (DisasContext *ctx,
277 } 277 }
278 } 278 }
279 279
280 -static always_inline void gen_store_mem (DisasContext *ctx, 280 +static always_inline void gen_load_mem (DisasContext *ctx,
  281 + void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
  282 + int ra, int rb, int32_t disp16,
  283 + int clear)
  284 +{
  285 + TCGv addr;
  286 +
  287 + if (unlikely(ra == 31))
  288 + return;
  289 +
  290 + addr = tcg_temp_new(TCG_TYPE_I64);
  291 + if (rb != 31) {
  292 + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
  293 + if (clear)
  294 + tcg_gen_andi_i64(addr, addr, ~0x7);
  295 + } else {
  296 + if (clear)
  297 + disp16 &= ~0x7;
  298 + tcg_gen_movi_i64(addr, disp16);
  299 + }
  300 + tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);
  301 + tcg_temp_free(addr);
  302 +}
  303 +
  304 +static always_inline void gen_store_mem_dyngen (DisasContext *ctx,
281 void (*gen_store_op)(DisasContext *ctx), 305 void (*gen_store_op)(DisasContext *ctx),
282 int ra, int rb, int32_t disp16, 306 int ra, int rb, int32_t disp16,
283 int clear) 307 int clear)
@@ -295,6 +319,31 @@ static always_inline void gen_store_mem (DisasContext *ctx, @@ -295,6 +319,31 @@ static always_inline void gen_store_mem (DisasContext *ctx,
295 (*gen_store_op)(ctx); 319 (*gen_store_op)(ctx);
296 } 320 }
297 321
  322 +static always_inline void gen_store_mem (DisasContext *ctx,
  323 + void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
  324 + int ra, int rb, int32_t disp16,
  325 + int clear)
  326 +{
  327 + TCGv addr = tcg_temp_new(TCG_TYPE_I64);
  328 + if (rb != 31) {
  329 + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
  330 + if (clear)
  331 + tcg_gen_andi_i64(addr, addr, ~0x7);
  332 + } else {
  333 + if (clear)
  334 + disp16 &= ~0x7;
  335 + tcg_gen_movi_i64(addr, disp16);
  336 + }
  337 + if (ra != 31)
  338 + tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
  339 + else {
  340 + TCGv zero = tcg_const_i64(0);
  341 + tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
  342 + tcg_temp_free(zero);
  343 + }
  344 + tcg_temp_free(addr);
  345 +}
  346 +
298 static always_inline void gen_load_fmem (DisasContext *ctx, 347 static always_inline void gen_load_fmem (DisasContext *ctx,
299 void (*gen_load_fop)(DisasContext *ctx), 348 void (*gen_load_fop)(DisasContext *ctx),
300 int ra, int rb, int32_t disp16) 349 int ra, int rb, int32_t disp16)
@@ -655,103 +704,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) @@ -655,103 +704,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
655 /* LDBU */ 704 /* LDBU */
656 if (!(ctx->amask & AMASK_BWX)) 705 if (!(ctx->amask & AMASK_BWX))
657 goto invalid_opc; 706 goto invalid_opc;
658 - if (likely(ra != 31)) {  
659 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
660 - if (rb != 31)  
661 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
662 - else  
663 - tcg_gen_movi_i64(addr, disp16);  
664 - tcg_gen_qemu_ld8u(cpu_ir[ra], addr, ctx->mem_idx);  
665 - tcg_temp_free(addr);  
666 - } 707 + gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0);
667 break; 708 break;
668 case 0x0B: 709 case 0x0B:
669 /* LDQ_U */ 710 /* LDQ_U */
670 - if (likely(ra != 31)) {  
671 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
672 - if (rb != 31) {  
673 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
674 - tcg_gen_andi_i64(addr, addr, ~0x7);  
675 - } else  
676 - tcg_gen_movi_i64(addr, disp16 & ~0x7);  
677 - tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx);  
678 - tcg_temp_free(addr);  
679 - } 711 + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1);
680 break; 712 break;
681 case 0x0C: 713 case 0x0C:
682 /* LDWU */ 714 /* LDWU */
683 if (!(ctx->amask & AMASK_BWX)) 715 if (!(ctx->amask & AMASK_BWX))
684 goto invalid_opc; 716 goto invalid_opc;
685 - if (likely(ra != 31)) {  
686 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
687 - if (rb != 31)  
688 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
689 - else  
690 - tcg_gen_movi_i64(addr, disp16);  
691 - tcg_gen_qemu_ld16u(cpu_ir[ra], addr, ctx->mem_idx);  
692 - tcg_temp_free(addr);  
693 - } 717 + gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 1);
694 break; 718 break;
695 case 0x0D: 719 case 0x0D:
696 /* STW */ 720 /* STW */
697 - {  
698 - TCGv addr;  
699 - if (!(ctx->amask & AMASK_BWX))  
700 - goto invalid_opc;  
701 - addr = tcg_temp_new(TCG_TYPE_I64);  
702 - if (rb != 31)  
703 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
704 - else  
705 - tcg_gen_movi_i64(addr, disp16);  
706 - if (ra != 31)  
707 - tcg_gen_qemu_st16(cpu_ir[ra], addr, ctx->mem_idx);  
708 - else {  
709 - TCGv zero = tcg_const_i64(0);  
710 - tcg_gen_qemu_st16(zero, addr, ctx->mem_idx);  
711 - tcg_temp_free(zero);  
712 - }  
713 - tcg_temp_free(addr);  
714 - } 721 + gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0);
715 break; 722 break;
716 case 0x0E: 723 case 0x0E:
717 /* STB */ 724 /* STB */
718 - {  
719 - TCGv addr;  
720 - if (!(ctx->amask & AMASK_BWX))  
721 - goto invalid_opc;  
722 - addr = tcg_temp_new(TCG_TYPE_I64);  
723 - if (rb != 31)  
724 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
725 - else  
726 - tcg_gen_movi_i64(addr, disp16);  
727 - if (ra != 31)  
728 - tcg_gen_qemu_st8(cpu_ir[ra], addr, ctx->mem_idx);  
729 - else {  
730 - TCGv zero = tcg_const_i64(0);  
731 - tcg_gen_qemu_st8(zero, addr, ctx->mem_idx);  
732 - tcg_temp_free(zero);  
733 - }  
734 - tcg_temp_free(addr);  
735 - } 725 + gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0);
736 break; 726 break;
737 case 0x0F: 727 case 0x0F:
738 /* STQ_U */ 728 /* STQ_U */
739 - {  
740 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
741 - if (rb != 31) {  
742 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
743 - tcg_gen_andi_i64(addr, addr, ~0x7);  
744 - } else  
745 - tcg_gen_movi_i64(addr, disp16 & ~0x7);  
746 - if (ra != 31)  
747 - tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx);  
748 - else {  
749 - TCGv zero = tcg_const_i64(0);  
750 - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);  
751 - tcg_temp_free(zero);  
752 - }  
753 - tcg_temp_free(addr);  
754 - } 729 + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1);
755 break; 730 break;
756 case 0x10: 731 case 0x10:
757 switch (fn7) { 732 switch (fn7) {
@@ -2189,79 +2164,35 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) @@ -2189,79 +2164,35 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2189 break; 2164 break;
2190 case 0x28: 2165 case 0x28:
2191 /* LDL */ 2166 /* LDL */
2192 - if (likely(ra != 31)) {  
2193 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
2194 - if (rb != 31)  
2195 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
2196 - else  
2197 - tcg_gen_movi_i64(addr, disp16);  
2198 - tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->mem_idx);  
2199 - tcg_temp_free(addr);  
2200 - } 2167 + gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0);
2201 break; 2168 break;
2202 case 0x29: 2169 case 0x29:
2203 /* LDQ */ 2170 /* LDQ */
2204 - if (likely(ra != 31)) {  
2205 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
2206 - if (rb != 31)  
2207 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
2208 - else  
2209 - tcg_gen_movi_i64(addr, disp16);  
2210 - tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx);  
2211 - tcg_temp_free(addr);  
2212 - } 2171 + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0);
2213 break; 2172 break;
2214 case 0x2A: 2173 case 0x2A:
2215 /* LDL_L */ 2174 /* LDL_L */
2216 - gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0); 2175 + gen_load_mem_dyngen(ctx, &gen_ldl_l, ra, rb, disp16, 0);
2217 break; 2176 break;
2218 case 0x2B: 2177 case 0x2B:
2219 /* LDQ_L */ 2178 /* LDQ_L */
2220 - gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0); 2179 + gen_load_mem_dyngen(ctx, &gen_ldq_l, ra, rb, disp16, 0);
2221 break; 2180 break;
2222 case 0x2C: 2181 case 0x2C:
2223 /* STL */ 2182 /* STL */
2224 - {  
2225 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
2226 - if (rb != 31)  
2227 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
2228 - else  
2229 - tcg_gen_movi_i64(addr, disp16);  
2230 - if (ra != 31)  
2231 - tcg_gen_qemu_st32(cpu_ir[ra], addr, ctx->mem_idx);  
2232 - else {  
2233 - TCGv zero = tcg_const_i64(0);  
2234 - tcg_gen_qemu_st32(zero, addr, ctx->mem_idx);  
2235 - tcg_temp_free(zero);  
2236 - }  
2237 - tcg_temp_free(addr);  
2238 - } 2183 + gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0);
2239 break; 2184 break;
2240 case 0x2D: 2185 case 0x2D:
2241 /* STQ */ 2186 /* STQ */
2242 - {  
2243 - TCGv addr = tcg_temp_new(TCG_TYPE_I64);  
2244 - if (rb != 31)  
2245 - tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);  
2246 - else  
2247 - tcg_gen_movi_i64(addr, disp16);  
2248 - if (ra != 31)  
2249 - tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx);  
2250 - else {  
2251 - TCGv zero = tcg_const_i64(0);  
2252 - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);  
2253 - tcg_temp_free(zero);  
2254 - }  
2255 - tcg_temp_free(addr);  
2256 - } 2187 + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0);
2257 break; 2188 break;
2258 case 0x2E: 2189 case 0x2E:
2259 /* STL_C */ 2190 /* STL_C */
2260 - gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0); 2191 + gen_store_mem_dyngen(ctx, &gen_stl_c, ra, rb, disp16, 0);
2261 break; 2192 break;
2262 case 0x2F: 2193 case 0x2F:
2263 /* STQ_C */ 2194 /* STQ_C */
2264 - gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0); 2195 + gen_store_mem_dyngen(ctx, &gen_stq_c, ra, rb, disp16, 0);
2265 break; 2196 break;
2266 case 0x30: 2197 case 0x30:
2267 /* BR */ 2198 /* BR */