Commit 01ff9cc8fed03f0425d921ea8712614b6b8e692c

Authored by aurel32
1 parent adf3c8b6

target-alpha: convert cmp* instructions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha/op.c
... ... @@ -208,51 +208,6 @@ void OPPROTO op_umulh (void)
208 208 }
209 209  
210 210 /* Tests */
211   -void OPPROTO op_cmpult (void)
212   -{
213   - if (T0 < T1)
214   - T0 = 1;
215   - else
216   - T0 = 0;
217   - RETURN();
218   -}
219   -
220   -void OPPROTO op_cmpule (void)
221   -{
222   - if (T0 <= T1)
223   - T0 = 1;
224   - else
225   - T0 = 0;
226   - RETURN();
227   -}
228   -
229   -void OPPROTO op_cmpeq (void)
230   -{
231   - if (T0 == T1)
232   - T0 = 1;
233   - else
234   - T0 = 0;
235   - RETURN();
236   -}
237   -
238   -void OPPROTO op_cmplt (void)
239   -{
240   - if ((int64_t)T0 < (int64_t)T1)
241   - T0 = 1;
242   - else
243   - T0 = 0;
244   - RETURN();
245   -}
246   -
247   -void OPPROTO op_cmple (void)
248   -{
249   - if ((int64_t)T0 <= (int64_t)T1)
250   - T0 = 1;
251   - else
252   - T0 = 0;
253   - RETURN();
254   -}
255   -
256 211 void OPPROTO op_cmpbge (void)
257 212 {
258 213 helper_cmpbge();
... ...
target-alpha/translate.c
... ... @@ -561,6 +561,38 @@ static always_inline void gen_byte_manipulation(void *helper,
561 561 tcg_gen_movi_i64(cpu_ir[rc], 0);
562 562 }
563 563  
  564 +static always_inline void gen_cmp(TCGCond cond,
  565 + int ra, int rb, int rc,
  566 + int islit, int8_t lit)
  567 +{
  568 + int l1, l2;
  569 + TCGv tmp;
  570 +
  571 + if (unlikely(rc == 31))
  572 + return;
  573 +
  574 + l1 = gen_new_label();
  575 + l2 = gen_new_label();
  576 +
  577 + if (ra != 31) {
  578 + tmp = tcg_temp_new(TCG_TYPE_I64);
  579 + tcg_gen_mov_i64(tmp, cpu_ir[ra]);
  580 + } else
  581 + tmp = tcg_const_i64(0);
  582 + if (islit)
  583 + tcg_gen_brcondi_i64(cond, tmp, lit, l1);
  584 + else if (rb != 31)
  585 + tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
  586 + else
  587 + tcg_gen_brcondi_i64(cond, tmp, 0, l1);
  588 +
  589 + tcg_gen_movi_i64(cpu_ir[rc], 0);
  590 + tcg_gen_br(l2);
  591 + gen_set_label(l1);
  592 + tcg_gen_movi_i64(cpu_ir[rc], 1);
  593 + gen_set_label(l2);
  594 +}
  595 +
564 596 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
565 597 {
566 598 uint32_t palcode;
... ... @@ -848,7 +880,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
848 880 break;
849 881 case 0x1D:
850 882 /* CMPULT */
851   - gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
  883 + gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
852 884 break;
853 885 case 0x20:
854 886 /* ADDQ */
... ... @@ -940,7 +972,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
940 972 break;
941 973 case 0x2D:
942 974 /* CMPEQ */
943   - gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
  975 + gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
944 976 break;
945 977 case 0x32:
946 978 /* S8ADDQ */
... ... @@ -992,7 +1024,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
992 1024 break;
993 1025 case 0x3D:
994 1026 /* CMPULE */
995   - gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
  1027 + gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
996 1028 break;
997 1029 case 0x40:
998 1030 /* ADDL/V */
... ... @@ -1004,7 +1036,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
1004 1036 break;
1005 1037 case 0x4D:
1006 1038 /* CMPLT */
1007   - gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
  1039 + gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
1008 1040 break;
1009 1041 case 0x60:
1010 1042 /* ADDQ/V */
... ... @@ -1016,7 +1048,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
1016 1048 break;
1017 1049 case 0x6D:
1018 1050 /* CMPLE */
1019   - gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
  1051 + gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
1020 1052 break;
1021 1053 default:
1022 1054 goto invalid_opc;
... ...