gwj / at91sam9263 · Commits

Commit 01d6a890b4dbfa63a6c2e23a768f0e6c9bee55e0

Authored by ths
1 parent 6a1cbf68

Sparc arm/mips/sparc register patch, by Martin Bochnig. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2377 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 39 additions and 0 deletions
target-arm/exec.h
  View file @01d6a89
... ... @@ -19,10 +19,17 @@
19 19 */
20 20 #include "dyngen-exec.h"
21 21  
  22 +#if defined(__sparc__)
  23 +struct CPUARMState *env;
  24 +uint32_t T0;
  25 +uint32_t T1;
  26 +uint32_t T2;
  27 +#else
22 28 register struct CPUARMState *env asm(AREG0);
23 29 register uint32_t T0 asm(AREG1);
24 30 register uint32_t T1 asm(AREG2);
25 31 register uint32_t T2 asm(AREG3);
  32 +#endif
26 33  
27 34 /* TODO: Put these in FP regs on targets that have such things. */
28 35 /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */
... ...
target-mips/exec.h
  View file @01d6a89
... ... @@ -7,7 +7,11 @@
7 7 #include "mips-defs.h"
8 8 #include "dyngen-exec.h"
9 9  
  10 +#if defined(__sparc__)
  11 +struct CPUMIPSState *env;
  12 +#else
10 13 register struct CPUMIPSState *env asm(AREG0);
  14 +#endif
11 15  
12 16 #if defined (USE_64BITS_REGS)
13 17 typedef int64_t host_int_t;
... ... @@ -17,6 +21,11 @@ typedef int32_t host_int_t;
17 21 typedef uint32_t host_uint_t;
18 22 #endif
19 23  
  24 +#if defined(__sparc__)
  25 +host_uint_t T0;
  26 +host_uint_t T1;
  27 +host_uint_t T2;
  28 +#else
20 29 #if TARGET_LONG_BITS > HOST_LONG_BITS
21 30 #define T0 (env->t0)
22 31 #define T1 (env->t1)
... ... @@ -26,6 +35,7 @@ register host_uint_t T0 asm(AREG1);
26 35 register host_uint_t T1 asm(AREG2);
27 36 register host_uint_t T2 asm(AREG3);
28 37 #endif
  38 +#endif
29 39  
30 40 #if defined (USE_HOST_FLOAT_REGS)
31 41 #error "implement me."
... ...
target-sparc/exec.h
  View file @01d6a89
... ... @@ -3,23 +3,41 @@
3 3 #include "dyngen-exec.h"
4 4 #include "config.h"
5 5  
  6 +#if defined(__sparc__)
  7 +struct CPUSPARCState *env;
  8 +#else
6 9 register struct CPUSPARCState *env asm(AREG0);
  10 +#endif
  11 +
7 12 #ifdef TARGET_SPARC64
8 13 #define T0 (env->t0)
9 14 #define T1 (env->t1)
10 15 #define T2 (env->t2)
11 16 #define REGWPTR env->regwptr
12 17 #else
  18 +#if defined(__sparc__)
  19 +register uint32_t T0 asm(AREG3);
  20 +register uint32_t T1 asm(AREG2);
  21 +#else
13 22 register uint32_t T0 asm(AREG1);
14 23 register uint32_t T1 asm(AREG2);
  24 +#endif
15 25  
16 26 #undef REG_REGWPTR // Broken
17 27 #ifdef REG_REGWPTR
  28 +#if defined(__sparc__)
  29 +register uint32_t *REGWPTR asm(AREG4);
  30 +#else
18 31 register uint32_t *REGWPTR asm(AREG3);
  32 +#endif
19 33 #define reg_REGWPTR
20 34  
21 35 #ifdef AREG4
  36 +#if defined(__sparc__)
  37 +register uint32_t T2 asm(AREG0);
  38 +#else
22 39 register uint32_t T2 asm(AREG4);
  40 +#endif
23 41 #define reg_T2
24 42 #else
25 43 #define T2 (env->t2)
... ... @@ -27,7 +45,11 @@ register uint32_t T2 asm(AREG4);
27 45  
28 46 #else
29 47 #define REGWPTR env->regwptr
  48 +#if defined(__sparc__)
  49 +register uint32_t T2 asm(AREG0);
  50 +#else
30 51 register uint32_t T2 asm(AREG3);
  52 +#endif
31 53 #define reg_T2
32 54 #endif
33 55 #endif
... ...