gwj / at91sam9263 · Commits

Commit 01a4afeb99ff8d6174e1fdd726cb95017f5a9b07

Authored by aurel32
1 parent 6a6ae23f

target-ppc: convert POWER2 load/store instructions to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 68 additions and 163 deletions
target-ppc/cpu.h
  View file @01a4afe
... ... @@ -561,9 +561,6 @@ struct CPUPPCState {
561 561 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
562 562  
563 563 /* Floating point execution context */
564   - /* temporary float registers */
565   - float64 ft0;
566   - float64 ft1;
567 564 float_status fp_status;
568 565 /* floating point registers */
569 566 float64 fpr[32];
... ...
target-ppc/exec.h
  View file @01a4afe
... ... @@ -45,9 +45,6 @@ register target_ulong T2 asm(AREG3);
45 45 #define TDX "%016lx"
46 46 #endif
47 47  
48   -#define FT0 (env->ft0)
49   -#define FT1 (env->ft1)
50   -
51 48 #if defined (DEBUG_OP)
52 49 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
53 50 #else
... ...
target-ppc/op_helper_mem.h
  View file @01a4afe
... ... @@ -309,48 +309,4 @@ void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
309 309 T0 = i;
310 310 }
311 311  
312   -/* XXX: TAGs are not managed */
313   -void glue(do_POWER2_lfq, MEMSUFFIX) (void)
314   -{
315   - FT0 = glue(ldfq, MEMSUFFIX)((uint32_t)T0);
316   - FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
317   -}
318   -
319   -static always_inline float64 glue(ldfqr, MEMSUFFIX) (target_ulong EA)
320   -{
321   - CPU_DoubleU u;
322   -
323   - u.d = glue(ldfq, MEMSUFFIX)(EA);
324   - u.ll = bswap64(u.ll);
325   -
326   - return u.d;
327   -}
328   -
329   -void glue(do_POWER2_lfq_le, MEMSUFFIX) (void)
330   -{
331   - FT0 = glue(ldfqr, MEMSUFFIX)((uint32_t)(T0 + 4));
332   - FT1 = glue(ldfqr, MEMSUFFIX)((uint32_t)T0);
333   -}
334   -
335   -void glue(do_POWER2_stfq, MEMSUFFIX) (void)
336   -{
337   - glue(stfq, MEMSUFFIX)((uint32_t)T0, FT0);
338   - glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
339   -}
340   -
341   -static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, float64 d)
342   -{
343   - CPU_DoubleU u;
344   -
345   - u.d = d;
346   - u.ll = bswap64(u.ll);
347   - glue(stfq, MEMSUFFIX)(EA, u.d);
348   -}
349   -
350   -void glue(do_POWER2_stfq_le, MEMSUFFIX) (void)
351   -{
352   - glue(stfqr, MEMSUFFIX)((uint32_t)(T0 + 4), FT0);
353   - glue(stfqr, MEMSUFFIX)((uint32_t)T0, FT1);
354   -}
355   -
356 312 #undef MEMSUFFIX
... ...
target-ppc/op_mem.h
  View file @01a4afe
... ... @@ -616,30 +616,4 @@ void OPPROTO glue(op_POWER_lscbx, MEMSUFFIX) (void)
616 616 RETURN();
617 617 }
618 618  
619   -/* POWER2 quad load and store */
620   -/* XXX: TAGs are not managed */
621   -void OPPROTO glue(op_POWER2_lfq, MEMSUFFIX) (void)
622   -{
623   - glue(do_POWER2_lfq, MEMSUFFIX)();
624   - RETURN();
625   -}
626   -
627   -void glue(op_POWER2_lfq_le, MEMSUFFIX) (void)
628   -{
629   - glue(do_POWER2_lfq_le, MEMSUFFIX)();
630   - RETURN();
631   -}
632   -
633   -void OPPROTO glue(op_POWER2_stfq, MEMSUFFIX) (void)
634   -{
635   - glue(do_POWER2_stfq, MEMSUFFIX)();
636   - RETURN();
637   -}
638   -
639   -void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
640   -{
641   - glue(do_POWER2_stfq_le, MEMSUFFIX)();
642   - RETURN();
643   -}
644   -
645 619 #undef MEMSUFFIX
... ...
target-ppc/translate.c
  View file @01a4afe
... ... @@ -71,7 +71,6 @@ static TCGv_i32 cpu_access_type;
71 71  
72 72 /* dyngen register indexes */
73 73 static TCGv cpu_T[3];
74   -static TCGv_i64 cpu_FT[2];
75 74  
76 75 #include "gen-icount.h"
77 76  
... ... @@ -103,11 +102,6 @@ void ppc_translate_init(void)
103 102 #endif
104 103 #endif
105 104  
106   - cpu_FT[0] = tcg_global_mem_new_i64(TCG_AREG0,
107   - offsetof(CPUState, ft0), "FT0");
108   - cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
109   - offsetof(CPUState, ft1), "FT1");
110   -
111 105 p = cpu_reg_names;
112 106  
113 107 for (i = 0; i < 8; i++) {
... ... @@ -5102,134 +5096,121 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5102 5096  
5103 5097 /* POWER2 specific instructions */
5104 5098 /* Quad manipulation (load/store two floats at a time) */
5105   -/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
5106   -#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5107   -#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
5108   -#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5109   -#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5110   -#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5111   -#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5112   -#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5113   -#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5114   -#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5115   -#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5116   -#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5117   -#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5118   -#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5119   -#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5120   -#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5121   -#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5122   -#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5123   -#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5124   -static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5125   - GEN_MEM_FUNCS(POWER2_lfq),
5126   -};
5127   -static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5128   - GEN_MEM_FUNCS(POWER2_stfq),
5129   -};
5130 5099  
5131 5100 /* lfq */
5132 5101 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5133 5102 {
5134   - /* NIP cannot be restored if the memory exception comes from an helper */
5135   - gen_update_nip(ctx, ctx->nip - 4);
5136   - gen_addr_imm_index(cpu_T[0], ctx, 0);
5137   - op_POWER2_lfq();
5138   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5139   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
  5103 + int rd = rD(ctx->opcode);
  5104 + TCGv t0 = tcg_temp_new();
  5105 + gen_addr_imm_index(t0, ctx, 0);
  5106 + gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
  5107 + tcg_gen_addi_tl(t0, t0, 8);
  5108 + gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
  5109 + tcg_temp_free(t0);
5140 5110 }
5141 5111  
5142 5112 /* lfqu */
5143 5113 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5144 5114 {
5145 5115 int ra = rA(ctx->opcode);
5146   -
5147   - /* NIP cannot be restored if the memory exception comes from an helper */
5148   - gen_update_nip(ctx, ctx->nip - 4);
5149   - gen_addr_imm_index(cpu_T[0], ctx, 0);
5150   - op_POWER2_lfq();
5151   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5152   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
  5116 + int rd = rD(ctx->opcode);
  5117 + TCGv t0 = tcg_temp_new();
  5118 + TCGv t1 = tcg_temp_new();
  5119 + gen_addr_imm_index(t0, ctx, 0);
  5120 + gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
  5121 + tcg_gen_addi_tl(t1, t0, 8);
  5122 + gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5153 5123 if (ra != 0)
5154   - tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
  5124 + tcg_gen_mov_tl(cpu_gpr[ra], t0);
  5125 + tcg_temp_free(t0);
  5126 + tcg_temp_free(t1);
5155 5127 }
5156 5128  
5157 5129 /* lfqux */
5158 5130 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5159 5131 {
5160 5132 int ra = rA(ctx->opcode);
5161   -
5162   - /* NIP cannot be restored if the memory exception comes from an helper */
5163   - gen_update_nip(ctx, ctx->nip - 4);
5164   - gen_addr_reg_index(cpu_T[0], ctx);
5165   - op_POWER2_lfq();
5166   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5167   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
  5133 + int rd = rD(ctx->opcode);
  5134 + TCGv t0 = tcg_temp_new();
  5135 + TCGv t1 = tcg_temp_new();
  5136 + gen_addr_reg_index(t0, ctx);
  5137 + gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
  5138 + tcg_gen_addi_tl(t1, t0, 8);
  5139 + gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5168 5140 if (ra != 0)
5169   - tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
  5141 + tcg_gen_mov_tl(cpu_gpr[ra], t0);
  5142 + tcg_temp_free(t0);
  5143 + tcg_temp_free(t1);
5170 5144 }
5171 5145  
5172 5146 /* lfqx */
5173 5147 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5174 5148 {
5175   - /* NIP cannot be restored if the memory exception comes from an helper */
5176   - gen_update_nip(ctx, ctx->nip - 4);
5177   - gen_addr_reg_index(cpu_T[0], ctx);
5178   - op_POWER2_lfq();
5179   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5180   - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
  5149 + int rd = rD(ctx->opcode);
  5150 + TCGv t0 = tcg_temp_new();
  5151 + gen_addr_reg_index(t0, ctx);
  5152 + gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
  5153 + tcg_gen_addi_tl(t0, t0, 8);
  5154 + gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
  5155 + tcg_temp_free(t0);
5181 5156 }
5182 5157  
5183 5158 /* stfq */
5184 5159 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5185 5160 {
5186   - /* NIP cannot be restored if the memory exception comes from an helper */
5187   - gen_update_nip(ctx, ctx->nip - 4);
5188   - gen_addr_imm_index(cpu_T[0], ctx, 0);
5189   - tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5190   - tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5191   - op_POWER2_stfq();
  5161 + int rd = rD(ctx->opcode);
  5162 + TCGv t0 = tcg_temp_new();
  5163 + gen_addr_imm_index(t0, ctx, 0);
  5164 + gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
  5165 + tcg_gen_addi_tl(t0, t0, 8);
  5166 + gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
  5167 + tcg_temp_free(t0);
5192 5168 }
5193 5169  
5194 5170 /* stfqu */
5195 5171 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5196 5172 {
5197 5173 int ra = rA(ctx->opcode);
5198   -
5199   - /* NIP cannot be restored if the memory exception comes from an helper */
5200   - gen_update_nip(ctx, ctx->nip - 4);
5201   - gen_addr_imm_index(cpu_T[0], ctx, 0);
5202   - tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5203   - tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5204   - op_POWER2_stfq();
  5174 + int rd = rD(ctx->opcode);
  5175 + TCGv t0 = tcg_temp_new();
  5176 + TCGv t1 = tcg_temp_new();
  5177 + gen_addr_imm_index(t0, ctx, 0);
  5178 + gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
  5179 + tcg_gen_addi_tl(t1, t0, 8);
  5180 + gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5205 5181 if (ra != 0)
5206   - tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
  5182 + tcg_gen_mov_tl(cpu_gpr[ra], t0);
  5183 + tcg_temp_free(t0);
  5184 + tcg_temp_free(t1);
5207 5185 }
5208 5186  
5209 5187 /* stfqux */
5210 5188 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5211 5189 {
5212 5190 int ra = rA(ctx->opcode);
5213   -
5214   - /* NIP cannot be restored if the memory exception comes from an helper */
5215   - gen_update_nip(ctx, ctx->nip - 4);
5216   - gen_addr_reg_index(cpu_T[0], ctx);
5217   - tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5218   - tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5219   - op_POWER2_stfq();
  5191 + int rd = rD(ctx->opcode);
  5192 + TCGv t0 = tcg_temp_new();
  5193 + TCGv t1 = tcg_temp_new();
  5194 + gen_addr_reg_index(t0, ctx);
  5195 + gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
  5196 + tcg_gen_addi_tl(t1, t0, 8);
  5197 + gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5220 5198 if (ra != 0)
5221   - tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
  5199 + tcg_gen_mov_tl(cpu_gpr[ra], t0);
  5200 + tcg_temp_free(t0);
  5201 + tcg_temp_free(t1);
5222 5202 }
5223 5203  
5224 5204 /* stfqx */
5225 5205 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5226 5206 {
5227   - /* NIP cannot be restored if the memory exception comes from an helper */
5228   - gen_update_nip(ctx, ctx->nip - 4);
5229   - gen_addr_reg_index(cpu_T[0], ctx);
5230   - tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5231   - tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5232   - op_POWER2_stfq();
  5207 + int rd = rD(ctx->opcode);
  5208 + TCGv t0 = tcg_temp_new();
  5209 + gen_addr_reg_index(t0, ctx);
  5210 + gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
  5211 + tcg_gen_addi_tl(t0, t0, 8);
  5212 + gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
  5213 + tcg_temp_free(t0);
5233 5214 }
5234 5215  
5235 5216 /* BookE specific instructions */
... ...