ths
authored
17 years ago
1
/*
2
3
* Arm PrimeCell PL110 Color LCD Controller
*
4
* Copyright ( c ) 2005 - 2006 CodeSourcery .
5
6
7
8
9
* Written by Paul Brook
*
* This code is licenced under the GNU LGPL
*/
10
11
12
# include "hw.h"
# include "primecell.h"
# include "console.h"
13
14
# define PL110_CR_EN 0x001
15
# define PL110_CR_BGR 0x100
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
# define PL110_CR_BEBO 0x200
# define PL110_CR_BEPO 0x400
# define PL110_CR_PWR 0x800
enum pl110_bppmode
{
BPP_1 ,
BPP_2 ,
BPP_4 ,
BPP_8 ,
BPP_16 ,
BPP_32
};
typedef struct {
uint32_t base ;
DisplayState * ds ;
33
34
/* The Versatile/PB uses a slightly modified PL110 controller. */
int versatile ;
35
36
37
38
39
40
41
42
43
44
45
46
uint32_t timing [ 4 ];
uint32_t cr ;
uint32_t upbase ;
uint32_t lpbase ;
uint32_t int_status ;
uint32_t int_mask ;
int cols ;
int rows ;
enum pl110_bppmode bpp ;
int invalidate ;
uint32_t pallette [ 256 ];
uint32_t raw_pallette [ 128 ];
47
qemu_irq irq ;
48
49
50
51
52
} pl110_state ;
static const unsigned char pl110_id [] =
{ 0x10 , 0x11 , 0x04 , 0x00 , 0x0d , 0xf0 , 0x05 , 0xb1 };
53
54
55
56
57
58
59
60
61
/* The Arm documentation ( DDI0224C ) says the CLDC on the Versatile board
has a different ID . However Linux only looks for the normal ID . */
# if 0
static const unsigned char pl110_versatile_id [] =
{ 0x93 , 0x10 , 0x04 , 0x00 , 0x0d , 0xf0 , 0x05 , 0xb1 };
# else
# define pl110_versatile_id pl110_id
# endif
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
static inline uint32_t rgb_to_pixel8 ( unsigned int r , unsigned int g , unsigned b )
{
return (( r >> 5 ) << 5 ) | (( g >> 5 ) << 2 ) | ( b >> 6 );
}
static inline uint32_t rgb_to_pixel15 ( unsigned int r , unsigned int g , unsigned b )
{
return (( r >> 3 ) << 10 ) | (( g >> 3 ) << 5 ) | ( b >> 3 );
}
static inline uint32_t rgb_to_pixel16 ( unsigned int r , unsigned int g , unsigned b )
{
return (( r >> 3 ) << 11 ) | (( g >> 2 ) << 5 ) | ( b >> 3 );
}
static inline uint32_t rgb_to_pixel24 ( unsigned int r , unsigned int g , unsigned b )
{
return ( r << 16 ) | ( g << 8 ) | b ;
}
static inline uint32_t rgb_to_pixel32 ( unsigned int r , unsigned int g , unsigned b )
{
return ( r << 16 ) | ( g << 8 ) | b ;
}
typedef void ( * drawfn )( uint32_t * , uint8_t * , const uint8_t * , int );
# define BITS 8
# include "pl110_template.h"
# define BITS 15
# include "pl110_template.h"
# define BITS 16
# include "pl110_template.h"
# define BITS 24
# include "pl110_template.h"
# define BITS 32
# include "pl110_template.h"
static int pl110_enabled ( pl110_state * s )
{
return ( s -> cr & PL110_CR_EN ) && ( s -> cr & PL110_CR_PWR );
}
105
static void pl110_update_display ( void * opaque )
106
107
108
109
110
111
112
113
114
115
116
{
pl110_state * s = ( pl110_state * ) opaque ;
drawfn * fntable ;
drawfn fn ;
uint32_t * pallette ;
uint32_t addr ;
uint32_t base ;
int dest_width ;
int src_width ;
uint8_t * dest ;
uint8_t * src ;
117
int first , last = 0 ;
118
119
int dirty , new_dirty ;
int i ;
120
int bpp_offset ;
121
122
123
if ( ! pl110_enabled ( s ))
return ;
ths
authored
17 years ago
124
125
switch ( s -> ds -> depth ) {
126
127
case 0 :
return ;
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
case 8 :
fntable = pl110_draw_fn_8 ;
dest_width = 1 ;
break ;
case 15 :
fntable = pl110_draw_fn_15 ;
dest_width = 2 ;
break ;
case 16 :
fntable = pl110_draw_fn_16 ;
dest_width = 2 ;
break ;
case 24 :
fntable = pl110_draw_fn_24 ;
dest_width = 3 ;
break ;
case 32 :
fntable = pl110_draw_fn_32 ;
dest_width = 4 ;
break ;
default :
149
fprintf ( stderr , "pl110: Bad color depth \n " );
150
151
exit ( 1 );
}
152
153
154
155
156
if ( s -> cr & PL110_CR_BGR )
bpp_offset = 0 ;
else
bpp_offset = 18 ;
157
if ( s -> cr & PL110_CR_BEBO )
158
fn = fntable [ s -> bpp + 6 + bpp_offset ];
159
else if ( s -> cr & PL110_CR_BEPO )
160
fn = fntable [ s -> bpp + 12 + bpp_offset ];
161
else
162
fn = fntable [ s -> bpp + bpp_offset ];
ths
authored
17 years ago
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
src_width = s -> cols ;
switch ( s -> bpp ) {
case BPP_1 :
src_width >>= 3 ;
break ;
case BPP_2 :
src_width >>= 2 ;
break ;
case BPP_4 :
src_width >>= 1 ;
break ;
case BPP_8 :
break ;
case BPP_16 :
src_width <<= 1 ;
break ;
case BPP_32 :
src_width <<= 2 ;
break ;
}
dest_width *= s -> cols ;
pallette = s -> pallette ;
base = s -> upbase ;
/* HACK: Arm aliases physical memory at 0x80000000. */
if ( base > 0x80000000 )
base -= 0x80000000 ;
src = phys_ram_base + base ;
dest = s -> ds -> data ;
first = - 1 ;
addr = base ;
dirty = cpu_physical_memory_get_dirty ( addr , VGA_DIRTY_FLAG );
196
new_dirty = dirty ;
197
for ( i = 0 ; i < s -> rows ; i ++ ) {
198
if (( addr & ~ TARGET_PAGE_MASK ) + src_width >= TARGET_PAGE_SIZE ) {
199
uint32_t tmp ;
200
new_dirty = 0 ;
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
for ( tmp = 0 ; tmp < src_width ; tmp += TARGET_PAGE_SIZE ) {
new_dirty |= cpu_physical_memory_get_dirty ( addr + tmp ,
VGA_DIRTY_FLAG );
}
}
if ( dirty || new_dirty || s -> invalidate ) {
fn ( pallette , dest , src , s -> cols );
if ( first == - 1 )
first = i ;
last = i ;
}
dirty = new_dirty ;
addr += src_width ;
dest += dest_width ;
src += src_width ;
}
if ( first < 0 )
return ;
s -> invalidate = 0 ;
cpu_physical_memory_reset_dirty ( base + first * src_width ,
base + ( last + 1 ) * src_width ,
VGA_DIRTY_FLAG );
dpy_update ( s -> ds , 0 , first , s -> cols , last - first + 1 );
}
228
static void pl110_invalidate_display ( void * opaque )
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
{
pl110_state * s = ( pl110_state * ) opaque ;
s -> invalidate = 1 ;
}
static void pl110_update_pallette ( pl110_state * s , int n )
{
int i ;
uint32_t raw ;
unsigned int r , g , b ;
raw = s -> raw_pallette [ n ];
n <<= 1 ;
for ( i = 0 ; i < 2 ; i ++ ) {
r = ( raw & 0x1f ) << 3 ;
raw >>= 5 ;
g = ( raw & 0x1f ) << 3 ;
raw >>= 5 ;
b = ( raw & 0x1f ) << 3 ;
/* The I bit is ignored. */
raw >>= 6 ;
switch ( s -> ds -> depth ) {
case 8 :
s -> pallette [ n ] = rgb_to_pixel8 ( r , g , b );
break ;
case 15 :
s -> pallette [ n ] = rgb_to_pixel15 ( r , g , b );
break ;
case 16 :
s -> pallette [ n ] = rgb_to_pixel16 ( r , g , b );
break ;
case 24 :
case 32 :
s -> pallette [ n ] = rgb_to_pixel32 ( r , g , b );
break ;
}
n ++ ;
}
}
static void pl110_resize ( pl110_state * s , int width , int height )
{
if ( width != s -> cols || height != s -> rows ) {
if ( pl110_enabled ( s )) {
273
dpy_resize ( s -> ds , width , height );
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
}
}
s -> cols = width ;
s -> rows = height ;
}
/* Update interrupts. */
static void pl110_update ( pl110_state * s )
{
/* TODO: Implement interrupts. */
}
static uint32_t pl110_read ( void * opaque , target_phys_addr_t offset )
{
pl110_state * s = ( pl110_state * ) opaque ;
offset -= s -> base ;
if ( offset >= 0xfe0 && offset < 0x1000 ) {
292
293
294
295
if ( s -> versatile )
return pl110_versatile_id [( offset - 0xfe0 ) >> 2 ];
else
return pl110_id [( offset - 0xfe0 ) >> 2 ];
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
}
if ( offset >= 0x200 && offset < 0x400 ) {
return s -> raw_pallette [( offset - 0x200 ) >> 2 ];
}
switch ( offset >> 2 ) {
case 0 : /* LCDTiming0 */
return s -> timing [ 0 ];
case 1 : /* LCDTiming1 */
return s -> timing [ 1 ];
case 2 : /* LCDTiming2 */
return s -> timing [ 2 ];
case 3 : /* LCDTiming3 */
return s -> timing [ 3 ];
case 4 : /* LCDUPBASE */
return s -> upbase ;
case 5 : /* LCDLPBASE */
return s -> lpbase ;
case 6 : /* LCDIMSC */
314
315
if ( s -> versatile )
return s -> cr ;
316
317
return s -> int_mask ;
case 7 : /* LCDControl */
318
319
if ( s -> versatile )
return s -> int_mask ;
320
321
322
323
324
325
326
327
328
329
330
return s -> cr ;
case 8 : /* LCDRIS */
return s -> int_status ;
case 9 : /* LCDMIS */
return s -> int_status & s -> int_mask ;
case 11 : /* LCDUPCURR */
/* TODO: Implement vertical refresh. */
return s -> upbase ;
case 12 : /* LCDLPCURR */
return s -> lpbase ;
default :
331
cpu_abort ( cpu_single_env , "pl110_read: Bad offset %x \n " , ( int ) offset );
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
return 0 ;
}
}
static void pl110_write ( void * opaque , target_phys_addr_t offset ,
uint32_t val )
{
pl110_state * s = ( pl110_state * ) opaque ;
int n ;
/* For simplicity invalidate the display whenever a control register
is writen to . */
s -> invalidate = 1 ;
offset -= s -> base ;
if ( offset >= 0x200 && offset < 0x400 ) {
/* Pallette. */
n = ( offset - 0x200 ) >> 2 ;
s -> raw_pallette [( offset - 0x200 ) >> 2 ] = val ;
pl110_update_pallette ( s , n );
351
return ;
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
}
switch ( offset >> 2 ) {
case 0 : /* LCDTiming0 */
s -> timing [ 0 ] = val ;
n = (( val & 0xfc ) + 4 ) * 4 ;
pl110_resize ( s , n , s -> rows );
break ;
case 1 : /* LCDTiming1 */
s -> timing [ 1 ] = val ;
n = ( val & 0x3ff ) + 1 ;
pl110_resize ( s , s -> cols , n );
break ;
case 2 : /* LCDTiming2 */
s -> timing [ 2 ] = val ;
break ;
case 3 : /* LCDTiming3 */
s -> timing [ 3 ] = val ;
break ;
case 4 : /* LCDUPBASE */
s -> upbase = val ;
break ;
case 5 : /* LCDLPBASE */
s -> lpbase = val ;
break ;
case 6 : /* LCDIMSC */
377
378
379
if ( s -> versatile )
goto control ;
imsc :
380
381
382
383
s -> int_mask = val ;
pl110_update ( s );
break ;
case 7 : /* LCDControl */
384
385
386
if ( s -> versatile )
goto imsc ;
control :
387
388
389
390
391
392
393
394
395
396
397
s -> cr = val ;
s -> bpp = ( val >> 1 ) & 7 ;
if ( pl110_enabled ( s )) {
dpy_resize ( s -> ds , s -> cols , s -> rows );
}
break ;
case 10 : /* LCDICR */
s -> int_status &= ~ val ;
pl110_update ( s );
break ;
default :
398
cpu_abort ( cpu_single_env , "pl110_write: Bad offset %x \n " , ( int ) offset );
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
}
}
static CPUReadMemoryFunc * pl110_readfn [] = {
pl110_read ,
pl110_read ,
pl110_read
};
static CPUWriteMemoryFunc * pl110_writefn [] = {
pl110_write ,
pl110_write ,
pl110_write
};
414
void * pl110_init ( DisplayState * ds , uint32_t base , qemu_irq irq ,
415
int versatile )
416
417
418
419
420
421
422
{
pl110_state * s ;
int iomemtype ;
s = ( pl110_state * ) qemu_mallocz ( sizeof ( pl110_state ));
iomemtype = cpu_register_io_memory ( 0 , pl110_readfn ,
pl110_writefn , s );
423
cpu_register_physical_memory ( base , 0x00001000 , iomemtype );
424
425
s -> base = base ;
s -> ds = ds ;
426
s -> versatile = versatile ;
427
s -> irq = irq ;
428
graphic_console_init ( ds , pl110_update_display , pl110_invalidate_display ,
429
NULL , NULL , s );
430
431
432
/* ??? Save/restore. */
return s ;
}