1
2
/*
* APIC support
ths
authored
18 years ago
3
*
4
5
6
7
8
9
10
11
12
13
14
15
16
17
* Copyright ( c ) 2004 - 2005 Fabrice Bellard
*
* This library is free software ; you can redistribute it and / or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation ; either
* version 2 of the License , or ( at your option ) any later version .
*
* This library is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the GNU
* Lesser General Public License for more details .
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library ; if not , write to the Free Software
18
* Foundation , Inc ., 51 Franklin Street , Fifth Floor , Boston MA 02110 - 1301 USA
19
*/
20
21
22
# include "hw.h"
# include "pc.h"
# include "qemu-timer.h"
23
# include "host-utils.h"
24
25
// # define DEBUG_APIC
26
// # define DEBUG_IOAPIC
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
/* APIC Local Vector Table */
# define APIC_LVT_TIMER 0
# define APIC_LVT_THERMAL 1
# define APIC_LVT_PERFORM 2
# define APIC_LVT_LINT0 3
# define APIC_LVT_LINT1 4
# define APIC_LVT_ERROR 5
# define APIC_LVT_NB 6
/* APIC delivery modes */
# define APIC_DM_FIXED 0
# define APIC_DM_LOWPRI 1
# define APIC_DM_SMI 2
# define APIC_DM_NMI 4
# define APIC_DM_INIT 5
# define APIC_DM_SIPI 6
# define APIC_DM_EXTINT 7
46
47
48
49
/* APIC destination mode */
# define APIC_DESTMODE_FLAT 0xf
# define APIC_DESTMODE_CLUSTER 1
50
51
52
53
54
55
56
57
58
59
# define APIC_TRIGGER_EDGE 0
# define APIC_TRIGGER_LEVEL 1
# define APIC_LVT_TIMER_PERIODIC ( 1 << 17 )
# define APIC_LVT_MASKED ( 1 << 16 )
# define APIC_LVT_LEVEL_TRIGGER ( 1 << 15 )
# define APIC_LVT_REMOTE_IRR ( 1 << 14 )
# define APIC_INPUT_POLARITY ( 1 << 13 )
# define APIC_SEND_PENDING ( 1 << 12 )
60
61
# define IOAPIC_NUM_PINS 0x18
62
63
64
65
# define ESR_ILLEGAL_ADDRESS ( 1 << 7 )
# define APIC_SV_ENABLE ( 1 << 8 )
66
67
68
# define MAX_APICS 255
# define MAX_APIC_WORDS 8
69
70
71
72
typedef struct APICState {
CPUState * cpu_env ;
uint32_t apicbase ;
uint8_t id ;
73
uint8_t arb_id ;
74
75
uint8_t tpr ;
uint32_t spurious_vec ;
76
77
uint8_t log_dest ;
uint8_t dest_mode ;
78
79
80
81
82
83
84
85
86
87
88
89
90
91
uint32_t isr [ 8 ]; /* in service register */
uint32_t tmr [ 8 ]; /* trigger mode register */
uint32_t irr [ 8 ]; /* interrupt request register */
uint32_t lvt [ APIC_LVT_NB ];
uint32_t esr ; /* error register */
uint32_t icr [ 2 ];
uint32_t divide_conf ;
int count_shift ;
uint32_t initial_count ;
int64_t initial_count_load_time , next_time ;
QEMUTimer * timer ;
} APICState ;
92
93
94
95
96
97
98
99
struct IOAPICState {
uint8_t id ;
uint8_t ioregsel ;
uint32_t irr ;
uint64_t ioredtbl [ IOAPIC_NUM_PINS ];
};
100
static int apic_io_memory ;
101
static APICState * local_apics [ MAX_APICS + 1 ];
102
103
104
105
106
107
static int last_apic_id = 0 ;
static void apic_init_ipi ( APICState * s );
static void apic_set_irq ( APICState * s , int vector_num , int trigger_mode );
static void apic_update_irq ( APICState * s );
108
109
110
111
112
113
/* Find first bit starting from msb */
static int fls_bit ( uint32_t value )
{
return 31 - clz32 ( value );
}
114
/* Find first bit starting from lsb */
115
116
static int ffs_bit ( uint32_t value )
{
117
return ctz32 ( value );
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
}
static inline void set_bit ( uint32_t * tab , int index )
{
int i , mask ;
i = index >> 5 ;
mask = 1 << ( index & 0x1f );
tab [ i ] |= mask ;
}
static inline void reset_bit ( uint32_t * tab , int index )
{
int i , mask ;
i = index >> 5 ;
mask = 1 << ( index & 0x1f );
tab [ i ] &= ~ mask ;
}
136
static void apic_local_deliver ( CPUState * env , int vector )
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
{
APICState * s = env -> apic_state ;
uint32_t lvt = s -> lvt [ vector ];
int trigger_mode ;
if ( lvt & APIC_LVT_MASKED )
return ;
switch (( lvt >> 8 ) & 7 ) {
case APIC_DM_SMI :
cpu_interrupt ( env , CPU_INTERRUPT_SMI );
break ;
case APIC_DM_NMI :
cpu_interrupt ( env , CPU_INTERRUPT_NMI );
break ;
case APIC_DM_EXTINT :
cpu_interrupt ( env , CPU_INTERRUPT_HARD );
break ;
case APIC_DM_FIXED :
trigger_mode = APIC_TRIGGER_EDGE ;
if (( vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1 ) &&
( lvt & APIC_LVT_LEVEL_TRIGGER ))
trigger_mode = APIC_TRIGGER_LEVEL ;
apic_set_irq ( s , lvt & 0xff , trigger_mode );
}
}
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
void apic_deliver_pic_intr ( CPUState * env , int level )
{
if ( level )
apic_local_deliver ( env , APIC_LVT_LINT0 );
else {
APICState * s = env -> apic_state ;
uint32_t lvt = s -> lvt [ APIC_LVT_LINT0 ];
switch (( lvt >> 8 ) & 7 ) {
case APIC_DM_FIXED :
if ( ! ( lvt & APIC_LVT_LEVEL_TRIGGER ))
break ;
reset_bit ( s -> irr , lvt & 0xff );
/* fall through */
case APIC_DM_EXTINT :
cpu_reset_interrupt ( env , CPU_INTERRUPT_HARD );
break ;
}
}
}
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
# define foreach_apic ( apic , deliver_bitmask , code ) \
{ \
int __i , __j , __mask ; \
for ( __i = 0 ; __i < MAX_APIC_WORDS ; __i ++ ) { \
__mask = deliver_bitmask [ __i ]; \
if ( __mask ) { \
for ( __j = 0 ; __j < 32 ; __j ++ ) { \
if ( __mask & ( 1 << __j )) { \
apic = local_apics [ __i * 32 + __j ]; \
if ( apic ) { \
code ; \
} \
} \
} \
} \
} \
}
ths
authored
18 years ago
206
static void apic_bus_deliver ( const uint32_t * deliver_bitmask ,
207
uint8_t delivery_mode ,
208
209
210
211
212
213
214
uint8_t vector_num , uint8_t polarity ,
uint8_t trigger_mode )
{
APICState * apic_iter ;
switch ( delivery_mode ) {
case APIC_DM_LOWPRI :
215
/* XXX: search for focus processor, arbitration */
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
{
int i , d ;
d = - 1 ;
for ( i = 0 ; i < MAX_APIC_WORDS ; i ++ ) {
if ( deliver_bitmask [ i ]) {
d = i * 32 + ffs_bit ( deliver_bitmask [ i ]);
break ;
}
}
if ( d >= 0 ) {
apic_iter = local_apics [ d ];
if ( apic_iter ) {
apic_set_irq ( apic_iter , vector_num , trigger_mode );
}
}
231
}
232
return ;
233
234
235
236
237
case APIC_DM_FIXED :
break ;
case APIC_DM_SMI :
238
239
240
241
foreach_apic ( apic_iter , deliver_bitmask ,
cpu_interrupt ( apic_iter -> cpu_env , CPU_INTERRUPT_SMI ) );
return ;
242
case APIC_DM_NMI :
243
244
245
foreach_apic ( apic_iter , deliver_bitmask ,
cpu_interrupt ( apic_iter -> cpu_env , CPU_INTERRUPT_NMI ) );
return ;
246
247
248
case APIC_DM_INIT :
/* normal INIT IPI sent to processors */
ths
authored
18 years ago
249
foreach_apic ( apic_iter , deliver_bitmask ,
250
apic_init_ipi ( apic_iter ) );
251
return ;
ths
authored
18 years ago
252
253
case APIC_DM_EXTINT :
254
/* handled in I/O APIC code */
255
256
257
258
259
260
break ;
default :
return ;
}
ths
authored
18 years ago
261
foreach_apic ( apic_iter , deliver_bitmask ,
262
apic_set_irq ( apic_iter , vector_num , trigger_mode ) );
263
}
264
265
266
267
268
void cpu_set_apic_base ( CPUState * env , uint64_t val )
{
APICState * s = env -> apic_state ;
# ifdef DEBUG_APIC
269
printf ( "cpu_set_apic_base: %016" PRIx64 " \n " , val );
270
# endif
ths
authored
18 years ago
271
s -> apicbase = ( val & 0xfffff000 ) |
272
273
274
275
276
277
278
279
280
281
282
283
284
( s -> apicbase & ( MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE ));
/* if disabled, cannot be enabled again */
if ( ! ( val & MSR_IA32_APICBASE_ENABLE )) {
s -> apicbase &= ~ MSR_IA32_APICBASE_ENABLE ;
env -> cpuid_features &= ~ CPUID_APIC ;
s -> spurious_vec &= ~ APIC_SV_ENABLE ;
}
}
uint64_t cpu_get_apic_base ( CPUState * env )
{
APICState * s = env -> apic_state ;
# ifdef DEBUG_APIC
285
printf ( "cpu_get_apic_base: %016" PRIx64 " \n " , ( uint64_t ) s -> apicbase );
286
287
288
289
# endif
return s -> apicbase ;
}
290
291
292
293
void cpu_set_apic_tpr ( CPUX86State * env , uint8_t val )
{
APICState * s = env -> apic_state ;
s -> tpr = ( val & 0x0f ) << 4 ;
294
apic_update_irq ( s );
295
296
297
298
299
300
301
302
}
uint8_t cpu_get_apic_tpr ( CPUX86State * env )
{
APICState * s = env -> apic_state ;
return s -> tpr >> 4 ;
}
303
304
305
306
307
308
/* return -1 if no bit is set */
static int get_highest_priority_int ( uint32_t * tab )
{
int i ;
for ( i = 7 ; i >= 0 ; i -- ) {
if ( tab [ i ] != 0 ) {
309
return i * 32 + fls_bit ( tab [ i ]);
310
311
312
313
314
}
}
return - 1 ;
}
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
static int apic_get_ppr ( APICState * s )
{
int tpr , isrv , ppr ;
tpr = ( s -> tpr >> 4 );
isrv = get_highest_priority_int ( s -> isr );
if ( isrv < 0 )
isrv = 0 ;
isrv >>= 4 ;
if ( tpr >= isrv )
ppr = s -> tpr ;
else
ppr = isrv << 4 ;
return ppr ;
}
331
332
333
334
335
336
static int apic_get_arb_pri ( APICState * s )
{
/* XXX: arbitration */
return 0 ;
}
337
338
339
/* signal the CPU if an irq is pending */
static void apic_update_irq ( APICState * s )
{
340
341
342
int irrv , ppr ;
if ( ! ( s -> spurious_vec & APIC_SV_ENABLE ))
return ;
343
344
345
irrv = get_highest_priority_int ( s -> irr );
if ( irrv < 0 )
return ;
346
347
ppr = apic_get_ppr ( s );
if ( ppr && ( irrv & 0xf0 ) <= ( ppr & 0xf0 ))
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
return ;
cpu_interrupt ( s -> cpu_env , CPU_INTERRUPT_HARD );
}
static void apic_set_irq ( APICState * s , int vector_num , int trigger_mode )
{
set_bit ( s -> irr , vector_num );
if ( trigger_mode )
set_bit ( s -> tmr , vector_num );
else
reset_bit ( s -> tmr , vector_num );
apic_update_irq ( s );
}
static void apic_eoi ( APICState * s )
{
int isrv ;
isrv = get_highest_priority_int ( s -> isr );
if ( isrv < 0 )
return ;
reset_bit ( s -> isr , isrv );
369
370
/* XXX : send the EOI packet to the APIC bus to allow the I / O APIC to
set the remote IRR bit for level triggered interrupts . */
371
372
373
apic_update_irq ( s );
}
374
375
static void apic_get_delivery_bitmask ( uint32_t * deliver_bitmask ,
uint8_t dest , uint8_t dest_mode )
376
377
{
APICState * apic_iter ;
378
int i ;
379
380
if ( dest_mode == 0 ) {
381
382
383
384
385
386
if ( dest == 0xff ) {
memset ( deliver_bitmask , 0xff , MAX_APIC_WORDS * sizeof ( uint32_t ));
} else {
memset ( deliver_bitmask , 0x00 , MAX_APIC_WORDS * sizeof ( uint32_t ));
set_bit ( deliver_bitmask , dest );
}
387
388
} else {
/* XXX: cluster mode */
389
390
391
392
393
394
395
396
397
398
399
400
401
402
memset ( deliver_bitmask , 0x00 , MAX_APIC_WORDS * sizeof ( uint32_t ));
for ( i = 0 ; i < MAX_APICS ; i ++ ) {
apic_iter = local_apics [ i ];
if ( apic_iter ) {
if ( apic_iter -> dest_mode == 0xf ) {
if ( dest & apic_iter -> log_dest )
set_bit ( deliver_bitmask , i );
} else if ( apic_iter -> dest_mode == 0x0 ) {
if (( dest & 0xf0 ) == ( apic_iter -> log_dest & 0xf0 ) &&
( dest & apic_iter -> log_dest & 0x0f )) {
set_bit ( deliver_bitmask , i );
}
}
}
403
404
405
406
407
408
409
410
411
412
413
414
}
}
}
static void apic_init_ipi ( APICState * s )
{
int i ;
s -> tpr = 0 ;
s -> spurious_vec = 0xff ;
s -> log_dest = 0 ;
415
s -> dest_mode = 0xf ;
416
417
418
memset ( s -> isr , 0 , sizeof ( s -> isr ));
memset ( s -> tmr , 0 , sizeof ( s -> tmr ));
memset ( s -> irr , 0 , sizeof ( s -> irr ));
419
420
for ( i = 0 ; i < APIC_LVT_NB ; i ++ )
s -> lvt [ i ] = 1 << 16 ; /* mask LVT */
421
422
423
424
425
426
427
s -> esr = 0 ;
memset ( s -> icr , 0 , sizeof ( s -> icr ));
s -> divide_conf = 0 ;
s -> count_shift = 0 ;
s -> initial_count = 0 ;
s -> initial_count_load_time = 0 ;
s -> next_time = 0 ;
428
429
430
431
432
cpu_reset ( s -> cpu_env );
if ( ! ( s -> apicbase & MSR_IA32_APICBASE_BSP ))
s -> cpu_env -> halted = 1 ;
433
434
}
435
436
437
438
/* send a SIPI message to the CPU to start it */
static void apic_startup ( APICState * s , int vector_num )
{
CPUState * env = s -> cpu_env ;
439
if ( ! env -> halted )
440
441
return ;
env -> eip = 0 ;
ths
authored
18 years ago
442
cpu_x86_load_seg_cache ( env , R_CS , vector_num << 8 , vector_num << 12 ,
443
0xffff , 0 );
444
env -> halted = 0 ;
445
446
}
447
448
449
450
static void apic_deliver ( APICState * s , uint8_t dest , uint8_t dest_mode ,
uint8_t delivery_mode , uint8_t vector_num ,
uint8_t polarity , uint8_t trigger_mode )
{
451
uint32_t deliver_bitmask [ MAX_APIC_WORDS ];
452
453
454
int dest_shorthand = ( s -> icr [ 0 ] >> 18 ) & 3 ;
APICState * apic_iter ;
455
switch ( dest_shorthand ) {
456
457
458
459
460
461
462
463
464
465
466
467
468
469
case 0 :
apic_get_delivery_bitmask ( deliver_bitmask , dest , dest_mode );
break ;
case 1 :
memset ( deliver_bitmask , 0x00 , sizeof ( deliver_bitmask ));
set_bit ( deliver_bitmask , s -> id );
break ;
case 2 :
memset ( deliver_bitmask , 0xff , sizeof ( deliver_bitmask ));
break ;
case 3 :
memset ( deliver_bitmask , 0xff , sizeof ( deliver_bitmask ));
reset_bit ( deliver_bitmask , s -> id );
break ;
470
471
}
472
473
474
475
476
477
switch ( delivery_mode ) {
case APIC_DM_INIT :
{
int trig_mode = ( s -> icr [ 0 ] >> 15 ) & 1 ;
int level = ( s -> icr [ 0 ] >> 14 ) & 1 ;
if ( level == 0 && trig_mode == 1 ) {
ths
authored
18 years ago
478
foreach_apic ( apic_iter , deliver_bitmask ,
479
apic_iter -> arb_id = apic_iter -> id );
480
481
482
483
484
485
return ;
}
}
break ;
case APIC_DM_SIPI :
ths
authored
18 years ago
486
foreach_apic ( apic_iter , deliver_bitmask ,
487
apic_startup ( apic_iter , vector_num ) );
488
489
490
491
492
493
494
return ;
}
apic_bus_deliver ( deliver_bitmask , delivery_mode , vector_num , polarity ,
trigger_mode );
}
495
496
497
498
499
500
501
502
503
504
505
int apic_get_interrupt ( CPUState * env )
{
APICState * s = env -> apic_state ;
int intno ;
/* if the APIC is installed or enabled , we let the 8259 handle the
IRQs */
if ( ! s )
return - 1 ;
if ( ! ( s -> spurious_vec & APIC_SV_ENABLE ))
return - 1 ;
ths
authored
18 years ago
506
507
508
509
510
/* XXX: spurious IRQ handling */
intno = get_highest_priority_int ( s -> irr );
if ( intno < 0 )
return - 1 ;
511
512
if ( s -> tpr && intno <= s -> tpr )
return s -> spurious_vec & 0xff ;
513
reset_bit ( s -> irr , intno );
514
515
516
517
518
set_bit ( s -> isr , intno );
apic_update_irq ( s );
return intno ;
}
ths
authored
17 years ago
519
520
521
522
523
524
525
526
527
528
int apic_accept_pic_intr ( CPUState * env )
{
APICState * s = env -> apic_state ;
uint32_t lvt0 ;
if ( ! s )
return - 1 ;
lvt0 = s -> lvt [ APIC_LVT_LINT0 ];
529
530
if (( s -> apicbase & MSR_IA32_APICBASE_ENABLE ) == 0 ||
( lvt0 & APIC_LVT_MASKED ) == 0 )
ths
authored
17 years ago
531
532
533
534
535
return 1 ;
return 0 ;
}
536
537
538
539
static uint32_t apic_get_current_count ( APICState * s )
{
int64_t d ;
uint32_t val ;
ths
authored
18 years ago
540
d = ( qemu_get_clock ( vm_clock ) - s -> initial_count_load_time ) >>
541
542
543
s -> count_shift ;
if ( s -> lvt [ APIC_LVT_TIMER ] & APIC_LVT_TIMER_PERIODIC ) {
/* periodic */
544
val = s -> initial_count - ( d % (( uint64_t ) s -> initial_count + 1 ));
545
546
547
548
549
550
551
552
553
554
555
556
} else {
if ( d >= s -> initial_count )
val = 0 ;
else
val = s -> initial_count - d ;
}
return val ;
}
static void apic_timer_update ( APICState * s , int64_t current_time )
{
int64_t next_time , d ;
ths
authored
18 years ago
557
558
if ( ! ( s -> lvt [ APIC_LVT_TIMER ] & APIC_LVT_MASKED )) {
ths
authored
18 years ago
559
d = ( current_time - s -> initial_count_load_time ) >>
560
561
s -> count_shift ;
if ( s -> lvt [ APIC_LVT_TIMER ] & APIC_LVT_TIMER_PERIODIC ) {
562
563
if ( ! s -> initial_count )
goto no_timer ;
564
d = (( d / (( uint64_t ) s -> initial_count + 1 )) + 1 ) * (( uint64_t ) s -> initial_count + 1 );
565
566
567
} else {
if ( d >= s -> initial_count )
goto no_timer ;
568
d = ( uint64_t ) s -> initial_count + 1 ;
569
570
571
572
573
574
575
576
577
578
579
580
581
582
}
next_time = s -> initial_count_load_time + ( d << s -> count_shift );
qemu_mod_timer ( s -> timer , next_time );
s -> next_time = next_time ;
} else {
no_timer :
qemu_del_timer ( s -> timer );
}
}
static void apic_timer ( void * opaque )
{
APICState * s = opaque ;
583
apic_local_deliver ( s -> cpu_env , APIC_LVT_TIMER );
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
apic_timer_update ( s , s -> next_time );
}
static uint32_t apic_mem_readb ( void * opaque , target_phys_addr_t addr )
{
return 0 ;
}
static uint32_t apic_mem_readw ( void * opaque , target_phys_addr_t addr )
{
return 0 ;
}
static void apic_mem_writeb ( void * opaque , target_phys_addr_t addr , uint32_t val )
{
}
static void apic_mem_writew ( void * opaque , target_phys_addr_t addr , uint32_t val )
{
}
static uint32_t apic_mem_readl ( void * opaque , target_phys_addr_t addr )
{
CPUState * env ;
APICState * s ;
uint32_t val ;
int index ;
env = cpu_single_env ;
if ( ! env )
return 0 ;
s = env -> apic_state ;
index = ( addr >> 4 ) & 0xff ;
switch ( index ) {
case 0x02 : /* id */
val = s -> id << 24 ;
break ;
case 0x03 : /* version */
val = 0x11 | (( APIC_LVT_NB - 1 ) << 16 ); /* version 0x11 */
break ;
case 0x08 :
val = s -> tpr ;
break ;
628
629
630
case 0x09 :
val = apic_get_arb_pri ( s );
break ;
631
632
633
634
case 0x0a :
/* ppr */
val = apic_get_ppr ( s );
break ;
635
636
637
case 0x0b :
val = 0 ;
break ;
638
639
640
641
642
643
case 0x0d :
val = s -> log_dest << 24 ;
break ;
case 0x0e :
val = s -> dest_mode << 28 ;
break ;
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
case 0x0f :
val = s -> spurious_vec ;
break ;
case 0x10 ... 0x17 :
val = s -> isr [ index & 7 ];
break ;
case 0x18 ... 0x1f :
val = s -> tmr [ index & 7 ];
break ;
case 0x20 ... 0x27 :
val = s -> irr [ index & 7 ];
break ;
case 0x28 :
val = s -> esr ;
break ;
case 0x30 :
case 0x31 :
val = s -> icr [ index & 1 ];
break ;
663
664
665
case 0x32 ... 0x37 :
val = s -> lvt [ index - 0x32 ];
break ;
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
case 0x38 :
val = s -> initial_count ;
break ;
case 0x39 :
val = apic_get_current_count ( s );
break ;
case 0x3e :
val = s -> divide_conf ;
break ;
default :
s -> esr |= ESR_ILLEGAL_ADDRESS ;
val = 0 ;
break ;
}
# ifdef DEBUG_APIC
printf ( "APIC read: %08x = %08x \n " , ( uint32_t ) addr , val );
# endif
return val ;
}
static void apic_mem_writel ( void * opaque , target_phys_addr_t addr , uint32_t val )
{
CPUState * env ;
APICState * s ;
int index ;
env = cpu_single_env ;
if ( ! env )
return ;
s = env -> apic_state ;
# ifdef DEBUG_APIC
printf ( "APIC write: %08x = %08x \n " , ( uint32_t ) addr , val );
# endif
index = ( addr >> 4 ) & 0xff ;
switch ( index ) {
case 0x02 :
s -> id = ( val >> 24 );
break ;
706
707
case 0x03 :
break ;
708
709
case 0x08 :
s -> tpr = val ;
710
apic_update_irq ( s );
711
break ;
712
713
714
case 0x09 :
case 0x0a :
break ;
715
716
717
case 0x0b : /* EOI */
apic_eoi ( s );
break ;
718
719
720
721
722
723
case 0x0d :
s -> log_dest = val >> 24 ;
break ;
case 0x0e :
s -> dest_mode = val >> 28 ;
break ;
724
725
case 0x0f :
s -> spurious_vec = val & 0x1ff ;
726
apic_update_irq ( s );
727
break ;
728
729
730
731
732
case 0x10 ... 0x17 :
case 0x18 ... 0x1f :
case 0x20 ... 0x27 :
case 0x28 :
break ;
733
case 0x30 :
734
735
736
737
738
s -> icr [ 0 ] = val ;
apic_deliver ( s , ( s -> icr [ 1 ] >> 24 ) & 0xff , ( s -> icr [ 0 ] >> 11 ) & 1 ,
( s -> icr [ 0 ] >> 8 ) & 7 , ( s -> icr [ 0 ] & 0xff ),
( s -> icr [ 0 ] >> 14 ) & 1 , ( s -> icr [ 0 ] >> 15 ) & 1 );
break ;
739
case 0x31 :
740
s -> icr [ 1 ] = val ;
741
742
743
744
745
746
747
748
749
750
751
752
753
754
break ;
case 0x32 ... 0x37 :
{
int n = index - 0x32 ;
s -> lvt [ n ] = val ;
if ( n == APIC_LVT_TIMER )
apic_timer_update ( s , qemu_get_clock ( vm_clock ));
}
break ;
case 0x38 :
s -> initial_count = val ;
s -> initial_count_load_time = qemu_get_clock ( vm_clock );
apic_timer_update ( s , s -> initial_count_load_time );
break ;
755
756
case 0x39 :
break ;
757
758
759
760
761
762
763
764
765
766
767
768
769
770
case 0x3e :
{
int v ;
s -> divide_conf = val & 0xb ;
v = ( s -> divide_conf & 3 ) | (( s -> divide_conf >> 1 ) & 4 );
s -> count_shift = ( v + 1 ) & 7 ;
}
break ;
default :
s -> esr |= ESR_ILLEGAL_ADDRESS ;
break ;
}
}
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
static void apic_save ( QEMUFile * f , void * opaque )
{
APICState * s = opaque ;
int i ;
qemu_put_be32s ( f , & s -> apicbase );
qemu_put_8s ( f , & s -> id );
qemu_put_8s ( f , & s -> arb_id );
qemu_put_8s ( f , & s -> tpr );
qemu_put_be32s ( f , & s -> spurious_vec );
qemu_put_8s ( f , & s -> log_dest );
qemu_put_8s ( f , & s -> dest_mode );
for ( i = 0 ; i < 8 ; i ++ ) {
qemu_put_be32s ( f , & s -> isr [ i ]);
qemu_put_be32s ( f , & s -> tmr [ i ]);
qemu_put_be32s ( f , & s -> irr [ i ]);
}
for ( i = 0 ; i < APIC_LVT_NB ; i ++ ) {
qemu_put_be32s ( f , & s -> lvt [ i ]);
}
qemu_put_be32s ( f , & s -> esr );
qemu_put_be32s ( f , & s -> icr [ 0 ]);
qemu_put_be32s ( f , & s -> icr [ 1 ]);
qemu_put_be32s ( f , & s -> divide_conf );
ths
authored
17 years ago
795
qemu_put_be32 ( f , s -> count_shift );
796
qemu_put_be32s ( f , & s -> initial_count );
ths
authored
17 years ago
797
798
qemu_put_be64 ( f , s -> initial_count_load_time );
qemu_put_be64 ( f , s -> next_time );
799
800
qemu_put_timer ( f , s -> timer );
801
802
803
804
805
806
807
}
static int apic_load ( QEMUFile * f , void * opaque , int version_id )
{
APICState * s = opaque ;
int i ;
808
if ( version_id > 2 )
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
return - EINVAL ;
/* XXX: what if the base changes? (registered memory regions) */
qemu_get_be32s ( f , & s -> apicbase );
qemu_get_8s ( f , & s -> id );
qemu_get_8s ( f , & s -> arb_id );
qemu_get_8s ( f , & s -> tpr );
qemu_get_be32s ( f , & s -> spurious_vec );
qemu_get_8s ( f , & s -> log_dest );
qemu_get_8s ( f , & s -> dest_mode );
for ( i = 0 ; i < 8 ; i ++ ) {
qemu_get_be32s ( f , & s -> isr [ i ]);
qemu_get_be32s ( f , & s -> tmr [ i ]);
qemu_get_be32s ( f , & s -> irr [ i ]);
}
for ( i = 0 ; i < APIC_LVT_NB ; i ++ ) {
qemu_get_be32s ( f , & s -> lvt [ i ]);
}
qemu_get_be32s ( f , & s -> esr );
qemu_get_be32s ( f , & s -> icr [ 0 ]);
qemu_get_be32s ( f , & s -> icr [ 1 ]);
qemu_get_be32s ( f , & s -> divide_conf );
ths
authored
17 years ago
831
s -> count_shift = qemu_get_be32 ( f );
832
qemu_get_be32s ( f , & s -> initial_count );
ths
authored
17 years ago
833
834
s -> initial_count_load_time = qemu_get_be64 ( f );
s -> next_time = qemu_get_be64 ( f );
835
836
837
if ( version_id >= 2 )
qemu_get_timer ( f , s -> timer );
838
839
return 0 ;
}
840
841
842
843
static void apic_reset ( void * opaque )
{
APICState * s = opaque ;
844
845
846
847
s -> apicbase = 0xfee00000 |
( s -> id ? 0 : MSR_IA32_APICBASE_BSP ) | MSR_IA32_APICBASE_ENABLE ;
848
apic_init_ipi ( s );
ths
authored
17 years ago
849
850
851
852
853
854
855
856
857
if ( s -> id == 0 ) {
/*
* LINT0 delivery mode on CPU # 0 is set to ExtInt at initialization
* time typically by BIOS , so PIC interrupt can be delivered to the
* processor when local APIC is enabled .
*/
s -> lvt [ APIC_LVT_LINT0 ] = 0x700 ;
}
858
}
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
static CPUReadMemoryFunc * apic_mem_read [ 3 ] = {
apic_mem_readb ,
apic_mem_readw ,
apic_mem_readl ,
};
static CPUWriteMemoryFunc * apic_mem_write [ 3 ] = {
apic_mem_writeb ,
apic_mem_writew ,
apic_mem_writel ,
};
int apic_init ( CPUState * env )
{
APICState * s ;
876
877
if ( last_apic_id >= MAX_APICS )
return - 1 ;
878
s = qemu_mallocz ( sizeof ( APICState ));
879
880
881
if ( ! s )
return - 1 ;
env -> apic_state = s ;
882
s -> id = last_apic_id ++ ;
ths
authored
18 years ago
883
env -> cpuid_apic_id = s -> id ;
884
885
s -> cpu_env = env ;
886
apic_reset ( s );
ths
authored
17 years ago
887
888
/* XXX: mapping more APICs at the same memory location */
889
890
891
if ( apic_io_memory == 0 ) {
/* NOTE : the APIC is directly connected to the CPU - it is not
on the global memory bus . */
ths
authored
18 years ago
892
apic_io_memory = cpu_register_io_memory ( 0 , apic_mem_read ,
893
apic_mem_write , NULL );
894
895
cpu_register_physical_memory ( s -> apicbase & ~ 0xfff , 0x1000 ,
apic_io_memory );
896
897
}
s -> timer = qemu_new_timer ( vm_clock , apic_timer , s );
898
ths
authored
18 years ago
899
register_savevm ( "apic" , s -> id , 2 , apic_save , apic_load , s );
900
qemu_register_reset ( apic_reset , s );
ths
authored
18 years ago
901
902
local_apics [ s -> id ] = s ;
903
904
905
906
907
return 0 ;
}
static void ioapic_service ( IOAPICState * s )
{
908
909
uint8_t i ;
uint8_t trig_mode ;
910
uint8_t vector ;
911
uint8_t delivery_mode ;
912
913
914
915
uint32_t mask ;
uint64_t entry ;
uint8_t dest ;
uint8_t dest_mode ;
916
uint8_t polarity ;
917
uint32_t deliver_bitmask [ MAX_APIC_WORDS ];
918
919
920
for ( i = 0 ; i < IOAPIC_NUM_PINS ; i ++ ) {
mask = 1 << i ;
921
if ( s -> irr & mask ) {
922
entry = s -> ioredtbl [ i ];
923
if ( ! ( entry & APIC_LVT_MASKED )) {
924
trig_mode = (( entry >> 15 ) & 1 );
925
926
dest = entry >> 56 ;
dest_mode = ( entry >> 11 ) & 1 ;
927
928
929
930
931
932
933
934
delivery_mode = ( entry >> 8 ) & 7 ;
polarity = ( entry >> 13 ) & 1 ;
if ( trig_mode == APIC_TRIGGER_EDGE )
s -> irr &= ~ mask ;
if ( delivery_mode == APIC_DM_EXTINT )
vector = pic_read_irq ( isa_pic );
else
vector = entry & 0xff ;
ths
authored
18 years ago
935
936
apic_get_delivery_bitmask ( deliver_bitmask , dest , dest_mode );
ths
authored
18 years ago
937
apic_bus_deliver ( deliver_bitmask , delivery_mode ,
938
vector , polarity , trig_mode );
939
940
941
942
943
944
945
946
947
}
}
}
}
void ioapic_set_irq ( void * opaque , int vector , int level )
{
IOAPICState * s = opaque ;
948
949
950
951
952
953
954
/* ISA IRQs map to GSI 1 - 1 except for IRQ0 which maps
* to GSI 2 . GSI maps to ioapic 1 - 1 . This is not
* the cleanest way of doing it but it should work . */
if ( vector == 0 )
vector = 2 ;
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
if ( vector >= 0 && vector < IOAPIC_NUM_PINS ) {
uint32_t mask = 1 << vector ;
uint64_t entry = s -> ioredtbl [ vector ];
if (( entry >> 15 ) & 1 ) {
/* level triggered */
if ( level ) {
s -> irr |= mask ;
ioapic_service ( s );
} else {
s -> irr &= ~ mask ;
}
} else {
/* edge triggered */
if ( level ) {
s -> irr |= mask ;
ioapic_service ( s );
}
}
}
}
static uint32_t ioapic_mem_readl ( void * opaque , target_phys_addr_t addr )
{
IOAPICState * s = opaque ;
int index ;
uint32_t val = 0 ;
addr &= 0xff ;
if ( addr == 0x00 ) {
val = s -> ioregsel ;
} else if ( addr == 0x10 ) {
switch ( s -> ioregsel ) {
case 0x00 :
val = s -> id << 24 ;
break ;
case 0x01 :
val = 0x11 | (( IOAPIC_NUM_PINS - 1 ) << 16 ); /* version 0x11 */
break ;
case 0x02 :
val = 0 ;
break ;
default :
index = ( s -> ioregsel - 0x10 ) >> 1 ;
if ( index >= 0 && index < IOAPIC_NUM_PINS ) {
if ( s -> ioregsel & 1 )
val = s -> ioredtbl [ index ] >> 32 ;
else
val = s -> ioredtbl [ index ] & 0xffffffff ;
}
}
# ifdef DEBUG_IOAPIC
printf ( "I/O APIC read: %08x = %08x \n " , s -> ioregsel , val );
# endif
}
return val ;
}
static void ioapic_mem_writel ( void * opaque , target_phys_addr_t addr , uint32_t val )
{
IOAPICState * s = opaque ;
int index ;
addr &= 0xff ;
if ( addr == 0x00 ) {
s -> ioregsel = val ;
return ;
} else if ( addr == 0x10 ) {
# ifdef DEBUG_IOAPIC
printf ( "I/O APIC write: %08x = %08x \n " , s -> ioregsel , val );
# endif
switch ( s -> ioregsel ) {
case 0x00 :
s -> id = ( val >> 24 ) & 0xff ;
return ;
case 0x01 :
case 0x02 :
return ;
default :
index = ( s -> ioregsel - 0x10 ) >> 1 ;
if ( index >= 0 && index < IOAPIC_NUM_PINS ) {
if ( s -> ioregsel & 1 ) {
s -> ioredtbl [ index ] &= 0xffffffff ;
s -> ioredtbl [ index ] |= ( uint64_t ) val << 32 ;
} else {
s -> ioredtbl [ index ] &= ~ 0xffffffffULL ;
s -> ioredtbl [ index ] |= val ;
}
ioapic_service ( s );
}
}
}
}
static void ioapic_save ( QEMUFile * f , void * opaque )
{
IOAPICState * s = opaque ;
int i ;
qemu_put_8s ( f , & s -> id );
qemu_put_8s ( f , & s -> ioregsel );
for ( i = 0 ; i < IOAPIC_NUM_PINS ; i ++ ) {
qemu_put_be64s ( f , & s -> ioredtbl [ i ]);
}
}
static int ioapic_load ( QEMUFile * f , void * opaque , int version_id )
{
IOAPICState * s = opaque ;
int i ;
if ( version_id != 1 )
return - EINVAL ;
qemu_get_8s ( f , & s -> id );
qemu_get_8s ( f , & s -> ioregsel );
for ( i = 0 ; i < IOAPIC_NUM_PINS ; i ++ ) {
qemu_get_be64s ( f , & s -> ioredtbl [ i ]);
}
1074
1075
return 0 ;
}
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
static void ioapic_reset ( void * opaque )
{
IOAPICState * s = opaque ;
int i ;
memset ( s , 0 , sizeof ( * s ));
for ( i = 0 ; i < IOAPIC_NUM_PINS ; i ++ )
s -> ioredtbl [ i ] = 1 << 16 ; /* mask LVT */
}
static CPUReadMemoryFunc * ioapic_mem_read [ 3 ] = {
ioapic_mem_readl ,
ioapic_mem_readl ,
ioapic_mem_readl ,
};
static CPUWriteMemoryFunc * ioapic_mem_write [ 3 ] = {
ioapic_mem_writel ,
ioapic_mem_writel ,
ioapic_mem_writel ,
};
IOAPICState * ioapic_init ( void )
{
IOAPICState * s ;
int io_memory ;
1104
s = qemu_mallocz ( sizeof ( IOAPICState ));
1105
1106
1107
1108
1109
if ( ! s )
return NULL ;
ioapic_reset ( s );
s -> id = last_apic_id ++ ;
ths
authored
18 years ago
1110
io_memory = cpu_register_io_memory ( 0 , ioapic_mem_read ,
1111
1112
1113
1114
1115
ioapic_mem_write , s );
cpu_register_physical_memory ( 0xfec00000 , 0x1000 , io_memory );
register_savevm ( "ioapic" , 0 , 1 , ioapic_save , ioapic_load , s );
qemu_register_reset ( ioapic_reset , s );
ths
authored
18 years ago
1116
1117
1118
return s ;
}