Commit f930d07eda320b221360556eaa0c695c48173567
1 parent
81732d19
More detabification
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3338 c046a42c-6fe2-441c-8c8c-71466251a162
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14 changed files
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2547 additions
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2547 deletions
hw/apb_pci.c
... | ... | @@ -70,7 +70,7 @@ static CPUReadMemoryFunc *pci_apb_config_read[] = { |
70 | 70 | }; |
71 | 71 | |
72 | 72 | static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
73 | - uint32_t val) | |
73 | + uint32_t val) | |
74 | 74 | { |
75 | 75 | //PCIBus *s = opaque; |
76 | 76 | |
... | ... | @@ -80,14 +80,14 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
80 | 80 | case 0x18: // AFAR |
81 | 81 | case 0x20: // Diagnostic |
82 | 82 | case 0x28: // Target address space |
83 | - // XXX | |
83 | + // XXX | |
84 | 84 | default: |
85 | - break; | |
85 | + break; | |
86 | 86 | } |
87 | 87 | } |
88 | 88 | |
89 | 89 | static uint32_t apb_config_readl (void *opaque, |
90 | - target_phys_addr_t addr) | |
90 | + target_phys_addr_t addr) | |
91 | 91 | { |
92 | 92 | //PCIBus *s = opaque; |
93 | 93 | uint32_t val; |
... | ... | @@ -98,10 +98,10 @@ static uint32_t apb_config_readl (void *opaque, |
98 | 98 | case 0x18: // AFAR |
99 | 99 | case 0x20: // Diagnostic |
100 | 100 | case 0x28: // Target address space |
101 | - // XXX | |
101 | + // XXX | |
102 | 102 | default: |
103 | - val = 0; | |
104 | - break; | |
103 | + val = 0; | |
104 | + break; | |
105 | 105 | } |
106 | 106 | return val; |
107 | 107 | } |
... | ... | @@ -222,7 +222,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, |
222 | 222 | pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read, |
223 | 223 | pci_apb_config_write, s); |
224 | 224 | apb_config = cpu_register_io_memory(0, apb_config_read, |
225 | - apb_config_write, s); | |
225 | + apb_config_write, s); | |
226 | 226 | pci_mem_data = cpu_register_io_memory(0, pci_apb_read, |
227 | 227 | pci_apb_write, s); |
228 | 228 | pci_ioport = cpu_register_io_memory(0, pci_apb_ioread, | ... | ... |
hw/cs4231.c
... | ... | @@ -79,11 +79,11 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
79 | 79 | break; |
80 | 80 | } |
81 | 81 | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); |
82 | - break; | |
82 | + break; | |
83 | 83 | default: |
84 | 84 | ret = s->regs[saddr]; |
85 | 85 | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); |
86 | - break; | |
86 | + break; | |
87 | 87 | } |
88 | 88 | return ret; |
89 | 89 | } |
... | ... | @@ -122,7 +122,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
122 | 122 | break; |
123 | 123 | default: |
124 | 124 | s->regs[saddr] = val; |
125 | - break; | |
125 | + break; | |
126 | 126 | } |
127 | 127 | } |
128 | 128 | ... | ... |
hw/esp.c
... | ... | @@ -107,9 +107,9 @@ static int get_cmd(ESPState *s, uint8_t *buf) |
107 | 107 | if (s->dma) { |
108 | 108 | espdma_memory_read(s->dma_opaque, buf, dmalen); |
109 | 109 | } else { |
110 | - buf[0] = 0; | |
111 | - memcpy(&buf[1], s->ti_buf, dmalen); | |
112 | - dmalen++; | |
110 | + buf[0] = 0; | |
111 | + memcpy(&buf[1], s->ti_buf, dmalen); | |
112 | + dmalen++; | |
113 | 113 | } |
114 | 114 | |
115 | 115 | s->ti_size = 0; |
... | ... | @@ -124,11 +124,11 @@ static int get_cmd(ESPState *s, uint8_t *buf) |
124 | 124 | |
125 | 125 | if (target >= MAX_DISKS || !s->scsi_dev[target]) { |
126 | 126 | // No such drive |
127 | - s->rregs[4] = STAT_IN; | |
128 | - s->rregs[5] = INTR_DC; | |
129 | - s->rregs[6] = SEQ_0; | |
130 | - qemu_irq_raise(s->irq); | |
131 | - return 0; | |
127 | + s->rregs[4] = STAT_IN; | |
128 | + s->rregs[5] = INTR_DC; | |
129 | + s->rregs[6] = SEQ_0; | |
130 | + qemu_irq_raise(s->irq); | |
131 | + return 0; | |
132 | 132 | } |
133 | 133 | s->current_dev = s->scsi_dev[target]; |
134 | 134 | return dmalen; |
... | ... | @@ -190,14 +190,14 @@ static void write_response(ESPState *s) |
190 | 190 | s->ti_buf[1] = 0; |
191 | 191 | if (s->dma) { |
192 | 192 | espdma_memory_write(s->dma_opaque, s->ti_buf, 2); |
193 | - s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; | |
194 | - s->rregs[5] = INTR_BS | INTR_FC; | |
195 | - s->rregs[6] = SEQ_CD; | |
193 | + s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; | |
194 | + s->rregs[5] = INTR_BS | INTR_FC; | |
195 | + s->rregs[6] = SEQ_CD; | |
196 | 196 | } else { |
197 | - s->ti_size = 2; | |
198 | - s->ti_rptr = 0; | |
199 | - s->ti_wptr = 0; | |
200 | - s->rregs[7] = 2; | |
197 | + s->ti_size = 2; | |
198 | + s->ti_rptr = 0; | |
199 | + s->ti_wptr = 0; | |
200 | + s->rregs[7] = 2; | |
201 | 201 | } |
202 | 202 | qemu_irq_raise(s->irq); |
203 | 203 | } |
... | ... | @@ -359,9 +359,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
359 | 359 | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
360 | 360 | switch (saddr) { |
361 | 361 | case 2: |
362 | - // FIFO | |
363 | - if (s->ti_size > 0) { | |
364 | - s->ti_size--; | |
362 | + // FIFO | |
363 | + if (s->ti_size > 0) { | |
364 | + s->ti_size--; | |
365 | 365 | if ((s->rregs[4] & 6) == 0) { |
366 | 366 | /* Data in/out. */ |
367 | 367 | fprintf(stderr, "esp: PIO data read not implemented\n"); |
... | ... | @@ -370,20 +370,20 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
370 | 370 | s->rregs[2] = s->ti_buf[s->ti_rptr++]; |
371 | 371 | } |
372 | 372 | qemu_irq_raise(s->irq); |
373 | - } | |
374 | - if (s->ti_size == 0) { | |
373 | + } | |
374 | + if (s->ti_size == 0) { | |
375 | 375 | s->ti_rptr = 0; |
376 | 376 | s->ti_wptr = 0; |
377 | 377 | } |
378 | - break; | |
378 | + break; | |
379 | 379 | case 5: |
380 | 380 | // interrupt |
381 | 381 | // Clear interrupt/error status bits |
382 | 382 | s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); |
383 | - qemu_irq_lower(s->irq); | |
383 | + qemu_irq_lower(s->irq); | |
384 | 384 | break; |
385 | 385 | default: |
386 | - break; | |
386 | + break; | |
387 | 387 | } |
388 | 388 | return s->rregs[saddr]; |
389 | 389 | } |
... | ... | @@ -401,7 +401,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
401 | 401 | s->rregs[4] &= ~STAT_TC; |
402 | 402 | break; |
403 | 403 | case 2: |
404 | - // FIFO | |
404 | + // FIFO | |
405 | 405 | if (s->do_cmd) { |
406 | 406 | s->cmdbuf[s->cmdlen++] = val & 0xff; |
407 | 407 | } else if ((s->rregs[4] & 6) == 0) { |
... | ... | @@ -413,73 +413,73 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
413 | 413 | s->ti_size++; |
414 | 414 | s->ti_buf[s->ti_wptr++] = val & 0xff; |
415 | 415 | } |
416 | - break; | |
416 | + break; | |
417 | 417 | case 3: |
418 | 418 | s->rregs[saddr] = val; |
419 | - // Command | |
420 | - if (val & 0x80) { | |
421 | - s->dma = 1; | |
419 | + // Command | |
420 | + if (val & 0x80) { | |
421 | + s->dma = 1; | |
422 | 422 | /* Reload DMA counter. */ |
423 | 423 | s->rregs[0] = s->wregs[0]; |
424 | 424 | s->rregs[1] = s->wregs[1]; |
425 | - } else { | |
426 | - s->dma = 0; | |
427 | - } | |
428 | - switch(val & 0x7f) { | |
429 | - case 0: | |
430 | - DPRINTF("NOP (%2.2x)\n", val); | |
431 | - break; | |
432 | - case 1: | |
433 | - DPRINTF("Flush FIFO (%2.2x)\n", val); | |
425 | + } else { | |
426 | + s->dma = 0; | |
427 | + } | |
428 | + switch(val & 0x7f) { | |
429 | + case 0: | |
430 | + DPRINTF("NOP (%2.2x)\n", val); | |
431 | + break; | |
432 | + case 1: | |
433 | + DPRINTF("Flush FIFO (%2.2x)\n", val); | |
434 | 434 | //s->ti_size = 0; |
435 | - s->rregs[5] = INTR_FC; | |
436 | - s->rregs[6] = 0; | |
437 | - break; | |
438 | - case 2: | |
439 | - DPRINTF("Chip reset (%2.2x)\n", val); | |
440 | - esp_reset(s); | |
441 | - break; | |
442 | - case 3: | |
443 | - DPRINTF("Bus reset (%2.2x)\n", val); | |
444 | - s->rregs[5] = INTR_RST; | |
435 | + s->rregs[5] = INTR_FC; | |
436 | + s->rregs[6] = 0; | |
437 | + break; | |
438 | + case 2: | |
439 | + DPRINTF("Chip reset (%2.2x)\n", val); | |
440 | + esp_reset(s); | |
441 | + break; | |
442 | + case 3: | |
443 | + DPRINTF("Bus reset (%2.2x)\n", val); | |
444 | + s->rregs[5] = INTR_RST; | |
445 | 445 | if (!(s->wregs[8] & 0x40)) { |
446 | 446 | qemu_irq_raise(s->irq); |
447 | 447 | } |
448 | - break; | |
449 | - case 0x10: | |
450 | - handle_ti(s); | |
451 | - break; | |
452 | - case 0x11: | |
453 | - DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); | |
454 | - write_response(s); | |
455 | - break; | |
456 | - case 0x12: | |
457 | - DPRINTF("Message Accepted (%2.2x)\n", val); | |
458 | - write_response(s); | |
459 | - s->rregs[5] = INTR_DC; | |
460 | - s->rregs[6] = 0; | |
461 | - break; | |
462 | - case 0x1a: | |
463 | - DPRINTF("Set ATN (%2.2x)\n", val); | |
464 | - break; | |
465 | - case 0x42: | |
466 | - DPRINTF("Set ATN (%2.2x)\n", val); | |
467 | - handle_satn(s); | |
468 | - break; | |
469 | - case 0x43: | |
470 | - DPRINTF("Set ATN & stop (%2.2x)\n", val); | |
471 | - handle_satn_stop(s); | |
472 | - break; | |
448 | + break; | |
449 | + case 0x10: | |
450 | + handle_ti(s); | |
451 | + break; | |
452 | + case 0x11: | |
453 | + DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); | |
454 | + write_response(s); | |
455 | + break; | |
456 | + case 0x12: | |
457 | + DPRINTF("Message Accepted (%2.2x)\n", val); | |
458 | + write_response(s); | |
459 | + s->rregs[5] = INTR_DC; | |
460 | + s->rregs[6] = 0; | |
461 | + break; | |
462 | + case 0x1a: | |
463 | + DPRINTF("Set ATN (%2.2x)\n", val); | |
464 | + break; | |
465 | + case 0x42: | |
466 | + DPRINTF("Set ATN (%2.2x)\n", val); | |
467 | + handle_satn(s); | |
468 | + break; | |
469 | + case 0x43: | |
470 | + DPRINTF("Set ATN & stop (%2.2x)\n", val); | |
471 | + handle_satn_stop(s); | |
472 | + break; | |
473 | 473 | case 0x44: |
474 | 474 | DPRINTF("Enable selection (%2.2x)\n", val); |
475 | 475 | break; |
476 | - default: | |
477 | - DPRINTF("Unhandled ESP command (%2.2x)\n", val); | |
478 | - break; | |
479 | - } | |
480 | - break; | |
476 | + default: | |
477 | + DPRINTF("Unhandled ESP command (%2.2x)\n", val); | |
478 | + break; | |
479 | + } | |
480 | + break; | |
481 | 481 | case 4 ... 7: |
482 | - break; | |
482 | + break; | |
483 | 483 | case 8: |
484 | 484 | s->rregs[saddr] = val; |
485 | 485 | break; |
... | ... | @@ -492,7 +492,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
492 | 492 | s->rregs[saddr] = val; |
493 | 493 | break; |
494 | 494 | default: |
495 | - break; | |
495 | + break; | |
496 | 496 | } |
497 | 497 | s->wregs[saddr] = val; |
498 | 498 | } | ... | ... |
hw/iommu.c
... | ... | @@ -81,7 +81,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) |
81 | 81 | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
82 | 82 | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
83 | 83 | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
84 | - produced by this device as pure | |
84 | + produced by this device as pure | |
85 | 85 | physical. */ |
86 | 86 | #define IOMMU_SBCFG_MASK 0x00010003 |
87 | 87 | |
... | ... | @@ -98,7 +98,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) |
98 | 98 | |
99 | 99 | #define PAGE_SHIFT 12 |
100 | 100 | #define PAGE_SIZE (1 << PAGE_SHIFT) |
101 | -#define PAGE_MASK (PAGE_SIZE - 1) | |
101 | +#define PAGE_MASK (PAGE_SIZE - 1) | |
102 | 102 | |
103 | 103 | typedef struct IOMMUState { |
104 | 104 | target_phys_addr_t addr; |
... | ... | @@ -114,9 +114,9 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) |
114 | 114 | saddr = (addr - s->addr) >> 2; |
115 | 115 | switch (saddr) { |
116 | 116 | default: |
117 | - DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]); | |
118 | - return s->regs[saddr]; | |
119 | - break; | |
117 | + DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]); | |
118 | + return s->regs[saddr]; | |
119 | + break; | |
120 | 120 | } |
121 | 121 | return 0; |
122 | 122 | } |
... | ... | @@ -130,61 +130,61 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val |
130 | 130 | DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
131 | 131 | switch (saddr) { |
132 | 132 | case IOMMU_CTRL: |
133 | - switch (val & IOMMU_CTRL_RNGE) { | |
134 | - case IOMMU_RNGE_16MB: | |
135 | - s->iostart = 0xffffffffff000000ULL; | |
136 | - break; | |
137 | - case IOMMU_RNGE_32MB: | |
138 | - s->iostart = 0xfffffffffe000000ULL; | |
139 | - break; | |
140 | - case IOMMU_RNGE_64MB: | |
141 | - s->iostart = 0xfffffffffc000000ULL; | |
142 | - break; | |
143 | - case IOMMU_RNGE_128MB: | |
144 | - s->iostart = 0xfffffffff8000000ULL; | |
145 | - break; | |
146 | - case IOMMU_RNGE_256MB: | |
147 | - s->iostart = 0xfffffffff0000000ULL; | |
148 | - break; | |
149 | - case IOMMU_RNGE_512MB: | |
150 | - s->iostart = 0xffffffffe0000000ULL; | |
151 | - break; | |
152 | - case IOMMU_RNGE_1GB: | |
153 | - s->iostart = 0xffffffffc0000000ULL; | |
154 | - break; | |
155 | - default: | |
156 | - case IOMMU_RNGE_2GB: | |
157 | - s->iostart = 0xffffffff80000000ULL; | |
158 | - break; | |
159 | - } | |
160 | - DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); | |
161 | - s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); | |
162 | - break; | |
133 | + switch (val & IOMMU_CTRL_RNGE) { | |
134 | + case IOMMU_RNGE_16MB: | |
135 | + s->iostart = 0xffffffffff000000ULL; | |
136 | + break; | |
137 | + case IOMMU_RNGE_32MB: | |
138 | + s->iostart = 0xfffffffffe000000ULL; | |
139 | + break; | |
140 | + case IOMMU_RNGE_64MB: | |
141 | + s->iostart = 0xfffffffffc000000ULL; | |
142 | + break; | |
143 | + case IOMMU_RNGE_128MB: | |
144 | + s->iostart = 0xfffffffff8000000ULL; | |
145 | + break; | |
146 | + case IOMMU_RNGE_256MB: | |
147 | + s->iostart = 0xfffffffff0000000ULL; | |
148 | + break; | |
149 | + case IOMMU_RNGE_512MB: | |
150 | + s->iostart = 0xffffffffe0000000ULL; | |
151 | + break; | |
152 | + case IOMMU_RNGE_1GB: | |
153 | + s->iostart = 0xffffffffc0000000ULL; | |
154 | + break; | |
155 | + default: | |
156 | + case IOMMU_RNGE_2GB: | |
157 | + s->iostart = 0xffffffff80000000ULL; | |
158 | + break; | |
159 | + } | |
160 | + DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); | |
161 | + s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); | |
162 | + break; | |
163 | 163 | case IOMMU_BASE: |
164 | - s->regs[saddr] = val & IOMMU_BASE_MASK; | |
165 | - break; | |
164 | + s->regs[saddr] = val & IOMMU_BASE_MASK; | |
165 | + break; | |
166 | 166 | case IOMMU_TLBFLUSH: |
167 | - DPRINTF("tlb flush %x\n", val); | |
168 | - s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; | |
169 | - break; | |
167 | + DPRINTF("tlb flush %x\n", val); | |
168 | + s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; | |
169 | + break; | |
170 | 170 | case IOMMU_PGFLUSH: |
171 | - DPRINTF("page flush %x\n", val); | |
172 | - s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; | |
173 | - break; | |
171 | + DPRINTF("page flush %x\n", val); | |
172 | + s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; | |
173 | + break; | |
174 | 174 | case IOMMU_SBCFG0: |
175 | 175 | case IOMMU_SBCFG1: |
176 | 176 | case IOMMU_SBCFG2: |
177 | 177 | case IOMMU_SBCFG3: |
178 | - s->regs[saddr] = val & IOMMU_SBCFG_MASK; | |
179 | - break; | |
178 | + s->regs[saddr] = val & IOMMU_SBCFG_MASK; | |
179 | + break; | |
180 | 180 | case IOMMU_ARBEN: |
181 | 181 | // XXX implement SBus probing: fault when reading unmapped |
182 | 182 | // addresses, fault cause and address stored to MMU/IOMMU |
183 | - s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; | |
184 | - break; | |
183 | + s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; | |
184 | + break; | |
185 | 185 | default: |
186 | - s->regs[saddr] = val; | |
187 | - break; | |
186 | + s->regs[saddr] = val; | |
187 | + break; | |
188 | 188 | } |
189 | 189 | } |
190 | 190 | |
... | ... | @@ -283,7 +283,7 @@ static void iommu_save(QEMUFile *f, void *opaque) |
283 | 283 | int i; |
284 | 284 | |
285 | 285 | for (i = 0; i < IOMMU_NREGS; i++) |
286 | - qemu_put_be32s(f, &s->regs[i]); | |
286 | + qemu_put_be32s(f, &s->regs[i]); | |
287 | 287 | qemu_put_be64s(f, &s->iostart); |
288 | 288 | } |
289 | 289 | ... | ... |
hw/slavio_intctl.c
... | ... | @@ -100,21 +100,21 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint |
100 | 100 | DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); |
101 | 101 | switch (saddr) { |
102 | 102 | case 1: // clear pending softints |
103 | - if (val & 0x4000) | |
104 | - val |= 80000000; | |
105 | - val &= 0xfffe0000; | |
106 | - s->intreg_pending[cpu] &= ~val; | |
103 | + if (val & 0x4000) | |
104 | + val |= 80000000; | |
105 | + val &= 0xfffe0000; | |
106 | + s->intreg_pending[cpu] &= ~val; | |
107 | 107 | slavio_check_interrupts(s); |
108 | - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); | |
109 | - break; | |
108 | + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); | |
109 | + break; | |
110 | 110 | case 2: // set softint |
111 | - val &= 0xfffe0000; | |
112 | - s->intreg_pending[cpu] |= val; | |
111 | + val &= 0xfffe0000; | |
112 | + s->intreg_pending[cpu] |= val; | |
113 | 113 | slavio_check_interrupts(s); |
114 | - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); | |
115 | - break; | |
114 | + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); | |
115 | + break; | |
116 | 116 | default: |
117 | - break; | |
117 | + break; | |
118 | 118 | } |
119 | 119 | } |
120 | 120 | |
... | ... | @@ -165,27 +165,27 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin |
165 | 165 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
166 | 166 | switch (saddr) { |
167 | 167 | case 2: // clear (enable) |
168 | - // Force clear unused bits | |
169 | - val &= ~0x4fb2007f; | |
170 | - s->intregm_disabled &= ~val; | |
171 | - DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); | |
172 | - slavio_check_interrupts(s); | |
173 | - break; | |
168 | + // Force clear unused bits | |
169 | + val &= ~0x4fb2007f; | |
170 | + s->intregm_disabled &= ~val; | |
171 | + DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); | |
172 | + slavio_check_interrupts(s); | |
173 | + break; | |
174 | 174 | case 3: // set (disable, clear pending) |
175 | - // Force clear unused bits | |
176 | - val &= ~0x4fb2007f; | |
177 | - s->intregm_disabled |= val; | |
178 | - s->intregm_pending &= ~val; | |
175 | + // Force clear unused bits | |
176 | + val &= ~0x4fb2007f; | |
177 | + s->intregm_disabled |= val; | |
178 | + s->intregm_pending &= ~val; | |
179 | 179 | slavio_check_interrupts(s); |
180 | - DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); | |
181 | - break; | |
180 | + DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); | |
181 | + break; | |
182 | 182 | case 4: |
183 | - s->target_cpu = val & (MAX_CPUS - 1); | |
183 | + s->target_cpu = val & (MAX_CPUS - 1); | |
184 | 184 | slavio_check_interrupts(s); |
185 | - DPRINTF("Set master irq cpu %d\n", s->target_cpu); | |
186 | - break; | |
185 | + DPRINTF("Set master irq cpu %d\n", s->target_cpu); | |
186 | + break; | |
187 | 187 | default: |
188 | - break; | |
188 | + break; | |
189 | 189 | } |
190 | 190 | } |
191 | 191 | |
... | ... | @@ -207,7 +207,7 @@ void slavio_pic_info(void *opaque) |
207 | 207 | int i; |
208 | 208 | |
209 | 209 | for (i = 0; i < MAX_CPUS; i++) { |
210 | - term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); | |
210 | + term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); | |
211 | 211 | } |
212 | 212 | term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); |
213 | 213 | } |
... | ... | @@ -310,7 +310,7 @@ static void slavio_intctl_save(QEMUFile *f, void *opaque) |
310 | 310 | int i; |
311 | 311 | |
312 | 312 | for (i = 0; i < MAX_CPUS; i++) { |
313 | - qemu_put_be32s(f, &s->intreg_pending[i]); | |
313 | + qemu_put_be32s(f, &s->intreg_pending[i]); | |
314 | 314 | } |
315 | 315 | qemu_put_be32s(f, &s->intregm_pending); |
316 | 316 | qemu_put_be32s(f, &s->intregm_disabled); |
... | ... | @@ -326,7 +326,7 @@ static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) |
326 | 326 | return -EINVAL; |
327 | 327 | |
328 | 328 | for (i = 0; i < MAX_CPUS; i++) { |
329 | - qemu_get_be32s(f, &s->intreg_pending[i]); | |
329 | + qemu_get_be32s(f, &s->intreg_pending[i]); | |
330 | 330 | } |
331 | 331 | qemu_get_be32s(f, &s->intregm_pending); |
332 | 332 | qemu_get_be32s(f, &s->intregm_disabled); |
... | ... | @@ -341,7 +341,7 @@ static void slavio_intctl_reset(void *opaque) |
341 | 341 | int i; |
342 | 342 | |
343 | 343 | for (i = 0; i < MAX_CPUS; i++) { |
344 | - s->intreg_pending[i] = 0; | |
344 | + s->intreg_pending[i] = 0; | |
345 | 345 | } |
346 | 346 | s->intregm_disabled = ~0xffb2007f; |
347 | 347 | s->intregm_pending = 0; |
... | ... | @@ -363,8 +363,8 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, |
363 | 363 | |
364 | 364 | s->intbit_to_level = intbit_to_level; |
365 | 365 | for (i = 0; i < MAX_CPUS; i++) { |
366 | - slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); | |
367 | - cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, | |
366 | + slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); | |
367 | + cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, | |
368 | 368 | slavio_intctl_io_memory); |
369 | 369 | s->cpu_irqs[i] = parent_irq[i]; |
370 | 370 | } | ... | ... |
hw/slavio_misc.c
... | ... | @@ -76,9 +76,9 @@ void slavio_set_power_fail(void *opaque, int power_failing) |
76 | 76 | |
77 | 77 | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); |
78 | 78 | if (power_failing && (s->config & 0x8)) { |
79 | - s->aux2 |= 0x4; | |
79 | + s->aux2 |= 0x4; | |
80 | 80 | } else { |
81 | - s->aux2 &= ~0x4; | |
81 | + s->aux2 &= ~0x4; | |
82 | 82 | } |
83 | 83 | slavio_misc_update_irq(s); |
84 | 84 | } |
... | ... | @@ -89,44 +89,44 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32 |
89 | 89 | |
90 | 90 | switch (addr & 0xfff0000) { |
91 | 91 | case 0x1800000: |
92 | - MISC_DPRINTF("Write config %2.2x\n", val & 0xff); | |
93 | - s->config = val & 0xff; | |
94 | - slavio_misc_update_irq(s); | |
95 | - break; | |
92 | + MISC_DPRINTF("Write config %2.2x\n", val & 0xff); | |
93 | + s->config = val & 0xff; | |
94 | + slavio_misc_update_irq(s); | |
95 | + break; | |
96 | 96 | case 0x1900000: |
97 | - MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); | |
98 | - s->aux1 = val & 0xff; | |
99 | - break; | |
97 | + MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); | |
98 | + s->aux1 = val & 0xff; | |
99 | + break; | |
100 | 100 | case 0x1910000: |
101 | - val &= 0x3; | |
102 | - MISC_DPRINTF("Write aux2 %2.2x\n", val); | |
103 | - val |= s->aux2 & 0x4; | |
104 | - if (val & 0x2) // Clear Power Fail int | |
105 | - val &= 0x1; | |
106 | - s->aux2 = val; | |
107 | - if (val & 1) | |
108 | - qemu_system_shutdown_request(); | |
109 | - slavio_misc_update_irq(s); | |
110 | - break; | |
101 | + val &= 0x3; | |
102 | + MISC_DPRINTF("Write aux2 %2.2x\n", val); | |
103 | + val |= s->aux2 & 0x4; | |
104 | + if (val & 0x2) // Clear Power Fail int | |
105 | + val &= 0x1; | |
106 | + s->aux2 = val; | |
107 | + if (val & 1) | |
108 | + qemu_system_shutdown_request(); | |
109 | + slavio_misc_update_irq(s); | |
110 | + break; | |
111 | 111 | case 0x1a00000: |
112 | - MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); | |
113 | - s->diag = val & 0xff; | |
114 | - break; | |
112 | + MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); | |
113 | + s->diag = val & 0xff; | |
114 | + break; | |
115 | 115 | case 0x1b00000: |
116 | - MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); | |
117 | - s->mctrl = val & 0xff; | |
118 | - break; | |
116 | + MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); | |
117 | + s->mctrl = val & 0xff; | |
118 | + break; | |
119 | 119 | case 0x1f00000: |
120 | - MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); | |
121 | - if (val & 1) { | |
122 | - s->sysctrl = 0x2; | |
123 | - qemu_system_reset_request(); | |
124 | - } | |
125 | - break; | |
120 | + MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); | |
121 | + if (val & 1) { | |
122 | + s->sysctrl = 0x2; | |
123 | + qemu_system_reset_request(); | |
124 | + } | |
125 | + break; | |
126 | 126 | case 0xa000000: |
127 | - MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); | |
127 | + MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); | |
128 | 128 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
129 | - break; | |
129 | + break; | |
130 | 130 | } |
131 | 131 | } |
132 | 132 | |
... | ... | @@ -137,32 +137,32 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
137 | 137 | |
138 | 138 | switch (addr & 0xfff0000) { |
139 | 139 | case 0x1800000: |
140 | - ret = s->config; | |
141 | - MISC_DPRINTF("Read config %2.2x\n", ret); | |
142 | - break; | |
140 | + ret = s->config; | |
141 | + MISC_DPRINTF("Read config %2.2x\n", ret); | |
142 | + break; | |
143 | 143 | case 0x1900000: |
144 | - ret = s->aux1; | |
145 | - MISC_DPRINTF("Read aux1 %2.2x\n", ret); | |
146 | - break; | |
144 | + ret = s->aux1; | |
145 | + MISC_DPRINTF("Read aux1 %2.2x\n", ret); | |
146 | + break; | |
147 | 147 | case 0x1910000: |
148 | - ret = s->aux2; | |
149 | - MISC_DPRINTF("Read aux2 %2.2x\n", ret); | |
150 | - break; | |
148 | + ret = s->aux2; | |
149 | + MISC_DPRINTF("Read aux2 %2.2x\n", ret); | |
150 | + break; | |
151 | 151 | case 0x1a00000: |
152 | - ret = s->diag; | |
153 | - MISC_DPRINTF("Read diag %2.2x\n", ret); | |
154 | - break; | |
152 | + ret = s->diag; | |
153 | + MISC_DPRINTF("Read diag %2.2x\n", ret); | |
154 | + break; | |
155 | 155 | case 0x1b00000: |
156 | - ret = s->mctrl; | |
157 | - MISC_DPRINTF("Read modem control %2.2x\n", ret); | |
158 | - break; | |
156 | + ret = s->mctrl; | |
157 | + MISC_DPRINTF("Read modem control %2.2x\n", ret); | |
158 | + break; | |
159 | 159 | case 0x1f00000: |
160 | - MISC_DPRINTF("Read system control %2.2x\n", ret); | |
161 | - ret = s->sysctrl; | |
162 | - break; | |
160 | + MISC_DPRINTF("Read system control %2.2x\n", ret); | |
161 | + ret = s->sysctrl; | |
162 | + break; | |
163 | 163 | case 0xa000000: |
164 | - MISC_DPRINTF("Read power management %2.2x\n", ret); | |
165 | - break; | |
164 | + MISC_DPRINTF("Read power management %2.2x\n", ret); | |
165 | + break; | |
166 | 166 | } |
167 | 167 | return ret; |
168 | 168 | } | ... | ... |
hw/slavio_serial.c
... | ... | @@ -139,7 +139,7 @@ static uint32_t get_queue(void *opaque) |
139 | 139 | int val; |
140 | 140 | |
141 | 141 | if (q->count == 0) { |
142 | - return 0; | |
142 | + return 0; | |
143 | 143 | } else { |
144 | 144 | val = q->data[q->rptr]; |
145 | 145 | if (++q->rptr == SERIO_QUEUE_SIZE) |
... | ... | @@ -148,17 +148,17 @@ static uint32_t get_queue(void *opaque) |
148 | 148 | } |
149 | 149 | SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val); |
150 | 150 | if (q->count > 0) |
151 | - serial_receive_byte(s, 0); | |
151 | + serial_receive_byte(s, 0); | |
152 | 152 | return val; |
153 | 153 | } |
154 | 154 | |
155 | 155 | static int slavio_serial_update_irq_chn(ChannelState *s) |
156 | 156 | { |
157 | 157 | if ((s->wregs[1] & 1) && // interrupts enabled |
158 | - (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending | |
159 | - ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) && | |
160 | - s->rxint == 1) || // rx ints enabled, pending | |
161 | - ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p | |
158 | + (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending | |
159 | + ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) && | |
160 | + s->rxint == 1) || // rx ints enabled, pending | |
161 | + ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p | |
162 | 162 | return 1; |
163 | 163 | } |
164 | 164 | return 0; |
... | ... | @@ -181,8 +181,8 @@ static void slavio_serial_reset_chn(ChannelState *s) |
181 | 181 | |
182 | 182 | s->reg = 0; |
183 | 183 | for (i = 0; i < SERIAL_SIZE; i++) { |
184 | - s->rregs[i] = 0; | |
185 | - s->wregs[i] = 0; | |
184 | + s->rregs[i] = 0; | |
185 | + s->wregs[i] = 0; | |
186 | 186 | } |
187 | 187 | s->wregs[4] = 4; |
188 | 188 | s->wregs[9] = 0xc0; |
... | ... | @@ -367,82 +367,82 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint |
367 | 367 | s = &serial->chn[channel]; |
368 | 368 | switch (saddr) { |
369 | 369 | case 0: |
370 | - SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff); | |
371 | - newreg = 0; | |
372 | - switch (s->reg) { | |
373 | - case 0: | |
374 | - newreg = val & 7; | |
375 | - val &= 0x38; | |
376 | - switch (val) { | |
377 | - case 8: | |
378 | - newreg |= 0x8; | |
379 | - break; | |
380 | - case 0x28: | |
370 | + SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff); | |
371 | + newreg = 0; | |
372 | + switch (s->reg) { | |
373 | + case 0: | |
374 | + newreg = val & 7; | |
375 | + val &= 0x38; | |
376 | + switch (val) { | |
377 | + case 8: | |
378 | + newreg |= 0x8; | |
379 | + break; | |
380 | + case 0x28: | |
381 | 381 | clr_txint(s); |
382 | - break; | |
383 | - case 0x38: | |
382 | + break; | |
383 | + case 0x38: | |
384 | 384 | if (s->rxint_under_svc) |
385 | 385 | clr_rxint(s); |
386 | 386 | else if (s->txint_under_svc) |
387 | 387 | clr_txint(s); |
388 | - break; | |
389 | - default: | |
390 | - break; | |
391 | - } | |
392 | - break; | |
388 | + break; | |
389 | + default: | |
390 | + break; | |
391 | + } | |
392 | + break; | |
393 | 393 | case 1 ... 3: |
394 | 394 | case 6 ... 8: |
395 | 395 | case 10 ... 11: |
396 | 396 | case 14 ... 15: |
397 | - s->wregs[s->reg] = val; | |
398 | - break; | |
397 | + s->wregs[s->reg] = val; | |
398 | + break; | |
399 | 399 | case 4: |
400 | 400 | case 5: |
401 | 401 | case 12: |
402 | 402 | case 13: |
403 | - s->wregs[s->reg] = val; | |
403 | + s->wregs[s->reg] = val; | |
404 | 404 | slavio_serial_update_parameters(s); |
405 | - break; | |
406 | - case 9: | |
407 | - switch (val & 0xc0) { | |
408 | - case 0: | |
409 | - default: | |
410 | - break; | |
411 | - case 0x40: | |
412 | - slavio_serial_reset_chn(&serial->chn[1]); | |
413 | - return; | |
414 | - case 0x80: | |
415 | - slavio_serial_reset_chn(&serial->chn[0]); | |
416 | - return; | |
417 | - case 0xc0: | |
418 | - slavio_serial_reset(serial); | |
419 | - return; | |
420 | - } | |
421 | - break; | |
422 | - default: | |
423 | - break; | |
424 | - } | |
425 | - if (s->reg == 0) | |
426 | - s->reg = newreg; | |
427 | - else | |
428 | - s->reg = 0; | |
429 | - break; | |
405 | + break; | |
406 | + case 9: | |
407 | + switch (val & 0xc0) { | |
408 | + case 0: | |
409 | + default: | |
410 | + break; | |
411 | + case 0x40: | |
412 | + slavio_serial_reset_chn(&serial->chn[1]); | |
413 | + return; | |
414 | + case 0x80: | |
415 | + slavio_serial_reset_chn(&serial->chn[0]); | |
416 | + return; | |
417 | + case 0xc0: | |
418 | + slavio_serial_reset(serial); | |
419 | + return; | |
420 | + } | |
421 | + break; | |
422 | + default: | |
423 | + break; | |
424 | + } | |
425 | + if (s->reg == 0) | |
426 | + s->reg = newreg; | |
427 | + else | |
428 | + s->reg = 0; | |
429 | + break; | |
430 | 430 | case 1: |
431 | - SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val); | |
431 | + SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val); | |
432 | 432 | s->tx = val; |
433 | - if (s->wregs[5] & 8) { // tx enabled | |
434 | - if (s->chr) | |
435 | - qemu_chr_write(s->chr, &s->tx, 1); | |
436 | - else if (s->type == kbd) { | |
437 | - handle_kbd_command(s, val); | |
438 | - } | |
439 | - } | |
433 | + if (s->wregs[5] & 8) { // tx enabled | |
434 | + if (s->chr) | |
435 | + qemu_chr_write(s->chr, &s->tx, 1); | |
436 | + else if (s->type == kbd) { | |
437 | + handle_kbd_command(s, val); | |
438 | + } | |
439 | + } | |
440 | 440 | s->rregs[0] |= 4; // Tx buffer empty |
441 | 441 | s->rregs[1] |= 1; // All sent |
442 | 442 | set_txint(s); |
443 | - break; | |
443 | + break; | |
444 | 444 | default: |
445 | - break; | |
445 | + break; | |
446 | 446 | } |
447 | 447 | } |
448 | 448 | |
... | ... | @@ -459,21 +459,21 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr) |
459 | 459 | s = &serial->chn[channel]; |
460 | 460 | switch (saddr) { |
461 | 461 | case 0: |
462 | - SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]); | |
463 | - ret = s->rregs[s->reg]; | |
464 | - s->reg = 0; | |
465 | - return ret; | |
462 | + SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]); | |
463 | + ret = s->rregs[s->reg]; | |
464 | + s->reg = 0; | |
465 | + return ret; | |
466 | 466 | case 1: |
467 | - s->rregs[0] &= ~1; | |
467 | + s->rregs[0] &= ~1; | |
468 | 468 | clr_rxint(s); |
469 | - if (s->type == kbd || s->type == mouse) | |
470 | - ret = get_queue(s); | |
471 | - else | |
472 | - ret = s->rx; | |
473 | - SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret); | |
474 | - return ret; | |
469 | + if (s->type == kbd || s->type == mouse) | |
470 | + ret = get_queue(s); | |
471 | + else | |
472 | + ret = s->rx; | |
473 | + SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret); | |
474 | + return ret; | |
475 | 475 | default: |
476 | - break; | |
476 | + break; | |
477 | 477 | } |
478 | 478 | return 0; |
479 | 479 | } |
... | ... | @@ -484,10 +484,10 @@ static int serial_can_receive(void *opaque) |
484 | 484 | int ret; |
485 | 485 | |
486 | 486 | if (((s->wregs[3] & 1) == 0) // Rx not enabled |
487 | - || ((s->rregs[0] & 1) == 1)) // char already available | |
488 | - ret = 0; | |
487 | + || ((s->rregs[0] & 1) == 1)) // char already available | |
488 | + ret = 0; | |
489 | 489 | else |
490 | - ret = 1; | |
490 | + ret = 1; | |
491 | 491 | //SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret); |
492 | 492 | return ret; |
493 | 493 | } |
... | ... | @@ -584,7 +584,7 @@ static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id) |
584 | 584 | |
585 | 585 | ret = slavio_serial_load_chn(f, &s->chn[0], version_id); |
586 | 586 | if (ret != 0) |
587 | - return ret; | |
587 | + return ret; | |
588 | 588 | ret = slavio_serial_load_chn(f, &s->chn[1], version_id); |
589 | 589 | return ret; |
590 | 590 | |
... | ... | @@ -607,13 +607,13 @@ SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
607 | 607 | s->chn[1].chr = chr2; |
608 | 608 | |
609 | 609 | for (i = 0; i < 2; i++) { |
610 | - s->chn[i].irq = irq; | |
611 | - s->chn[i].chn = 1 - i; | |
612 | - s->chn[i].type = ser; | |
613 | - if (s->chn[i].chr) { | |
614 | - qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, | |
610 | + s->chn[i].irq = irq; | |
611 | + s->chn[i].chn = 1 - i; | |
612 | + s->chn[i].type = ser; | |
613 | + if (s->chn[i].chr) { | |
614 | + qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, | |
615 | 615 | serial_receive1, serial_event, &s->chn[i]); |
616 | - } | |
616 | + } | |
617 | 617 | } |
618 | 618 | s->chn[0].otherchn = &s->chn[1]; |
619 | 619 | s->chn[1].otherchn = &s->chn[0]; |
... | ... | @@ -698,21 +698,21 @@ static void handle_kbd_command(ChannelState *s, int val) |
698 | 698 | switch (val) { |
699 | 699 | case 1: // Reset, return type code |
700 | 700 | clear_queue(s); |
701 | - put_queue(s, 0xff); | |
702 | - put_queue(s, 4); // Type 4 | |
703 | - put_queue(s, 0x7f); | |
704 | - break; | |
701 | + put_queue(s, 0xff); | |
702 | + put_queue(s, 4); // Type 4 | |
703 | + put_queue(s, 0x7f); | |
704 | + break; | |
705 | 705 | case 0xe: // Set leds |
706 | 706 | s->led_mode = 1; |
707 | 707 | break; |
708 | 708 | case 7: // Query layout |
709 | 709 | case 0xf: |
710 | 710 | clear_queue(s); |
711 | - put_queue(s, 0xfe); | |
712 | - put_queue(s, 0); // XXX, layout? | |
713 | - break; | |
711 | + put_queue(s, 0xfe); | |
712 | + put_queue(s, 0); // XXX, layout? | |
713 | + break; | |
714 | 714 | default: |
715 | - break; | |
715 | + break; | |
716 | 716 | } |
717 | 717 | } |
718 | 718 | |
... | ... | @@ -768,9 +768,9 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq) |
768 | 768 | if (!s) |
769 | 769 | return; |
770 | 770 | for (i = 0; i < 2; i++) { |
771 | - s->chn[i].irq = irq; | |
772 | - s->chn[i].chn = 1 - i; | |
773 | - s->chn[i].chr = NULL; | |
771 | + s->chn[i].irq = irq; | |
772 | + s->chn[i].chn = 1 - i; | |
773 | + s->chn[i].chr = NULL; | |
774 | 774 | } |
775 | 775 | s->chn[0].otherchn = &s->chn[1]; |
776 | 776 | s->chn[1].otherchn = &s->chn[0]; | ... | ... |
hw/slavio_timer.c
... | ... | @@ -86,7 +86,7 @@ static void slavio_timer_irq(void *opaque) |
86 | 86 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count); |
87 | 87 | s->reached = 0x80000000; |
88 | 88 | if (s->mode != 1) |
89 | - qemu_irq_raise(s->irq); | |
89 | + qemu_irq_raise(s->irq); | |
90 | 90 | } |
91 | 91 | |
92 | 92 | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
... | ... | @@ -97,34 +97,34 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
97 | 97 | saddr = (addr & TIMER_MAXADDR) >> 2; |
98 | 98 | switch (saddr) { |
99 | 99 | case 0: |
100 | - // read limit (system counter mode) or read most signifying | |
101 | - // part of counter (user mode) | |
102 | - if (s->mode != 1) { | |
103 | - // clear irq | |
100 | + // read limit (system counter mode) or read most signifying | |
101 | + // part of counter (user mode) | |
102 | + if (s->mode != 1) { | |
103 | + // clear irq | |
104 | 104 | qemu_irq_lower(s->irq); |
105 | - s->reached = 0; | |
105 | + s->reached = 0; | |
106 | 106 | ret = s->limit & 0x7fffffff; |
107 | - } | |
108 | - else { | |
109 | - slavio_timer_get_out(s); | |
107 | + } | |
108 | + else { | |
109 | + slavio_timer_get_out(s); | |
110 | 110 | ret = s->counthigh & 0x7fffffff; |
111 | - } | |
111 | + } | |
112 | 112 | break; |
113 | 113 | case 1: |
114 | - // read counter and reached bit (system mode) or read lsbits | |
115 | - // of counter (user mode) | |
116 | - slavio_timer_get_out(s); | |
117 | - if (s->mode != 1) | |
114 | + // read counter and reached bit (system mode) or read lsbits | |
115 | + // of counter (user mode) | |
116 | + slavio_timer_get_out(s); | |
117 | + if (s->mode != 1) | |
118 | 118 | ret = (s->count & 0x7fffffff) | s->reached; |
119 | - else | |
119 | + else | |
120 | 120 | ret = s->count; |
121 | 121 | break; |
122 | 122 | case 3: |
123 | - // read start/stop status | |
123 | + // read start/stop status | |
124 | 124 | ret = s->stopped; |
125 | 125 | break; |
126 | 126 | case 4: |
127 | - // read user/system mode | |
127 | + // read user/system mode | |
128 | 128 | ret = s->slave_mode; |
129 | 129 | break; |
130 | 130 | default: |
... | ... | @@ -161,14 +161,14 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 |
161 | 161 | qemu_irq_lower(s->irq); |
162 | 162 | // fall through |
163 | 163 | case 2: |
164 | - // set limit without resetting counter | |
164 | + // set limit without resetting counter | |
165 | 165 | s->limit = val & 0x7ffffe00ULL; |
166 | 166 | if (!s->limit) |
167 | 167 | s->limit = 0x7ffffe00ULL; |
168 | 168 | ptimer_set_limit(s->timer, s->limit >> 9, reload); |
169 | - break; | |
169 | + break; | |
170 | 170 | case 1: |
171 | - // set user counter limit LSW, reset counter | |
171 | + // set user counter limit LSW, reset counter | |
172 | 172 | if (s->mode == 1) { |
173 | 173 | qemu_irq_lower(s->irq); |
174 | 174 | s->limit &= 0x7fffffff00000000ULL; |
... | ... | @@ -179,20 +179,20 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 |
179 | 179 | } |
180 | 180 | break; |
181 | 181 | case 3: |
182 | - // start/stop user counter | |
183 | - if (s->mode == 1) { | |
184 | - if (val & 1) { | |
182 | + // start/stop user counter | |
183 | + if (s->mode == 1) { | |
184 | + if (val & 1) { | |
185 | 185 | ptimer_stop(s->timer); |
186 | - s->stopped = 1; | |
187 | - } | |
188 | - else { | |
186 | + s->stopped = 1; | |
187 | + } | |
188 | + else { | |
189 | 189 | ptimer_run(s->timer, 0); |
190 | - s->stopped = 0; | |
191 | - } | |
192 | - } | |
193 | - break; | |
190 | + s->stopped = 0; | |
191 | + } | |
192 | + } | |
193 | + break; | |
194 | 194 | case 4: |
195 | - // bit 0: user (1) or system (0) counter mode | |
195 | + // bit 0: user (1) or system (0) counter mode | |
196 | 196 | { |
197 | 197 | unsigned int i; |
198 | 198 | |
... | ... | @@ -211,9 +211,9 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 |
211 | 211 | } |
212 | 212 | s->slave_mode = val & ((1 << MAX_CPUS) - 1); |
213 | 213 | } |
214 | - break; | |
214 | + break; | |
215 | 215 | default: |
216 | - break; | |
216 | + break; | |
217 | 217 | } |
218 | 218 | } |
219 | 219 | |
... | ... | @@ -294,7 +294,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, |
294 | 294 | ptimer_set_period(s->timer, 500ULL); |
295 | 295 | |
296 | 296 | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, |
297 | - slavio_timer_mem_write, s); | |
297 | + slavio_timer_mem_write, s); | |
298 | 298 | if (mode < 2) |
299 | 299 | cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); |
300 | 300 | else | ... | ... |
hw/sun4m.c
... | ... | @@ -52,7 +52,7 @@ |
52 | 52 | #define PROM_SIZE_MAX (512 * 1024) |
53 | 53 | #define PROM_PADDR 0xff0000000ULL |
54 | 54 | #define PROM_VADDR 0xffd00000 |
55 | -#define PROM_FILENAME "openbios-sparc32" | |
55 | +#define PROM_FILENAME "openbios-sparc32" | |
56 | 56 | |
57 | 57 | #define MAX_CPUS 16 |
58 | 58 | #define MAX_PILS 16 |
... | ... | @@ -158,9 +158,9 @@ static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, |
158 | 158 | extern int nographic; |
159 | 159 | |
160 | 160 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
161 | - int boot_device, uint32_t RAM_size, | |
162 | - uint32_t kernel_size, | |
163 | - int width, int height, int depth, | |
161 | + int boot_device, uint32_t RAM_size, | |
162 | + uint32_t kernel_size, | |
163 | + int width, int height, int depth, | |
164 | 164 | int machine_id) |
165 | 165 | { |
166 | 166 | unsigned char tmp = 0; |
... | ... | @@ -179,8 +179,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
179 | 179 | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
180 | 180 | nvram_set_lword(nvram, 0x3C, kernel_size); |
181 | 181 | if (cmdline) { |
182 | - strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); | |
183 | - nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
182 | + strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); | |
183 | + nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
184 | 184 | nvram_set_lword(nvram, 0x44, strlen(cmdline)); |
185 | 185 | } |
186 | 186 | // initrd_image, initrd_size passed differently |
... | ... | @@ -444,13 +444,13 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, |
444 | 444 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
445 | 445 | NULL); |
446 | 446 | if (kernel_size < 0) |
447 | - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
448 | - if (kernel_size < 0) | |
449 | - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
447 | + kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
448 | + if (kernel_size < 0) | |
449 | + kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
450 | 450 | if (kernel_size < 0) { |
451 | 451 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
452 | 452 | kernel_filename); |
453 | - exit(1); | |
453 | + exit(1); | |
454 | 454 | } |
455 | 455 | |
456 | 456 | /* load initrd */ |
... | ... | @@ -464,14 +464,14 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, |
464 | 464 | } |
465 | 465 | } |
466 | 466 | if (initrd_size > 0) { |
467 | - for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
468 | - if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
469 | - == 0x48647253) { // HdrS | |
470 | - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
471 | - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
472 | - break; | |
473 | - } | |
474 | - } | |
467 | + for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
468 | + if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
469 | + == 0x48647253) { // HdrS | |
470 | + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
471 | + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
472 | + break; | |
473 | + } | |
474 | + } | |
475 | 475 | } |
476 | 476 | } |
477 | 477 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
... | ... | @@ -509,8 +509,8 @@ static const struct hwdef hwdefs[] = { |
509 | 509 | .cs_irq = 5, |
510 | 510 | .machine_id = 0x80, |
511 | 511 | .intbit_to_level = { |
512 | - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
513 | - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
512 | + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
513 | + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
514 | 514 | }, |
515 | 515 | }, |
516 | 516 | /* SS-10 */ |
... | ... | @@ -542,8 +542,8 @@ static const struct hwdef hwdefs[] = { |
542 | 542 | .cs_irq = -1, |
543 | 543 | .machine_id = 0x72, |
544 | 544 | .intbit_to_level = { |
545 | - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
546 | - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
545 | + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
546 | + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
547 | 547 | }, |
548 | 548 | }, |
549 | 549 | }; | ... | ... |
hw/sun4u.c
... | ... | @@ -28,12 +28,12 @@ |
28 | 28 | #define CMDLINE_ADDR 0x003ff000 |
29 | 29 | #define INITRD_LOAD_ADDR 0x00300000 |
30 | 30 | #define PROM_SIZE_MAX (512 * 1024) |
31 | -#define PROM_ADDR 0x1fff0000000ULL | |
32 | -#define PROM_VADDR 0x000ffd00000ULL | |
31 | +#define PROM_ADDR 0x1fff0000000ULL | |
32 | +#define PROM_VADDR 0x000ffd00000ULL | |
33 | 33 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
34 | -#define APB_MEM_BASE 0x1ff00000000ULL | |
35 | -#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
36 | -#define PROM_FILENAME "openbios-sparc64" | |
34 | +#define APB_MEM_BASE 0x1ff00000000ULL | |
35 | +#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
36 | +#define PROM_FILENAME "openbios-sparc64" | |
37 | 37 | #define NVRAM_SIZE 0x2000 |
38 | 38 | |
39 | 39 | /* TSC handling */ |
... | ... | @@ -162,10 +162,10 @@ uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
162 | 162 | odd = count & 1; |
163 | 163 | count &= ~1; |
164 | 164 | for (i = 0; i != count; i++) { |
165 | - crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
165 | + crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
166 | 166 | } |
167 | 167 | if (odd) { |
168 | - crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
168 | + crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
169 | 169 | } |
170 | 170 | |
171 | 171 | return crc; |
... | ... | @@ -387,9 +387,9 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
387 | 387 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
388 | 388 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
389 | 389 | if (ret < 0) { |
390 | - fprintf(stderr, "qemu: could not load prom '%s'\n", | |
391 | - buf); | |
392 | - exit(1); | |
390 | + fprintf(stderr, "qemu: could not load prom '%s'\n", | |
391 | + buf); | |
392 | + exit(1); | |
393 | 393 | } |
394 | 394 | |
395 | 395 | kernel_size = 0; |
... | ... | @@ -398,13 +398,13 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
398 | 398 | /* XXX: put correct offset */ |
399 | 399 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
400 | 400 | if (kernel_size < 0) |
401 | - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
402 | - if (kernel_size < 0) | |
403 | - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
401 | + kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
402 | + if (kernel_size < 0) | |
403 | + kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
404 | 404 | if (kernel_size < 0) { |
405 | 405 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
406 | 406 | kernel_filename); |
407 | - exit(1); | |
407 | + exit(1); | |
408 | 408 | } |
409 | 409 | |
410 | 410 | /* load initrd */ |
... | ... | @@ -417,14 +417,14 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
417 | 417 | } |
418 | 418 | } |
419 | 419 | if (initrd_size > 0) { |
420 | - for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
421 | - if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
422 | - == 0x48647253) { // HdrS | |
423 | - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
424 | - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
425 | - break; | |
426 | - } | |
427 | - } | |
420 | + for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
421 | + if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
422 | + == 0x48647253) { // HdrS | |
423 | + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
424 | + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
425 | + break; | |
426 | + } | |
427 | + } | |
428 | 428 | } |
429 | 429 | } |
430 | 430 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
... | ... | @@ -446,7 +446,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, |
446 | 446 | for(i = 0; i < nb_nics; i++) { |
447 | 447 | if (!nd_table[i].model) |
448 | 448 | nd_table[i].model = "ne2k_pci"; |
449 | - pci_nic_init(pci_bus, &nd_table[i], -1); | |
449 | + pci_nic_init(pci_bus, &nd_table[i], -1); | |
450 | 450 | } |
451 | 451 | |
452 | 452 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); | ... | ... |
hw/tcx.c
... | ... | @@ -84,39 +84,39 @@ static void update_palette_entries(TCXState *s, int start, int end) |
84 | 84 | } |
85 | 85 | |
86 | 86 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
87 | - const uint8_t *s, int width) | |
87 | + const uint8_t *s, int width) | |
88 | 88 | { |
89 | 89 | int x; |
90 | 90 | uint8_t val; |
91 | 91 | uint32_t *p = (uint32_t *)d; |
92 | 92 | |
93 | 93 | for(x = 0; x < width; x++) { |
94 | - val = *s++; | |
94 | + val = *s++; | |
95 | 95 | *p++ = s1->palette[val]; |
96 | 96 | } |
97 | 97 | } |
98 | 98 | |
99 | 99 | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
100 | - const uint8_t *s, int width) | |
100 | + const uint8_t *s, int width) | |
101 | 101 | { |
102 | 102 | int x; |
103 | 103 | uint8_t val; |
104 | 104 | uint16_t *p = (uint16_t *)d; |
105 | 105 | |
106 | 106 | for(x = 0; x < width; x++) { |
107 | - val = *s++; | |
107 | + val = *s++; | |
108 | 108 | *p++ = s1->palette[val]; |
109 | 109 | } |
110 | 110 | } |
111 | 111 | |
112 | 112 | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
113 | - const uint8_t *s, int width) | |
113 | + const uint8_t *s, int width) | |
114 | 114 | { |
115 | 115 | int x; |
116 | 116 | uint8_t val; |
117 | 117 | |
118 | 118 | for(x = 0; x < width; x++) { |
119 | - val = *s++; | |
119 | + val = *s++; | |
120 | 120 | *d++ = s1->palette[val]; |
121 | 121 | } |
122 | 122 | } |
... | ... | @@ -183,7 +183,7 @@ static void tcx_update_display(void *opaque) |
183 | 183 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
184 | 184 | |
185 | 185 | if (ts->ds->depth == 0) |
186 | - return; | |
186 | + return; | |
187 | 187 | page = ts->vram_offset; |
188 | 188 | y_start = -1; |
189 | 189 | page_min = 0xffffffff; |
... | ... | @@ -195,55 +195,55 @@ static void tcx_update_display(void *opaque) |
195 | 195 | |
196 | 196 | switch (ts->ds->depth) { |
197 | 197 | case 32: |
198 | - f = tcx_draw_line32; | |
199 | - break; | |
198 | + f = tcx_draw_line32; | |
199 | + break; | |
200 | 200 | case 15: |
201 | 201 | case 16: |
202 | - f = tcx_draw_line16; | |
203 | - break; | |
202 | + f = tcx_draw_line16; | |
203 | + break; | |
204 | 204 | default: |
205 | 205 | case 8: |
206 | - f = tcx_draw_line8; | |
207 | - break; | |
206 | + f = tcx_draw_line8; | |
207 | + break; | |
208 | 208 | case 0: |
209 | - return; | |
209 | + return; | |
210 | 210 | } |
211 | 211 | |
212 | 212 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
213 | - if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { | |
214 | - if (y_start < 0) | |
213 | + if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { | |
214 | + if (y_start < 0) | |
215 | 215 | y_start = y; |
216 | 216 | if (page < page_min) |
217 | 217 | page_min = page; |
218 | 218 | if (page > page_max) |
219 | 219 | page_max = page; |
220 | - f(ts, d, s, ts->width); | |
221 | - d += dd; | |
222 | - s += ds; | |
223 | - f(ts, d, s, ts->width); | |
224 | - d += dd; | |
225 | - s += ds; | |
226 | - f(ts, d, s, ts->width); | |
227 | - d += dd; | |
228 | - s += ds; | |
229 | - f(ts, d, s, ts->width); | |
230 | - d += dd; | |
231 | - s += ds; | |
232 | - } else { | |
220 | + f(ts, d, s, ts->width); | |
221 | + d += dd; | |
222 | + s += ds; | |
223 | + f(ts, d, s, ts->width); | |
224 | + d += dd; | |
225 | + s += ds; | |
226 | + f(ts, d, s, ts->width); | |
227 | + d += dd; | |
228 | + s += ds; | |
229 | + f(ts, d, s, ts->width); | |
230 | + d += dd; | |
231 | + s += ds; | |
232 | + } else { | |
233 | 233 | if (y_start >= 0) { |
234 | 234 | /* flush to display */ |
235 | 235 | dpy_update(ts->ds, 0, y_start, |
236 | 236 | ts->width, y - y_start); |
237 | 237 | y_start = -1; |
238 | 238 | } |
239 | - d += dd * 4; | |
240 | - s += ds * 4; | |
241 | - } | |
239 | + d += dd * 4; | |
240 | + s += ds * 4; | |
241 | + } | |
242 | 242 | } |
243 | 243 | if (y_start >= 0) { |
244 | - /* flush to display */ | |
245 | - dpy_update(ts->ds, 0, y_start, | |
246 | - ts->width, y - y_start); | |
244 | + /* flush to display */ | |
245 | + dpy_update(ts->ds, 0, y_start, | |
246 | + ts->width, y - y_start); | |
247 | 247 | } |
248 | 248 | /* reset modified pages */ |
249 | 249 | if (page_min <= page_max) { |
... | ... | @@ -334,7 +334,7 @@ static void tcx_invalidate_display(void *opaque) |
334 | 334 | int i; |
335 | 335 | |
336 | 336 | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
337 | - cpu_physical_memory_set_dirty(s->vram_offset + i); | |
337 | + cpu_physical_memory_set_dirty(s->vram_offset + i); | |
338 | 338 | } |
339 | 339 | } |
340 | 340 | |
... | ... | @@ -424,32 +424,32 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
424 | 424 | saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
425 | 425 | switch (saddr) { |
426 | 426 | case 0: |
427 | - s->dac_index = val >> 24; | |
428 | - s->dac_state = 0; | |
429 | - break; | |
427 | + s->dac_index = val >> 24; | |
428 | + s->dac_state = 0; | |
429 | + break; | |
430 | 430 | case 1: |
431 | - switch (s->dac_state) { | |
432 | - case 0: | |
433 | - s->r[s->dac_index] = val >> 24; | |
431 | + switch (s->dac_state) { | |
432 | + case 0: | |
433 | + s->r[s->dac_index] = val >> 24; | |
434 | 434 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
435 | - s->dac_state++; | |
436 | - break; | |
437 | - case 1: | |
438 | - s->g[s->dac_index] = val >> 24; | |
435 | + s->dac_state++; | |
436 | + break; | |
437 | + case 1: | |
438 | + s->g[s->dac_index] = val >> 24; | |
439 | 439 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
440 | - s->dac_state++; | |
441 | - break; | |
442 | - case 2: | |
443 | - s->b[s->dac_index] = val >> 24; | |
440 | + s->dac_state++; | |
441 | + break; | |
442 | + case 2: | |
443 | + s->b[s->dac_index] = val >> 24; | |
444 | 444 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
445 | 445 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
446 | - default: | |
447 | - s->dac_state = 0; | |
448 | - break; | |
449 | - } | |
450 | - break; | |
446 | + default: | |
447 | + s->dac_state = 0; | |
448 | + break; | |
449 | + } | |
450 | + break; | |
451 | 451 | default: |
452 | - break; | |
452 | + break; | |
453 | 453 | } |
454 | 454 | return; |
455 | 455 | } | ... | ... |
sparc-dis.c
... | ... | @@ -88,21 +88,21 @@ extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch |
88 | 88 | |
89 | 89 | struct sparc_opcode { |
90 | 90 | const char *name; |
91 | - unsigned long match; /* Bits that must be set. */ | |
92 | - unsigned long lose; /* Bits that must not be set. */ | |
91 | + unsigned long match; /* Bits that must be set. */ | |
92 | + unsigned long lose; /* Bits that must not be set. */ | |
93 | 93 | const char *args; |
94 | 94 | /* This was called "delayed" in versions before the flags. */ |
95 | 95 | char flags; |
96 | - short architecture; /* Bitmask of sparc_opcode_arch_val's. */ | |
96 | + short architecture; /* Bitmask of sparc_opcode_arch_val's. */ | |
97 | 97 | }; |
98 | 98 | |
99 | -#define F_DELAYED 1 /* Delayed branch */ | |
100 | -#define F_ALIAS 2 /* Alias for a "real" instruction */ | |
101 | -#define F_UNBR 4 /* Unconditional branch */ | |
102 | -#define F_CONDBR 8 /* Conditional branch */ | |
103 | -#define F_JSR 16 /* Subroutine call */ | |
104 | -#define F_FLOAT 32 /* Floating point instruction (not a branch) */ | |
105 | -#define F_FBR 64 /* Floating point branch */ | |
99 | +#define F_DELAYED 1 /* Delayed branch */ | |
100 | +#define F_ALIAS 2 /* Alias for a "real" instruction */ | |
101 | +#define F_UNBR 4 /* Unconditional branch */ | |
102 | +#define F_CONDBR 8 /* Conditional branch */ | |
103 | +#define F_JSR 16 /* Subroutine call */ | |
104 | +#define F_FLOAT 32 /* Floating point instruction (not a branch) */ | |
105 | +#define F_FBR 64 /* Floating point branch */ | |
106 | 106 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
107 | 107 | |
108 | 108 | /* |
... | ... | @@ -117,104 +117,104 @@ The args component is a string containing one character for each operand of the |
117 | 117 | instruction. |
118 | 118 | |
119 | 119 | Kinds of operands: |
120 | - # Number used by optimizer. It is ignored. | |
121 | - 1 rs1 register. | |
122 | - 2 rs2 register. | |
123 | - d rd register. | |
124 | - e frs1 floating point register. | |
125 | - v frs1 floating point register (double/even). | |
126 | - V frs1 floating point register (quad/multiple of 4). | |
127 | - f frs2 floating point register. | |
128 | - B frs2 floating point register (double/even). | |
129 | - R frs2 floating point register (quad/multiple of 4). | |
130 | - g frsd floating point register. | |
131 | - H frsd floating point register (double/even). | |
132 | - J frsd floating point register (quad/multiple of 4). | |
133 | - b crs1 coprocessor register | |
134 | - c crs2 coprocessor register | |
135 | - D crsd coprocessor register | |
136 | - m alternate space register (asr) in rd | |
137 | - M alternate space register (asr) in rs1 | |
138 | - h 22 high bits. | |
139 | - X 5 bit unsigned immediate | |
140 | - Y 6 bit unsigned immediate | |
141 | - 3 SIAM mode (3 bits). (v9b) | |
142 | - K MEMBAR mask (7 bits). (v9) | |
143 | - j 10 bit Immediate. (v9) | |
144 | - I 11 bit Immediate. (v9) | |
145 | - i 13 bit Immediate. | |
146 | - n 22 bit immediate. | |
147 | - k 2+14 bit PC relative immediate. (v9) | |
148 | - G 19 bit PC relative immediate. (v9) | |
149 | - l 22 bit PC relative immediate. | |
150 | - L 30 bit PC relative immediate. | |
151 | - a Annul. The annul bit is set. | |
152 | - A Alternate address space. Stored as 8 bits. | |
153 | - C Coprocessor state register. | |
154 | - F floating point state register. | |
155 | - p Processor state register. | |
156 | - N Branch predict clear ",pn" (v9) | |
157 | - T Branch predict set ",pt" (v9) | |
158 | - z %icc. (v9) | |
159 | - Z %xcc. (v9) | |
160 | - q Floating point queue. | |
161 | - r Single register that is both rs1 and rd. | |
162 | - O Single register that is both rs2 and rd. | |
163 | - Q Coprocessor queue. | |
164 | - S Special case. | |
165 | - t Trap base register. | |
166 | - w Window invalid mask register. | |
167 | - y Y register. | |
168 | - u sparclet coprocessor registers in rd position | |
169 | - U sparclet coprocessor registers in rs1 position | |
170 | - E %ccr. (v9) | |
171 | - s %fprs. (v9) | |
172 | - P %pc. (v9) | |
173 | - W %tick. (v9) | |
174 | - o %asi. (v9) | |
175 | - 6 %fcc0. (v9) | |
176 | - 7 %fcc1. (v9) | |
177 | - 8 %fcc2. (v9) | |
178 | - 9 %fcc3. (v9) | |
179 | - ! Privileged Register in rd (v9) | |
180 | - ? Privileged Register in rs1 (v9) | |
181 | - * Prefetch function constant. (v9) | |
182 | - x OPF field (v9 impdep). | |
183 | - 0 32/64 bit immediate for set or setx (v9) insns | |
184 | - _ Ancillary state register in rd (v9a) | |
185 | - / Ancillary state register in rs1 (v9a) | |
120 | + # Number used by optimizer. It is ignored. | |
121 | + 1 rs1 register. | |
122 | + 2 rs2 register. | |
123 | + d rd register. | |
124 | + e frs1 floating point register. | |
125 | + v frs1 floating point register (double/even). | |
126 | + V frs1 floating point register (quad/multiple of 4). | |
127 | + f frs2 floating point register. | |
128 | + B frs2 floating point register (double/even). | |
129 | + R frs2 floating point register (quad/multiple of 4). | |
130 | + g frsd floating point register. | |
131 | + H frsd floating point register (double/even). | |
132 | + J frsd floating point register (quad/multiple of 4). | |
133 | + b crs1 coprocessor register | |
134 | + c crs2 coprocessor register | |
135 | + D crsd coprocessor register | |
136 | + m alternate space register (asr) in rd | |
137 | + M alternate space register (asr) in rs1 | |
138 | + h 22 high bits. | |
139 | + X 5 bit unsigned immediate | |
140 | + Y 6 bit unsigned immediate | |
141 | + 3 SIAM mode (3 bits). (v9b) | |
142 | + K MEMBAR mask (7 bits). (v9) | |
143 | + j 10 bit Immediate. (v9) | |
144 | + I 11 bit Immediate. (v9) | |
145 | + i 13 bit Immediate. | |
146 | + n 22 bit immediate. | |
147 | + k 2+14 bit PC relative immediate. (v9) | |
148 | + G 19 bit PC relative immediate. (v9) | |
149 | + l 22 bit PC relative immediate. | |
150 | + L 30 bit PC relative immediate. | |
151 | + a Annul. The annul bit is set. | |
152 | + A Alternate address space. Stored as 8 bits. | |
153 | + C Coprocessor state register. | |
154 | + F floating point state register. | |
155 | + p Processor state register. | |
156 | + N Branch predict clear ",pn" (v9) | |
157 | + T Branch predict set ",pt" (v9) | |
158 | + z %icc. (v9) | |
159 | + Z %xcc. (v9) | |
160 | + q Floating point queue. | |
161 | + r Single register that is both rs1 and rd. | |
162 | + O Single register that is both rs2 and rd. | |
163 | + Q Coprocessor queue. | |
164 | + S Special case. | |
165 | + t Trap base register. | |
166 | + w Window invalid mask register. | |
167 | + y Y register. | |
168 | + u sparclet coprocessor registers in rd position | |
169 | + U sparclet coprocessor registers in rs1 position | |
170 | + E %ccr. (v9) | |
171 | + s %fprs. (v9) | |
172 | + P %pc. (v9) | |
173 | + W %tick. (v9) | |
174 | + o %asi. (v9) | |
175 | + 6 %fcc0. (v9) | |
176 | + 7 %fcc1. (v9) | |
177 | + 8 %fcc2. (v9) | |
178 | + 9 %fcc3. (v9) | |
179 | + ! Privileged Register in rd (v9) | |
180 | + ? Privileged Register in rs1 (v9) | |
181 | + * Prefetch function constant. (v9) | |
182 | + x OPF field (v9 impdep). | |
183 | + 0 32/64 bit immediate for set or setx (v9) insns | |
184 | + _ Ancillary state register in rd (v9a) | |
185 | + / Ancillary state register in rs1 (v9a) | |
186 | 186 | |
187 | 187 | The following chars are unused: (note: ,[] are used as punctuation) |
188 | 188 | [45] |
189 | 189 | |
190 | 190 | */ |
191 | 191 | |
192 | -#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ | |
193 | -#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ | |
194 | -#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ | |
195 | -#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ | |
196 | -#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ | |
197 | -#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ | |
198 | -#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ | |
199 | -#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ | |
200 | -#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ | |
201 | -#define F1(x) (OP(x)) | |
202 | -#define DISP30(x) ((x)&0x3fffffff) | |
203 | -#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ | |
204 | -#define RS2(x) ((x)&0x1f) /* rs2 field */ | |
205 | -#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ | |
206 | -#define RD(x) (((x)&0x1f) << 25) /* destination register field */ | |
207 | -#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ | |
208 | -#define ASI_RS2(x) (SIMM13(x)) | |
209 | -#define MEMBAR(x) ((x)&0x7f) | |
210 | -#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ | |
211 | - | |
212 | -#define ANNUL (1<<29) | |
213 | -#define BPRED (1<<19) /* v9 */ | |
214 | -#define IMMED F3I(1) | |
215 | -#define RD_G0 RD(~0) | |
216 | -#define RS1_G0 RS1(~0) | |
217 | -#define RS2_G0 RS2(~0) | |
192 | +#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ | |
193 | +#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ | |
194 | +#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ | |
195 | +#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ | |
196 | +#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ | |
197 | +#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ | |
198 | +#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ | |
199 | +#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ | |
200 | +#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ | |
201 | +#define F1(x) (OP(x)) | |
202 | +#define DISP30(x) ((x)&0x3fffffff) | |
203 | +#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ | |
204 | +#define RS2(x) ((x)&0x1f) /* rs2 field */ | |
205 | +#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ | |
206 | +#define RD(x) (((x)&0x1f) << 25) /* destination register field */ | |
207 | +#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ | |
208 | +#define ASI_RS2(x) (SIMM13(x)) | |
209 | +#define MEMBAR(x) ((x)&0x7f) | |
210 | +#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ | |
211 | + | |
212 | +#define ANNUL (1<<29) | |
213 | +#define BPRED (1<<19) /* v9 */ | |
214 | +#define IMMED F3I(1) | |
215 | +#define RD_G0 RD(~0) | |
216 | +#define RS1_G0 RS1(~0) | |
217 | +#define RS2_G0 RS2(~0) | |
218 | 218 | |
219 | 219 | extern const struct sparc_opcode sparc_opcodes[]; |
220 | 220 | extern const int sparc_num_opcodes; |
... | ... | @@ -229,43 +229,43 @@ extern int sparc_encode_sparclet_cpreg PARAMS ((const char *)); |
229 | 229 | extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); |
230 | 230 | |
231 | 231 | /* Some defines to make life easy. */ |
232 | -#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) | |
233 | -#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) | |
234 | -#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) | |
235 | -#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) | |
236 | -#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) | |
237 | -#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) | |
238 | -#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) | |
239 | -#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) | |
232 | +#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) | |
233 | +#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) | |
234 | +#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) | |
235 | +#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) | |
236 | +#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) | |
237 | +#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) | |
238 | +#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) | |
239 | +#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) | |
240 | 240 | |
241 | 241 | /* Bit masks of architectures supporting the insn. */ |
242 | 242 | |
243 | -#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ | |
244 | - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
243 | +#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ | |
244 | + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
245 | 245 | /* v6 insns not supported on the sparclet */ |
246 | -#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ | |
247 | - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
248 | -#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ | |
249 | - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
246 | +#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ | |
247 | + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
248 | +#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ | |
249 | + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | |
250 | 250 | /* Although not all insns are implemented in hardware, sparclite is defined |
251 | 251 | to be a superset of v8. Unimplemented insns trap and are then theoretically |
252 | 252 | implemented in software. |
253 | 253 | It's not clear that the same is true for sparclet, although the docs |
254 | 254 | suggest it is. Rather than complicating things, the sparclet assembler |
255 | 255 | recognizes all v8 insns. */ |
256 | -#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ | |
257 | - | MASK_V9 | MASK_V9A | MASK_V9B) | |
258 | -#define sparclet (MASK_SPARCLET) | |
259 | -#define sparclite (MASK_SPARCLITE) | |
260 | -#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) | |
261 | -#define v9a (MASK_V9A | MASK_V9B) | |
262 | -#define v9b (MASK_V9B) | |
256 | +#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ | |
257 | + | MASK_V9 | MASK_V9A | MASK_V9B) | |
258 | +#define sparclet (MASK_SPARCLET) | |
259 | +#define sparclite (MASK_SPARCLITE) | |
260 | +#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) | |
261 | +#define v9a (MASK_V9A | MASK_V9B) | |
262 | +#define v9b (MASK_V9B) | |
263 | 263 | /* v6 insns not supported by v9 */ |
264 | -#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ | |
265 | - | MASK_SPARCLET | MASK_SPARCLITE) | |
264 | +#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ | |
265 | + | MASK_SPARCLET | MASK_SPARCLITE) | |
266 | 266 | /* v9a instructions which would appear to be aliases to v9's impdep's |
267 | 267 | otherwise */ |
268 | -#define v9notv9a (MASK_V9) | |
268 | +#define v9notv9a (MASK_V9) | |
269 | 269 | |
270 | 270 | /* Table of opcode architectures. |
271 | 271 | The order is defined in opcode/sparc.h. */ |
... | ... | @@ -296,959 +296,959 @@ sparc_opcode_lookup_arch (name) |
296 | 296 | for (p = &sparc_opcode_archs[0]; p->name; ++p) |
297 | 297 | { |
298 | 298 | if (strcmp (name, p->name) == 0) |
299 | - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); | |
299 | + return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); | |
300 | 300 | } |
301 | 301 | |
302 | 302 | return SPARC_OPCODE_ARCH_BAD; |
303 | 303 | } |
304 | 304 | |
305 | 305 | /* Branch condition field. */ |
306 | -#define COND(x) (((x)&0xf)<<25) | |
306 | +#define COND(x) (((x)&0xf)<<25) | |
307 | 307 | |
308 | 308 | /* v9: Move (MOVcc and FMOVcc) condition field. */ |
309 | -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ | |
309 | +#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ | |
310 | 310 | |
311 | 311 | /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ |
312 | -#define RCOND(x) (((x)&0x7)<<10) /* v9 */ | |
313 | - | |
314 | -#define CONDA (COND(0x8)) | |
315 | -#define CONDCC (COND(0xd)) | |
316 | -#define CONDCS (COND(0x5)) | |
317 | -#define CONDE (COND(0x1)) | |
318 | -#define CONDG (COND(0xa)) | |
319 | -#define CONDGE (COND(0xb)) | |
320 | -#define CONDGU (COND(0xc)) | |
321 | -#define CONDL (COND(0x3)) | |
322 | -#define CONDLE (COND(0x2)) | |
323 | -#define CONDLEU (COND(0x4)) | |
324 | -#define CONDN (COND(0x0)) | |
325 | -#define CONDNE (COND(0x9)) | |
326 | -#define CONDNEG (COND(0x6)) | |
327 | -#define CONDPOS (COND(0xe)) | |
328 | -#define CONDVC (COND(0xf)) | |
329 | -#define CONDVS (COND(0x7)) | |
330 | - | |
331 | -#define CONDNZ CONDNE | |
332 | -#define CONDZ CONDE | |
333 | -#define CONDGEU CONDCC | |
334 | -#define CONDLU CONDCS | |
335 | - | |
336 | -#define FCONDA (COND(0x8)) | |
337 | -#define FCONDE (COND(0x9)) | |
338 | -#define FCONDG (COND(0x6)) | |
339 | -#define FCONDGE (COND(0xb)) | |
340 | -#define FCONDL (COND(0x4)) | |
341 | -#define FCONDLE (COND(0xd)) | |
342 | -#define FCONDLG (COND(0x2)) | |
343 | -#define FCONDN (COND(0x0)) | |
344 | -#define FCONDNE (COND(0x1)) | |
345 | -#define FCONDO (COND(0xf)) | |
346 | -#define FCONDU (COND(0x7)) | |
347 | -#define FCONDUE (COND(0xa)) | |
348 | -#define FCONDUG (COND(0x5)) | |
349 | -#define FCONDUGE (COND(0xc)) | |
350 | -#define FCONDUL (COND(0x3)) | |
351 | -#define FCONDULE (COND(0xe)) | |
352 | - | |
353 | -#define FCONDNZ FCONDNE | |
354 | -#define FCONDZ FCONDE | |
355 | - | |
356 | -#define ICC (0) /* v9 */ | |
312 | +#define RCOND(x) (((x)&0x7)<<10) /* v9 */ | |
313 | + | |
314 | +#define CONDA (COND(0x8)) | |
315 | +#define CONDCC (COND(0xd)) | |
316 | +#define CONDCS (COND(0x5)) | |
317 | +#define CONDE (COND(0x1)) | |
318 | +#define CONDG (COND(0xa)) | |
319 | +#define CONDGE (COND(0xb)) | |
320 | +#define CONDGU (COND(0xc)) | |
321 | +#define CONDL (COND(0x3)) | |
322 | +#define CONDLE (COND(0x2)) | |
323 | +#define CONDLEU (COND(0x4)) | |
324 | +#define CONDN (COND(0x0)) | |
325 | +#define CONDNE (COND(0x9)) | |
326 | +#define CONDNEG (COND(0x6)) | |
327 | +#define CONDPOS (COND(0xe)) | |
328 | +#define CONDVC (COND(0xf)) | |
329 | +#define CONDVS (COND(0x7)) | |
330 | + | |
331 | +#define CONDNZ CONDNE | |
332 | +#define CONDZ CONDE | |
333 | +#define CONDGEU CONDCC | |
334 | +#define CONDLU CONDCS | |
335 | + | |
336 | +#define FCONDA (COND(0x8)) | |
337 | +#define FCONDE (COND(0x9)) | |
338 | +#define FCONDG (COND(0x6)) | |
339 | +#define FCONDGE (COND(0xb)) | |
340 | +#define FCONDL (COND(0x4)) | |
341 | +#define FCONDLE (COND(0xd)) | |
342 | +#define FCONDLG (COND(0x2)) | |
343 | +#define FCONDN (COND(0x0)) | |
344 | +#define FCONDNE (COND(0x1)) | |
345 | +#define FCONDO (COND(0xf)) | |
346 | +#define FCONDU (COND(0x7)) | |
347 | +#define FCONDUE (COND(0xa)) | |
348 | +#define FCONDUG (COND(0x5)) | |
349 | +#define FCONDUGE (COND(0xc)) | |
350 | +#define FCONDUL (COND(0x3)) | |
351 | +#define FCONDULE (COND(0xe)) | |
352 | + | |
353 | +#define FCONDNZ FCONDNE | |
354 | +#define FCONDZ FCONDE | |
355 | + | |
356 | +#define ICC (0) /* v9 */ | |
357 | 357 | #define XCC (1<<12) /* v9 */ |
358 | -#define FCC(x) (((x)&0x3)<<11) /* v9 */ | |
359 | -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ | |
358 | +#define FCC(x) (((x)&0x3)<<11) /* v9 */ | |
359 | +#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ | |
360 | 360 | |
361 | 361 | /* The order of the opcodes in the table is significant: |
362 | 362 | |
363 | - * The assembler requires that all instances of the same mnemonic must | |
364 | - be consecutive. If they aren't, the assembler will bomb at runtime. | |
363 | + * The assembler requires that all instances of the same mnemonic must | |
364 | + be consecutive. If they aren't, the assembler will bomb at runtime. | |
365 | 365 | |
366 | - * The disassembler should not care about the order of the opcodes. | |
366 | + * The disassembler should not care about the order of the opcodes. | |
367 | 367 | |
368 | 368 | */ |
369 | 369 | |
370 | 370 | /* Entries for commutative arithmetic operations. */ |
371 | 371 | /* ??? More entries can make use of this. */ |
372 | 372 | #define COMMUTEOP(opcode, op3, arch_mask) \ |
373 | -{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ | |
374 | -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ | |
375 | -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } | |
373 | +{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ | |
374 | +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ | |
375 | +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } | |
376 | 376 | |
377 | 377 | const struct sparc_opcode sparc_opcodes[] = { |
378 | 378 | |
379 | -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, | |
380 | -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ | |
381 | -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, | |
382 | -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, | |
383 | -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
384 | -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ | |
385 | -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, | |
386 | -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ | |
387 | -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, | |
388 | -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, | |
389 | -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, | |
390 | -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ | |
391 | - | |
392 | -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, | |
393 | -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ | |
394 | -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, | |
395 | -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, | |
396 | -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, | |
397 | -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ | |
398 | - | |
399 | -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, | |
400 | -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
401 | -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, | |
402 | -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, | |
403 | -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, | |
404 | -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ | |
405 | -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, | |
406 | -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
407 | -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, | |
408 | -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, | |
409 | -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, | |
410 | -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ | |
379 | +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, | |
380 | +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ | |
381 | +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, | |
382 | +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, | |
383 | +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
384 | +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ | |
385 | +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, | |
386 | +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ | |
387 | +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, | |
388 | +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, | |
389 | +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, | |
390 | +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ | |
391 | + | |
392 | +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, | |
393 | +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ | |
394 | +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, | |
395 | +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, | |
396 | +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, | |
397 | +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ | |
398 | + | |
399 | +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, | |
400 | +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
401 | +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, | |
402 | +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, | |
403 | +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, | |
404 | +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ | |
405 | +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, | |
406 | +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
407 | +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, | |
408 | +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, | |
409 | +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, | |
410 | +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ | |
411 | 411 | |
412 | 412 | /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the |
413 | 413 | 'ld' pseudo-op in v9. */ |
414 | -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, | |
415 | -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ | |
416 | -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, | |
417 | -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, | |
418 | -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, | |
419 | -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ | |
420 | - | |
421 | -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
422 | -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ | |
423 | -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, | |
424 | -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, | |
425 | -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
426 | -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ | |
427 | -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, | |
428 | -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ | |
429 | -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, | |
430 | -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, | |
431 | -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, | |
432 | -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ | |
433 | - | |
434 | -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, | |
435 | -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ | |
436 | -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, | |
437 | -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, | |
438 | -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, | |
439 | -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ | |
440 | - | |
441 | -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, | |
442 | -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ | |
443 | -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, | |
444 | -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, | |
445 | -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, | |
446 | -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ | |
447 | - | |
448 | -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
449 | -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ | |
450 | -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, | |
451 | -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, | |
452 | -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
453 | -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ | |
454 | - | |
455 | -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ | |
456 | -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
457 | -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, | |
458 | -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, | |
459 | -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
460 | -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ | |
461 | - | |
462 | -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
463 | -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ | |
464 | -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, | |
465 | -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, | |
466 | -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
467 | -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ | |
468 | - | |
469 | -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, | |
470 | -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ | |
471 | -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, | |
472 | -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, | |
473 | -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, | |
474 | -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ | |
475 | - | |
476 | -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
477 | -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ | |
478 | -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, | |
479 | -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, | |
480 | -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
481 | -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ | |
482 | - | |
483 | -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
484 | -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ | |
485 | -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, | |
486 | -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, | |
487 | -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
488 | -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ | |
489 | - | |
490 | -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, | |
491 | -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ | |
492 | -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, | |
493 | -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, | |
494 | -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, | |
495 | -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ | |
496 | - | |
497 | -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, | |
498 | -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ | |
499 | -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, | |
500 | -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, | |
501 | -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, | |
502 | -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ | |
503 | - | |
504 | -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, | |
505 | -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ | |
506 | -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, | |
507 | -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, | |
508 | -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
509 | -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
510 | -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, | |
511 | -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ | |
512 | -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, | |
513 | -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, | |
514 | -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, | |
515 | -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ | |
516 | - | |
517 | -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, | |
518 | -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ | |
519 | -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, | |
520 | -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, | |
521 | -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
522 | -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
523 | - | |
524 | -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, | |
525 | -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ | |
526 | -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, | |
527 | -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, | |
528 | -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, | |
529 | -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ | |
530 | - | |
531 | -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, | |
532 | -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ | |
533 | -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, | |
534 | -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, | |
535 | -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, | |
536 | -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ | |
537 | - | |
538 | -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, | |
539 | -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ | |
540 | -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, | |
541 | -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, | |
542 | -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
543 | -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
544 | - | |
545 | -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, | |
546 | -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ | |
547 | -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, | |
548 | -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, | |
549 | -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
550 | -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
551 | - | |
552 | -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, | |
553 | -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ | |
554 | -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, | |
555 | -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, | |
556 | -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
557 | -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
558 | - | |
559 | -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, | |
560 | -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ | |
561 | -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, | |
562 | -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, | |
563 | -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
564 | -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
565 | - | |
566 | -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, | |
567 | -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ | |
568 | -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, | |
569 | -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, | |
570 | -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
571 | -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
572 | - | |
573 | -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, | |
574 | -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ | |
575 | -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, | |
576 | -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, | |
577 | -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
578 | -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
579 | - | |
580 | -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ | |
581 | -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ | |
582 | -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, | |
583 | -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, | |
584 | -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, | |
585 | -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ | |
586 | - | |
587 | -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, | |
588 | -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ | |
589 | -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, | |
590 | -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, | |
591 | -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
592 | -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
593 | - | |
594 | -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
595 | -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ | |
596 | -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, | |
597 | -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, | |
598 | -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
599 | -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
600 | -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, | |
601 | -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ | |
602 | -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, | |
603 | -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, | |
604 | -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, | |
605 | -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
606 | - | |
607 | -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, | |
608 | -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
609 | -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, | |
610 | -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, | |
611 | -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, | |
612 | -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ | |
613 | -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, | |
614 | -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
615 | -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, | |
616 | -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, | |
617 | -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, | |
618 | -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ | |
619 | - | |
620 | -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, | |
621 | -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ | |
622 | -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, | |
623 | -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, | |
624 | -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, | |
625 | -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
626 | - | |
627 | -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
628 | -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
629 | -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
630 | -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
631 | -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
632 | -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
633 | -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
634 | -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
635 | -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
636 | -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
637 | -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
638 | -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
639 | -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
640 | -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
641 | -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
642 | -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
643 | -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
644 | -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
645 | - | |
646 | -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
647 | -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ | |
648 | -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
649 | -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
650 | -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
651 | -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ | |
652 | - | |
653 | -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, | |
654 | -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ | |
655 | -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, | |
656 | -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, | |
657 | -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
658 | -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ | |
659 | - | |
660 | -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, | |
661 | -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ | |
662 | -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, | |
663 | -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, | |
664 | -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, | |
665 | -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ | |
666 | - | |
667 | -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
668 | -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
669 | -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
670 | -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
671 | -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
672 | -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
673 | -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
674 | -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
675 | -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
676 | -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
677 | -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
678 | -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
679 | -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
680 | -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
681 | -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
682 | -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
683 | -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
684 | -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
685 | - | |
686 | -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
687 | -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ | |
688 | -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, | |
689 | -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, | |
690 | -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
691 | -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ | |
692 | - | |
693 | -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
694 | -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ | |
695 | -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
696 | -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
697 | -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
698 | -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ | |
699 | -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
700 | -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ | |
701 | -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
702 | -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
703 | -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
704 | -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ | |
705 | - | |
706 | -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, | |
707 | -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ | |
708 | -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, | |
709 | -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, | |
710 | -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
711 | -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ | |
712 | - | |
713 | -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
714 | -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ | |
715 | -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
716 | -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
717 | -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
718 | -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ | |
719 | -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
720 | -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ | |
721 | -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
722 | -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
723 | -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
724 | -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ | |
725 | - | |
726 | -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
727 | -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ | |
728 | -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, | |
729 | -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, | |
730 | -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
731 | -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ | |
732 | - | |
733 | -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, | |
734 | -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
735 | -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, | |
736 | -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, | |
737 | -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, | |
738 | -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
739 | -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, | |
740 | -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ | |
741 | -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, | |
742 | -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, | |
743 | -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, | |
744 | -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ | |
745 | - | |
746 | -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, | |
747 | -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
748 | -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, | |
749 | -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, | |
750 | -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, | |
751 | -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
752 | -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, | |
753 | -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
754 | -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, | |
755 | -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, | |
756 | -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, | |
757 | -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
758 | - | |
759 | -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
760 | -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ | |
761 | -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
762 | -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
763 | -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
764 | -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ | |
765 | - | |
766 | -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, | |
767 | -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ | |
768 | -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, | |
769 | -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, | |
770 | -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
771 | -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ | |
772 | -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, | |
773 | -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ | |
774 | -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, | |
775 | -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, | |
776 | -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, | |
777 | -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ | |
778 | - | |
779 | -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
780 | -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ | |
781 | -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, | |
782 | -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, | |
783 | -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
784 | -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ | |
785 | - | |
786 | -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
787 | -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ | |
788 | -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
789 | -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
790 | -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
791 | -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ | |
792 | -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
793 | -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ | |
794 | -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
795 | -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
796 | -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
797 | -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ | |
798 | - | |
799 | -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, | |
800 | -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ | |
801 | -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, | |
802 | -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, | |
803 | -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
804 | -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ | |
805 | - | |
806 | -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
807 | -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ | |
808 | -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
809 | -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
810 | -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
811 | -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ | |
812 | -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
813 | -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ | |
814 | -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
815 | -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
816 | -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
817 | -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ | |
818 | - | |
819 | -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, | |
820 | -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ | |
821 | -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, | |
822 | -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, | |
823 | -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, | |
824 | -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ | |
825 | - | |
826 | -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, | |
827 | -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ | |
828 | -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, | |
829 | -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, | |
830 | -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, | |
831 | -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ | |
832 | - | |
833 | -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, | |
834 | -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ | |
835 | -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, | |
836 | -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, | |
837 | -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
838 | -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ | |
839 | - | |
840 | -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, | |
841 | -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ | |
842 | -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, | |
843 | -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, | |
844 | -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, | |
845 | -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ | |
846 | - | |
847 | -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, | |
848 | -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ | |
849 | -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, | |
850 | -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, | |
851 | -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, | |
852 | -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ | |
853 | - | |
854 | -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, | |
855 | -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ | |
856 | -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, | |
857 | -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, | |
858 | -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, | |
859 | -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ | |
860 | - | |
861 | -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, | |
862 | -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ | |
863 | -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, | |
864 | -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, | |
865 | -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
866 | -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ | |
867 | - | |
868 | -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
869 | -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ | |
870 | -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, | |
871 | -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ | |
872 | - | |
873 | -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ | |
874 | -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ | |
875 | -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ | |
876 | -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ | |
877 | -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ | |
878 | -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ | |
879 | -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ | |
880 | - | |
881 | -{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
882 | -{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, | |
883 | -{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, | |
884 | - | |
885 | -{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ | |
414 | +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, | |
415 | +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ | |
416 | +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, | |
417 | +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, | |
418 | +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, | |
419 | +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ | |
420 | + | |
421 | +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
422 | +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ | |
423 | +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, | |
424 | +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, | |
425 | +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
426 | +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ | |
427 | +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, | |
428 | +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ | |
429 | +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, | |
430 | +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, | |
431 | +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, | |
432 | +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ | |
433 | + | |
434 | +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, | |
435 | +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ | |
436 | +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, | |
437 | +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, | |
438 | +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, | |
439 | +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ | |
440 | + | |
441 | +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, | |
442 | +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ | |
443 | +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, | |
444 | +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, | |
445 | +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, | |
446 | +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ | |
447 | + | |
448 | +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
449 | +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ | |
450 | +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, | |
451 | +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, | |
452 | +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
453 | +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ | |
454 | + | |
455 | +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ | |
456 | +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
457 | +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, | |
458 | +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, | |
459 | +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
460 | +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ | |
461 | + | |
462 | +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
463 | +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ | |
464 | +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, | |
465 | +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, | |
466 | +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
467 | +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ | |
468 | + | |
469 | +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, | |
470 | +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ | |
471 | +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, | |
472 | +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, | |
473 | +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, | |
474 | +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ | |
475 | + | |
476 | +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
477 | +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ | |
478 | +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, | |
479 | +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, | |
480 | +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
481 | +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ | |
482 | + | |
483 | +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, | |
484 | +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ | |
485 | +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, | |
486 | +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, | |
487 | +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, | |
488 | +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ | |
489 | + | |
490 | +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, | |
491 | +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ | |
492 | +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, | |
493 | +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, | |
494 | +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, | |
495 | +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ | |
496 | + | |
497 | +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, | |
498 | +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ | |
499 | +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, | |
500 | +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, | |
501 | +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, | |
502 | +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ | |
503 | + | |
504 | +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, | |
505 | +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ | |
506 | +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, | |
507 | +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, | |
508 | +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
509 | +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
510 | +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, | |
511 | +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ | |
512 | +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, | |
513 | +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, | |
514 | +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, | |
515 | +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ | |
516 | + | |
517 | +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, | |
518 | +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ | |
519 | +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, | |
520 | +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, | |
521 | +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
522 | +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
523 | + | |
524 | +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, | |
525 | +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ | |
526 | +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, | |
527 | +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, | |
528 | +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, | |
529 | +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ | |
530 | + | |
531 | +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, | |
532 | +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ | |
533 | +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, | |
534 | +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, | |
535 | +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, | |
536 | +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ | |
537 | + | |
538 | +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, | |
539 | +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ | |
540 | +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, | |
541 | +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, | |
542 | +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
543 | +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
544 | + | |
545 | +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, | |
546 | +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ | |
547 | +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, | |
548 | +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, | |
549 | +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
550 | +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
551 | + | |
552 | +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, | |
553 | +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ | |
554 | +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, | |
555 | +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, | |
556 | +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
557 | +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
558 | + | |
559 | +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, | |
560 | +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ | |
561 | +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, | |
562 | +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, | |
563 | +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
564 | +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
565 | + | |
566 | +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, | |
567 | +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ | |
568 | +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, | |
569 | +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, | |
570 | +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
571 | +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
572 | + | |
573 | +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, | |
574 | +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ | |
575 | +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, | |
576 | +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, | |
577 | +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
578 | +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
579 | + | |
580 | +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ | |
581 | +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ | |
582 | +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, | |
583 | +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, | |
584 | +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, | |
585 | +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ | |
586 | + | |
587 | +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, | |
588 | +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ | |
589 | +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, | |
590 | +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, | |
591 | +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
592 | +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ | |
593 | + | |
594 | +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
595 | +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ | |
596 | +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, | |
597 | +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, | |
598 | +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
599 | +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
600 | +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, | |
601 | +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ | |
602 | +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, | |
603 | +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, | |
604 | +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, | |
605 | +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
606 | + | |
607 | +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, | |
608 | +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
609 | +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, | |
610 | +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, | |
611 | +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, | |
612 | +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ | |
613 | +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, | |
614 | +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
615 | +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, | |
616 | +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, | |
617 | +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, | |
618 | +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ | |
619 | + | |
620 | +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, | |
621 | +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ | |
622 | +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, | |
623 | +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, | |
624 | +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, | |
625 | +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ | |
626 | + | |
627 | +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
628 | +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
629 | +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
630 | +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
631 | +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
632 | +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
633 | +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
634 | +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
635 | +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
636 | +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
637 | +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
638 | +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
639 | +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, | |
640 | +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ | |
641 | +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, | |
642 | +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, | |
643 | +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, | |
644 | +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
645 | + | |
646 | +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
647 | +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ | |
648 | +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
649 | +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
650 | +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
651 | +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ | |
652 | + | |
653 | +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, | |
654 | +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ | |
655 | +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, | |
656 | +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, | |
657 | +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
658 | +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ | |
659 | + | |
660 | +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, | |
661 | +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ | |
662 | +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, | |
663 | +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, | |
664 | +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, | |
665 | +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ | |
666 | + | |
667 | +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
668 | +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
669 | +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
670 | +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
671 | +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
672 | +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
673 | +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
674 | +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
675 | +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
676 | +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
677 | +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
678 | +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
679 | +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, | |
680 | +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ | |
681 | +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
682 | +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
683 | +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
684 | +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ | |
685 | + | |
686 | +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
687 | +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ | |
688 | +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, | |
689 | +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, | |
690 | +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
691 | +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ | |
692 | + | |
693 | +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
694 | +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ | |
695 | +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
696 | +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
697 | +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
698 | +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ | |
699 | +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
700 | +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ | |
701 | +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
702 | +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
703 | +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
704 | +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ | |
705 | + | |
706 | +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, | |
707 | +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ | |
708 | +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, | |
709 | +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, | |
710 | +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
711 | +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ | |
712 | + | |
713 | +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
714 | +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ | |
715 | +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
716 | +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
717 | +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
718 | +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ | |
719 | +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
720 | +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ | |
721 | +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
722 | +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
723 | +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
724 | +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ | |
725 | + | |
726 | +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
727 | +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ | |
728 | +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, | |
729 | +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, | |
730 | +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
731 | +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ | |
732 | + | |
733 | +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, | |
734 | +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
735 | +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, | |
736 | +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, | |
737 | +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, | |
738 | +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
739 | +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, | |
740 | +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ | |
741 | +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, | |
742 | +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, | |
743 | +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, | |
744 | +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ | |
745 | + | |
746 | +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, | |
747 | +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
748 | +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, | |
749 | +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, | |
750 | +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, | |
751 | +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
752 | +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, | |
753 | +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
754 | +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, | |
755 | +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, | |
756 | +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, | |
757 | +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ | |
758 | + | |
759 | +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
760 | +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ | |
761 | +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
762 | +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
763 | +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
764 | +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ | |
765 | + | |
766 | +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, | |
767 | +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ | |
768 | +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, | |
769 | +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, | |
770 | +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
771 | +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ | |
772 | +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, | |
773 | +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ | |
774 | +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, | |
775 | +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, | |
776 | +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, | |
777 | +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ | |
778 | + | |
779 | +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, | |
780 | +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ | |
781 | +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, | |
782 | +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, | |
783 | +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, | |
784 | +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ | |
785 | + | |
786 | +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
787 | +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ | |
788 | +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
789 | +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
790 | +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
791 | +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ | |
792 | +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, | |
793 | +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ | |
794 | +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, | |
795 | +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, | |
796 | +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, | |
797 | +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ | |
798 | + | |
799 | +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, | |
800 | +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ | |
801 | +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, | |
802 | +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, | |
803 | +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
804 | +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ | |
805 | + | |
806 | +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
807 | +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ | |
808 | +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
809 | +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
810 | +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
811 | +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ | |
812 | +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, | |
813 | +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ | |
814 | +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, | |
815 | +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, | |
816 | +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, | |
817 | +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ | |
818 | + | |
819 | +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, | |
820 | +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ | |
821 | +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, | |
822 | +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, | |
823 | +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, | |
824 | +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ | |
825 | + | |
826 | +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, | |
827 | +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ | |
828 | +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, | |
829 | +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, | |
830 | +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, | |
831 | +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ | |
832 | + | |
833 | +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, | |
834 | +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ | |
835 | +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, | |
836 | +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, | |
837 | +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, | |
838 | +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ | |
839 | + | |
840 | +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, | |
841 | +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ | |
842 | +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, | |
843 | +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, | |
844 | +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, | |
845 | +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ | |
846 | + | |
847 | +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, | |
848 | +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ | |
849 | +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, | |
850 | +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, | |
851 | +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, | |
852 | +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ | |
853 | + | |
854 | +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, | |
855 | +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ | |
856 | +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, | |
857 | +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, | |
858 | +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, | |
859 | +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ | |
860 | + | |
861 | +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, | |
862 | +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ | |
863 | +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, | |
864 | +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, | |
865 | +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, | |
866 | +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ | |
867 | + | |
868 | +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
869 | +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ | |
870 | +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, | |
871 | +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ | |
872 | + | |
873 | +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ | |
874 | +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ | |
875 | +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ | |
876 | +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ | |
877 | +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ | |
878 | +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ | |
879 | +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ | |
880 | + | |
881 | +{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
882 | +{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, | |
883 | +{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, | |
884 | + | |
885 | +{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ | |
886 | 886 | { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ |
887 | 887 | |
888 | -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, | |
889 | -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ | |
890 | -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ | |
891 | -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ | |
892 | -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, | |
893 | -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, | |
894 | - | |
895 | -{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
896 | -{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
897 | -{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
898 | -{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
899 | -{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, | |
900 | - | |
901 | -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, | |
902 | -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ | |
903 | -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ | |
904 | -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ | |
905 | -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, | |
906 | -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, | |
888 | +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, | |
889 | +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ | |
890 | +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ | |
891 | +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ | |
892 | +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, | |
893 | +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, | |
894 | + | |
895 | +{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
896 | +{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
897 | +{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
898 | +{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, | |
899 | +{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, | |
900 | + | |
901 | +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, | |
902 | +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ | |
903 | +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ | |
904 | +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ | |
905 | +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, | |
906 | +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, | |
907 | 907 | |
908 | 908 | /* IFLUSH was renamed to FLUSH in v8. */ |
909 | -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, | |
910 | -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ | |
911 | -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ | |
912 | -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, | |
913 | -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, | |
914 | -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, | |
915 | - | |
916 | -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, | |
917 | -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ | |
918 | -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ | |
919 | -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ | |
920 | -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, | |
921 | -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, | |
922 | - | |
923 | -{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, | |
924 | - | |
925 | -{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, | |
926 | -{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, | |
927 | - | |
928 | -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, | |
929 | -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ | |
930 | -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, | |
931 | -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, | |
932 | -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, | |
933 | -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ | |
934 | -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, | |
935 | -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ | |
936 | -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, | |
937 | -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, | |
938 | -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, | |
939 | -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ | |
940 | - | |
941 | -{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
942 | -{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
943 | -{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
944 | -{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
945 | -{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
946 | -{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
947 | - | |
948 | -{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
949 | -{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
950 | -{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
951 | -{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
952 | -{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
953 | -{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
954 | - | |
955 | -{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
956 | -{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, | |
957 | - | |
958 | -{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, | |
959 | -{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, | |
960 | - | |
961 | -{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, | |
962 | -{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, | |
963 | - | |
964 | -{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, | |
965 | -{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, | |
966 | - | |
967 | -{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ | |
968 | -{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ | |
969 | -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
970 | -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ | |
971 | -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
972 | -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
973 | -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
974 | -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ | |
975 | - | |
976 | -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
977 | -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ | |
978 | -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
979 | -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
980 | -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
981 | -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ | |
982 | - | |
983 | -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
984 | -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ | |
985 | -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
986 | -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
987 | -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
988 | -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ | |
989 | - | |
990 | -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, | |
991 | -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ | |
992 | -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, | |
993 | -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, | |
994 | -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, | |
995 | -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ | |
996 | - | |
997 | -{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
998 | -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, | |
999 | -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, | |
909 | +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, | |
910 | +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ | |
911 | +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ | |
912 | +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, | |
913 | +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, | |
914 | +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, | |
915 | + | |
916 | +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, | |
917 | +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ | |
918 | +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ | |
919 | +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ | |
920 | +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, | |
921 | +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, | |
922 | + | |
923 | +{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, | |
924 | + | |
925 | +{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, | |
926 | +{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, | |
927 | + | |
928 | +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, | |
929 | +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ | |
930 | +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, | |
931 | +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, | |
932 | +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, | |
933 | +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ | |
934 | +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, | |
935 | +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ | |
936 | +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, | |
937 | +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, | |
938 | +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, | |
939 | +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ | |
940 | + | |
941 | +{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
942 | +{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
943 | +{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
944 | +{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
945 | +{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, | |
946 | +{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, | |
947 | + | |
948 | +{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
949 | +{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
950 | +{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
951 | +{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
952 | +{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, | |
953 | +{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, | |
954 | + | |
955 | +{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
956 | +{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, | |
957 | + | |
958 | +{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, | |
959 | +{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, | |
960 | + | |
961 | +{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, | |
962 | +{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, | |
963 | + | |
964 | +{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, | |
965 | +{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, | |
966 | + | |
967 | +{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ | |
968 | +{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ | |
969 | +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
970 | +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ | |
971 | +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
972 | +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
973 | +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
974 | +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ | |
975 | + | |
976 | +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
977 | +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ | |
978 | +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
979 | +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
980 | +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
981 | +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ | |
982 | + | |
983 | +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, | |
984 | +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ | |
985 | +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, | |
986 | +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, | |
987 | +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, | |
988 | +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ | |
989 | + | |
990 | +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, | |
991 | +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ | |
992 | +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, | |
993 | +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, | |
994 | +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, | |
995 | +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ | |
996 | + | |
997 | +{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
998 | +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, | |
999 | +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, | |
1000 | 1000 | |
1001 | 1001 | /* This is not a commutative instruction. */ |
1002 | -{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1003 | -{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, | |
1002 | +{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1003 | +{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, | |
1004 | 1004 | |
1005 | 1005 | /* This is not a commutative instruction. */ |
1006 | -{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1007 | -{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, | |
1008 | - | |
1009 | -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ | |
1010 | -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ | |
1011 | -{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ | |
1012 | - | |
1013 | -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ | |
1014 | -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ | |
1015 | -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ | |
1016 | -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ | |
1017 | -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ | |
1018 | -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ | |
1019 | -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ | |
1020 | -{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ | |
1021 | -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ | |
1022 | -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ | |
1023 | -{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ | |
1024 | -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ | |
1025 | -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ | |
1026 | -{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ | |
1027 | -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
1028 | - | |
1029 | -{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ | |
1030 | -{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ | |
1031 | -{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ | |
1032 | -{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ | |
1033 | -{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ | |
1034 | -{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ | |
1035 | - | |
1036 | -{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ | |
1037 | -{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ | |
1038 | -{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ | |
1039 | -{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ | |
1040 | -{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ | |
1041 | -{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ | |
1042 | -{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ | |
1043 | -{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ | |
1044 | -{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ | |
1045 | -{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ | |
1046 | -{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ | |
1047 | -{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ | |
1048 | -{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ | |
1049 | -{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ | |
1050 | -{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ | |
1051 | -{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ | |
1052 | -{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ | |
1053 | -{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ | |
1054 | -{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ | |
1055 | -{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ | |
1056 | - | |
1057 | -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ | |
1058 | -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ | |
1059 | -{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ | |
1060 | -{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ | |
1061 | -{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ | |
1062 | - | |
1063 | -{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ | |
1064 | -{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ | |
1065 | -{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ | |
1066 | -{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ | |
1067 | -{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ | |
1068 | - | |
1069 | -{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ | |
1070 | -{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ | |
1071 | -{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ | |
1072 | -{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ | |
1073 | -{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ | |
1074 | -{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ | |
1075 | -{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ | |
1076 | -{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ | |
1077 | - | |
1078 | -{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ | |
1079 | -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ | |
1080 | -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ | |
1081 | -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ | |
1082 | -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ | |
1083 | -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ | |
1006 | +{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1007 | +{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, | |
1008 | + | |
1009 | +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ | |
1010 | +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ | |
1011 | +{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ | |
1012 | + | |
1013 | +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ | |
1014 | +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ | |
1015 | +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ | |
1016 | +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ | |
1017 | +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ | |
1018 | +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ | |
1019 | +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ | |
1020 | +{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ | |
1021 | +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ | |
1022 | +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ | |
1023 | +{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ | |
1024 | +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ | |
1025 | +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ | |
1026 | +{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ | |
1027 | +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
1028 | + | |
1029 | +{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ | |
1030 | +{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ | |
1031 | +{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ | |
1032 | +{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ | |
1033 | +{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ | |
1034 | +{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ | |
1035 | + | |
1036 | +{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ | |
1037 | +{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ | |
1038 | +{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ | |
1039 | +{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ | |
1040 | +{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ | |
1041 | +{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ | |
1042 | +{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ | |
1043 | +{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ | |
1044 | +{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ | |
1045 | +{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ | |
1046 | +{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ | |
1047 | +{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ | |
1048 | +{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ | |
1049 | +{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ | |
1050 | +{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ | |
1051 | +{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ | |
1052 | +{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ | |
1053 | +{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ | |
1054 | +{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ | |
1055 | +{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ | |
1056 | + | |
1057 | +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ | |
1058 | +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ | |
1059 | +{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ | |
1060 | +{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ | |
1061 | +{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ | |
1062 | + | |
1063 | +{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ | |
1064 | +{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ | |
1065 | +{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ | |
1066 | +{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ | |
1067 | +{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ | |
1068 | + | |
1069 | +{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ | |
1070 | +{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ | |
1071 | +{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ | |
1072 | +{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ | |
1073 | +{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ | |
1074 | +{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ | |
1075 | +{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ | |
1076 | +{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ | |
1077 | + | |
1078 | +{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ | |
1079 | +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ | |
1080 | +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ | |
1081 | +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ | |
1082 | +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ | |
1083 | +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ | |
1084 | 1084 | |
1085 | 1085 | /* ??? This group seems wrong. A three operand move? */ |
1086 | -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ | |
1087 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ | |
1088 | -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ | |
1089 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ | |
1090 | -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ | |
1091 | -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ | |
1092 | -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ | |
1093 | -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ | |
1094 | -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ | |
1095 | -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ | |
1096 | - | |
1097 | -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ | |
1098 | -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ | |
1099 | -{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ | |
1100 | -{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ | |
1101 | -{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ | |
1102 | - | |
1103 | -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ | |
1104 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ | |
1105 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ | |
1106 | -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ | |
1107 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ | |
1108 | -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ | |
1109 | -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ | |
1110 | -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ | |
1111 | -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ | |
1112 | -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ | |
1113 | -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ | |
1114 | -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ | |
1115 | -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
1116 | -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ | |
1117 | -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ | |
1118 | - | |
1119 | -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ | |
1120 | -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ | |
1121 | -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ | |
1122 | -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ | |
1123 | - | |
1124 | -{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1125 | -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, | |
1126 | -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, | |
1127 | - | |
1128 | -{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ | |
1129 | -{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ | |
1086 | +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ | |
1087 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ | |
1088 | +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ | |
1089 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ | |
1090 | +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ | |
1091 | +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ | |
1092 | +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ | |
1093 | +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ | |
1094 | +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ | |
1095 | +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ | |
1096 | + | |
1097 | +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ | |
1098 | +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ | |
1099 | +{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ | |
1100 | +{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ | |
1101 | +{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ | |
1102 | + | |
1103 | +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ | |
1104 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ | |
1105 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ | |
1106 | +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ | |
1107 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ | |
1108 | +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ | |
1109 | +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ | |
1110 | +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ | |
1111 | +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ | |
1112 | +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ | |
1113 | +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ | |
1114 | +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ | |
1115 | +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
1116 | +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ | |
1117 | +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ | |
1118 | + | |
1119 | +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ | |
1120 | +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ | |
1121 | +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ | |
1122 | +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ | |
1123 | + | |
1124 | +{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1125 | +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, | |
1126 | +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, | |
1127 | + | |
1128 | +{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ | |
1129 | +{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ | |
1130 | 1130 | |
1131 | 1131 | /* This is not a commutative instruction. */ |
1132 | -{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1133 | -{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, | |
1132 | +{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1133 | +{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, | |
1134 | 1134 | |
1135 | 1135 | /* This is not a commutative instruction. */ |
1136 | -{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1137 | -{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, | |
1138 | - | |
1139 | -{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ | |
1140 | -{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ | |
1141 | - | |
1142 | -{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ | |
1143 | -{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ | |
1144 | - | |
1145 | -{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1146 | -{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, | |
1147 | - | |
1148 | -{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1149 | -{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, | |
1150 | - | |
1151 | -{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1152 | -{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, | |
1153 | -{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1154 | -{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, | |
1155 | - | |
1156 | -{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1157 | -{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, | |
1158 | -{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1159 | -{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, | |
1160 | - | |
1161 | -{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1162 | -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, | |
1163 | -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, | |
1164 | - | |
1165 | -{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1166 | -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, | |
1167 | -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, | |
1168 | - | |
1169 | -{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ | |
1170 | -{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ | |
1171 | -{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ | |
1172 | -{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ | |
1173 | -{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ | |
1174 | -{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ | |
1175 | -{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ | |
1176 | -{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ | |
1177 | - | |
1178 | -{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ | |
1179 | -{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ | |
1180 | - | |
1181 | -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ | |
1182 | -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ | |
1183 | - | |
1184 | -{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1185 | -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, | |
1186 | -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, | |
1187 | -{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1188 | -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, | |
1189 | -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, | |
1190 | - | |
1191 | -{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1192 | -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, | |
1193 | -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, | |
1194 | -{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1195 | -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, | |
1196 | -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, | |
1197 | - | |
1198 | -{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1199 | -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, | |
1200 | -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, | |
1201 | -{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1202 | -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, | |
1203 | -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, | |
1204 | - | |
1205 | -{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1206 | -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, | |
1207 | -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, | |
1208 | -{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1209 | -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, | |
1210 | -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, | |
1211 | -{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1212 | -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, | |
1213 | -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, | |
1214 | -{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1215 | -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, | |
1216 | -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, | |
1217 | -{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1218 | -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, | |
1219 | -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, | |
1220 | -{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1221 | -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, | |
1222 | -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, | |
1223 | -{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1224 | -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, | |
1225 | -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, | |
1226 | -{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1227 | -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, | |
1228 | -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, | |
1229 | - | |
1230 | -{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1231 | -{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, | |
1232 | -{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1233 | -{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, | |
1234 | -{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1235 | -{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, | |
1236 | - | |
1237 | -{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, | |
1238 | -{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, | |
1239 | - | |
1240 | -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ | |
1241 | -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, | |
1242 | -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ | |
1243 | -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, | |
1244 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ | |
1245 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, | |
1246 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ | |
1247 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, | |
1248 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ | |
1249 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, | |
1250 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ | |
1251 | -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, | |
1136 | +{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1137 | +{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, | |
1138 | + | |
1139 | +{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ | |
1140 | +{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ | |
1141 | + | |
1142 | +{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ | |
1143 | +{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ | |
1144 | + | |
1145 | +{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1146 | +{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, | |
1147 | + | |
1148 | +{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1149 | +{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, | |
1150 | + | |
1151 | +{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1152 | +{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, | |
1153 | +{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1154 | +{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, | |
1155 | + | |
1156 | +{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1157 | +{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, | |
1158 | +{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1159 | +{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, | |
1160 | + | |
1161 | +{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1162 | +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, | |
1163 | +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, | |
1164 | + | |
1165 | +{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1166 | +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, | |
1167 | +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, | |
1168 | + | |
1169 | +{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ | |
1170 | +{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ | |
1171 | +{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ | |
1172 | +{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ | |
1173 | +{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ | |
1174 | +{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ | |
1175 | +{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ | |
1176 | +{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ | |
1177 | + | |
1178 | +{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ | |
1179 | +{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ | |
1180 | + | |
1181 | +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ | |
1182 | +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ | |
1183 | + | |
1184 | +{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1185 | +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, | |
1186 | +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, | |
1187 | +{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1188 | +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, | |
1189 | +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, | |
1190 | + | |
1191 | +{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1192 | +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, | |
1193 | +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, | |
1194 | +{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1195 | +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, | |
1196 | +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, | |
1197 | + | |
1198 | +{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, | |
1199 | +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, | |
1200 | +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, | |
1201 | +{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1202 | +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, | |
1203 | +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, | |
1204 | + | |
1205 | +{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1206 | +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, | |
1207 | +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, | |
1208 | +{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1209 | +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, | |
1210 | +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, | |
1211 | +{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1212 | +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, | |
1213 | +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, | |
1214 | +{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1215 | +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, | |
1216 | +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, | |
1217 | +{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1218 | +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, | |
1219 | +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, | |
1220 | +{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1221 | +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, | |
1222 | +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, | |
1223 | +{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1224 | +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, | |
1225 | +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, | |
1226 | +{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, | |
1227 | +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, | |
1228 | +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, | |
1229 | + | |
1230 | +{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1231 | +{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, | |
1232 | +{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1233 | +{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, | |
1234 | +{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, | |
1235 | +{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, | |
1236 | + | |
1237 | +{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, | |
1238 | +{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, | |
1239 | + | |
1240 | +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ | |
1241 | +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, | |
1242 | +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ | |
1243 | +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, | |
1244 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ | |
1245 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, | |
1246 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ | |
1247 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, | |
1248 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ | |
1249 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, | |
1250 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ | |
1251 | +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, | |
1252 | 1252 | |
1253 | 1253 | |
1254 | 1254 | /* Conditional instructions. |
... | ... | @@ -1278,18 +1278,18 @@ const struct sparc_opcode sparc_opcodes[] = { |
1278 | 1278 | |
1279 | 1279 | /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ |
1280 | 1280 | #define tr(opcode, mask, lose, flags) \ |
1281 | - { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ | |
1282 | - { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ | |
1283 | - { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ | |
1284 | - { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ | |
1285 | - { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ | |
1286 | - { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ | |
1287 | - { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ | |
1288 | - { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ | |
1289 | - { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ | |
1290 | - { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ | |
1291 | - { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ | |
1292 | - { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ | |
1281 | + { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ | |
1282 | + { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ | |
1283 | + { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ | |
1284 | + { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ | |
1285 | + { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ | |
1286 | + { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ | |
1287 | + { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ | |
1288 | + { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ | |
1289 | + { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ | |
1290 | + { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ | |
1291 | + { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ | |
1292 | + { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ | |
1293 | 1293 | |
1294 | 1294 | /* v9: We must put `brx' before `br', to ensure that we never match something |
1295 | 1295 | v9: against an expression unless it is an expression. Otherwise, we end |
... | ... | @@ -1305,32 +1305,32 @@ const struct sparc_opcode sparc_opcodes[] = { |
1305 | 1305 | /* Define all the conditions, all the branches, all the traps. */ |
1306 | 1306 | |
1307 | 1307 | /* Standard branch, trap mnemonics */ |
1308 | -cond ("b", "ta", CONDA, F_UNBR), | |
1308 | +cond ("b", "ta", CONDA, F_UNBR), | |
1309 | 1309 | /* Alternative form (just for assembly, not for disassembly) */ |
1310 | -cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), | |
1311 | - | |
1312 | -cond ("bcc", "tcc", CONDCC, F_CONDBR), | |
1313 | -cond ("bcs", "tcs", CONDCS, F_CONDBR), | |
1314 | -cond ("be", "te", CONDE, F_CONDBR), | |
1315 | -cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), | |
1316 | -cond ("bg", "tg", CONDG, F_CONDBR), | |
1317 | -cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), | |
1318 | -cond ("bge", "tge", CONDGE, F_CONDBR), | |
1319 | -cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ | |
1320 | -cond ("bgu", "tgu", CONDGU, F_CONDBR), | |
1321 | -cond ("bl", "tl", CONDL, F_CONDBR), | |
1322 | -cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), | |
1323 | -cond ("ble", "tle", CONDLE, F_CONDBR), | |
1324 | -cond ("bleu", "tleu", CONDLEU, F_CONDBR), | |
1325 | -cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ | |
1326 | -cond ("bn", "tn", CONDN, F_CONDBR), | |
1327 | -cond ("bne", "tne", CONDNE, F_CONDBR), | |
1328 | -cond ("bneg", "tneg", CONDNEG, F_CONDBR), | |
1329 | -cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ | |
1330 | -cond ("bpos", "tpos", CONDPOS, F_CONDBR), | |
1331 | -cond ("bvc", "tvc", CONDVC, F_CONDBR), | |
1332 | -cond ("bvs", "tvs", CONDVS, F_CONDBR), | |
1333 | -cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ | |
1310 | +cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), | |
1311 | + | |
1312 | +cond ("bcc", "tcc", CONDCC, F_CONDBR), | |
1313 | +cond ("bcs", "tcs", CONDCS, F_CONDBR), | |
1314 | +cond ("be", "te", CONDE, F_CONDBR), | |
1315 | +cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), | |
1316 | +cond ("bg", "tg", CONDG, F_CONDBR), | |
1317 | +cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), | |
1318 | +cond ("bge", "tge", CONDGE, F_CONDBR), | |
1319 | +cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ | |
1320 | +cond ("bgu", "tgu", CONDGU, F_CONDBR), | |
1321 | +cond ("bl", "tl", CONDL, F_CONDBR), | |
1322 | +cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), | |
1323 | +cond ("ble", "tle", CONDLE, F_CONDBR), | |
1324 | +cond ("bleu", "tleu", CONDLEU, F_CONDBR), | |
1325 | +cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ | |
1326 | +cond ("bn", "tn", CONDN, F_CONDBR), | |
1327 | +cond ("bne", "tne", CONDNE, F_CONDBR), | |
1328 | +cond ("bneg", "tneg", CONDNEG, F_CONDBR), | |
1329 | +cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ | |
1330 | +cond ("bpos", "tpos", CONDPOS, F_CONDBR), | |
1331 | +cond ("bvc", "tvc", CONDVC, F_CONDBR), | |
1332 | +cond ("bvs", "tvs", CONDVS, F_CONDBR), | |
1333 | +cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ | |
1334 | 1334 | |
1335 | 1335 | #undef cond |
1336 | 1336 | #undef br |
... | ... | @@ -1436,42 +1436,42 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1436 | 1436 | movfcc (opcode, fcond, flags), /* v9 */ \ |
1437 | 1437 | movicc (opcode, cond, flags) /* v9 */ |
1438 | 1438 | |
1439 | -/* v9 */ movcc ("mova", CONDA, FCONDA, 0), | |
1440 | -/* v9 */ movicc ("movcc", CONDCC, 0), | |
1441 | -/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), | |
1442 | -/* v9 */ movicc ("movcs", CONDCS, 0), | |
1443 | -/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), | |
1444 | -/* v9 */ movcc ("move", CONDE, FCONDE, 0), | |
1445 | -/* v9 */ movcc ("movg", CONDG, FCONDG, 0), | |
1446 | -/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), | |
1447 | -/* v9 */ movicc ("movgu", CONDGU, 0), | |
1448 | -/* v9 */ movcc ("movl", CONDL, FCONDL, 0), | |
1449 | -/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), | |
1450 | -/* v9 */ movicc ("movleu", CONDLEU, 0), | |
1451 | -/* v9 */ movfcc ("movlg", FCONDLG, 0), | |
1452 | -/* v9 */ movcc ("movn", CONDN, FCONDN, 0), | |
1453 | -/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), | |
1454 | -/* v9 */ movicc ("movneg", CONDNEG, 0), | |
1455 | -/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), | |
1456 | -/* v9 */ movfcc ("movo", FCONDO, 0), | |
1457 | -/* v9 */ movicc ("movpos", CONDPOS, 0), | |
1458 | -/* v9 */ movfcc ("movu", FCONDU, 0), | |
1459 | -/* v9 */ movfcc ("movue", FCONDUE, 0), | |
1460 | -/* v9 */ movfcc ("movug", FCONDUG, 0), | |
1461 | -/* v9 */ movfcc ("movuge", FCONDUGE, 0), | |
1462 | -/* v9 */ movfcc ("movul", FCONDUL, 0), | |
1463 | -/* v9 */ movfcc ("movule", FCONDULE, 0), | |
1464 | -/* v9 */ movicc ("movvc", CONDVC, 0), | |
1465 | -/* v9 */ movicc ("movvs", CONDVS, 0), | |
1466 | -/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), | |
1439 | +/* v9 */ movcc ("mova", CONDA, FCONDA, 0), | |
1440 | +/* v9 */ movicc ("movcc", CONDCC, 0), | |
1441 | +/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), | |
1442 | +/* v9 */ movicc ("movcs", CONDCS, 0), | |
1443 | +/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), | |
1444 | +/* v9 */ movcc ("move", CONDE, FCONDE, 0), | |
1445 | +/* v9 */ movcc ("movg", CONDG, FCONDG, 0), | |
1446 | +/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), | |
1447 | +/* v9 */ movicc ("movgu", CONDGU, 0), | |
1448 | +/* v9 */ movcc ("movl", CONDL, FCONDL, 0), | |
1449 | +/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), | |
1450 | +/* v9 */ movicc ("movleu", CONDLEU, 0), | |
1451 | +/* v9 */ movfcc ("movlg", FCONDLG, 0), | |
1452 | +/* v9 */ movcc ("movn", CONDN, FCONDN, 0), | |
1453 | +/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), | |
1454 | +/* v9 */ movicc ("movneg", CONDNEG, 0), | |
1455 | +/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), | |
1456 | +/* v9 */ movfcc ("movo", FCONDO, 0), | |
1457 | +/* v9 */ movicc ("movpos", CONDPOS, 0), | |
1458 | +/* v9 */ movfcc ("movu", FCONDU, 0), | |
1459 | +/* v9 */ movfcc ("movue", FCONDUE, 0), | |
1460 | +/* v9 */ movfcc ("movug", FCONDUG, 0), | |
1461 | +/* v9 */ movfcc ("movuge", FCONDUGE, 0), | |
1462 | +/* v9 */ movfcc ("movul", FCONDUL, 0), | |
1463 | +/* v9 */ movfcc ("movule", FCONDULE, 0), | |
1464 | +/* v9 */ movicc ("movvc", CONDVC, 0), | |
1465 | +/* v9 */ movicc ("movvs", CONDVS, 0), | |
1466 | +/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), | |
1467 | 1467 | |
1468 | 1468 | #undef movicc /* v9 */ |
1469 | 1469 | #undef movfcc /* v9 */ |
1470 | 1470 | #undef movcc /* v9 */ |
1471 | 1471 | |
1472 | -#define FM_SF 1 /* v9 - values for fpsize */ | |
1473 | -#define FM_DF 2 /* v9 */ | |
1474 | -#define FM_QF 3 /* v9 */ | |
1472 | +#define FM_SF 1 /* v9 - values for fpsize */ | |
1473 | +#define FM_DF 2 /* v9 */ | |
1474 | +#define FM_QF 3 /* v9 */ | |
1475 | 1475 | |
1476 | 1476 | #define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \ |
1477 | 1477 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \ |
... | ... | @@ -1492,90 +1492,90 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1492 | 1492 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \ |
1493 | 1493 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 } |
1494 | 1494 | |
1495 | -/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), | |
1496 | -/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), | |
1497 | -/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), | |
1498 | -/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), | |
1499 | -/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), | |
1500 | -/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), | |
1501 | -/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), | |
1502 | -/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), | |
1503 | -/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), | |
1504 | -/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), | |
1505 | -/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), | |
1506 | -/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), | |
1507 | -/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), | |
1508 | -/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), | |
1509 | -/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), | |
1510 | -/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), | |
1511 | -/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), | |
1512 | -/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), | |
1513 | -/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), | |
1514 | -/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), | |
1515 | -/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), | |
1516 | -/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), | |
1517 | -/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), | |
1518 | -/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), | |
1519 | -/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), | |
1520 | -/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), | |
1521 | -/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), | |
1522 | -/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), | |
1523 | -/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), | |
1524 | -/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), | |
1525 | -/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), | |
1526 | -/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), | |
1527 | -/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), | |
1528 | -/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), | |
1529 | -/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), | |
1530 | -/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), | |
1531 | -/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), | |
1532 | -/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), | |
1533 | -/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), | |
1534 | -/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), | |
1535 | -/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), | |
1536 | -/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), | |
1537 | -/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), | |
1538 | -/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), | |
1539 | -/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), | |
1540 | -/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), | |
1541 | -/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), | |
1542 | -/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), | |
1543 | -/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), | |
1544 | -/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), | |
1545 | -/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), | |
1546 | -/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), | |
1547 | -/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), | |
1548 | -/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), | |
1549 | -/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), | |
1550 | -/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), | |
1551 | -/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), | |
1552 | -/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), | |
1553 | -/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), | |
1554 | -/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), | |
1555 | -/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), | |
1556 | -/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), | |
1557 | -/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), | |
1558 | -/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), | |
1559 | -/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), | |
1560 | -/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), | |
1561 | -/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), | |
1562 | -/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), | |
1563 | -/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), | |
1564 | -/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), | |
1565 | -/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), | |
1566 | -/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), | |
1567 | -/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), | |
1568 | -/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), | |
1569 | -/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), | |
1570 | -/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), | |
1571 | -/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), | |
1572 | -/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), | |
1573 | -/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), | |
1574 | -/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), | |
1575 | -/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), | |
1576 | -/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), | |
1577 | -/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), | |
1578 | -/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), | |
1495 | +/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), | |
1496 | +/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), | |
1497 | +/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), | |
1498 | +/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), | |
1499 | +/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), | |
1500 | +/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), | |
1501 | +/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), | |
1502 | +/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), | |
1503 | +/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), | |
1504 | +/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), | |
1505 | +/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), | |
1506 | +/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), | |
1507 | +/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), | |
1508 | +/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), | |
1509 | +/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), | |
1510 | +/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), | |
1511 | +/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), | |
1512 | +/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), | |
1513 | +/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), | |
1514 | +/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), | |
1515 | +/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), | |
1516 | +/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), | |
1517 | +/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), | |
1518 | +/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), | |
1519 | +/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), | |
1520 | +/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), | |
1521 | +/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), | |
1522 | +/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), | |
1523 | +/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), | |
1524 | +/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), | |
1525 | +/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), | |
1526 | +/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), | |
1527 | +/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), | |
1528 | +/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), | |
1529 | +/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), | |
1530 | +/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), | |
1531 | +/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), | |
1532 | +/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), | |
1533 | +/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), | |
1534 | +/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), | |
1535 | +/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), | |
1536 | +/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), | |
1537 | +/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), | |
1538 | +/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), | |
1539 | +/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), | |
1540 | +/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), | |
1541 | +/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), | |
1542 | +/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), | |
1543 | +/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), | |
1544 | +/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), | |
1545 | +/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), | |
1546 | +/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), | |
1547 | +/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), | |
1548 | +/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), | |
1549 | +/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), | |
1550 | +/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), | |
1551 | +/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), | |
1552 | +/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), | |
1553 | +/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), | |
1554 | +/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), | |
1555 | +/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), | |
1556 | +/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), | |
1557 | +/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), | |
1558 | +/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), | |
1559 | +/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), | |
1560 | +/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), | |
1561 | +/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), | |
1562 | +/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), | |
1563 | +/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), | |
1564 | +/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), | |
1565 | +/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), | |
1566 | +/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), | |
1567 | +/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), | |
1568 | +/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), | |
1569 | +/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), | |
1570 | +/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), | |
1571 | +/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), | |
1572 | +/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), | |
1573 | +/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), | |
1574 | +/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), | |
1575 | +/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), | |
1576 | +/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), | |
1577 | +/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), | |
1578 | +/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), | |
1579 | 1579 | |
1580 | 1580 | #undef fmovicc /* v9 */ |
1581 | 1581 | #undef fmovfcc /* v9 */ |
... | ... | @@ -1641,19 +1641,19 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1641 | 1641 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) |
1642 | 1642 | |
1643 | 1643 | CONDFC ("fb", "cb", 0x8, F_UNBR), |
1644 | -CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), | |
1645 | -CONDFC ("fbe", "cb0", 0x9, F_CONDBR), | |
1644 | +CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), | |
1645 | +CONDFC ("fbe", "cb0", 0x9, F_CONDBR), | |
1646 | 1646 | CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), |
1647 | -CONDFC ("fbg", "cb2", 0x6, F_CONDBR), | |
1647 | +CONDFC ("fbg", "cb2", 0x6, F_CONDBR), | |
1648 | 1648 | CONDFC ("fbge", "cb02", 0xb, F_CONDBR), |
1649 | -CONDFC ("fbl", "cb1", 0x4, F_CONDBR), | |
1649 | +CONDFC ("fbl", "cb1", 0x4, F_CONDBR), | |
1650 | 1650 | CONDFC ("fble", "cb01", 0xd, F_CONDBR), |
1651 | 1651 | CONDFC ("fblg", "cb12", 0x2, F_CONDBR), |
1652 | -CONDFCL ("fbn", "cbn", 0x0, F_UNBR), | |
1652 | +CONDFCL ("fbn", "cbn", 0x0, F_UNBR), | |
1653 | 1653 | CONDFC ("fbne", "cb123", 0x1, F_CONDBR), |
1654 | 1654 | CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), |
1655 | -CONDFC ("fbo", "cb012", 0xf, F_CONDBR), | |
1656 | -CONDFC ("fbu", "cb3", 0x7, F_CONDBR), | |
1655 | +CONDFC ("fbo", "cb012", 0xf, F_CONDBR), | |
1656 | +CONDFC ("fbu", "cb3", 0x7, F_CONDBR), | |
1657 | 1657 | CONDFC ("fbue", "cb03", 0xa, F_CONDBR), |
1658 | 1658 | CONDFC ("fbug", "cb23", 0x5, F_CONDBR), |
1659 | 1659 | CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), |
... | ... | @@ -1665,167 +1665,167 @@ CONDFC ("fbule", "cb013", 0xe, F_CONDBR), |
1665 | 1665 | #undef CONDF |
1666 | 1666 | #undef CBR |
1667 | 1667 | #undef FBR |
1668 | -#undef FBRX /* v9 */ | |
1668 | +#undef FBRX /* v9 */ | |
1669 | 1669 | |
1670 | -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ | |
1671 | -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ | |
1672 | -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ | |
1673 | -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ | |
1674 | -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ | |
1675 | -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ | |
1670 | +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ | |
1671 | +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ | |
1672 | +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ | |
1673 | +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ | |
1674 | +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ | |
1675 | +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ | |
1676 | 1676 | |
1677 | -{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ | |
1677 | +{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ | |
1678 | 1678 | |
1679 | -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, | |
1680 | -{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, | |
1681 | -{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, | |
1682 | -{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, | |
1679 | +{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, | |
1680 | +{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, | |
1681 | +{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, | |
1682 | +{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, | |
1683 | 1683 | |
1684 | -{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, | |
1684 | +{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, | |
1685 | 1685 | |
1686 | -{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1687 | -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, | |
1688 | -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, | |
1689 | -{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1690 | -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, | |
1691 | -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, | |
1686 | +{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1687 | +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, | |
1688 | +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, | |
1689 | +{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1690 | +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, | |
1691 | +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, | |
1692 | 1692 | |
1693 | -{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1694 | -{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, | |
1695 | -{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1696 | -{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, | |
1693 | +{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1694 | +{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, | |
1695 | +{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1696 | +{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, | |
1697 | 1697 | |
1698 | -{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, | |
1699 | -{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, | |
1698 | +{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, | |
1699 | +{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, | |
1700 | 1700 | |
1701 | 1701 | /* This *is* a commutative instruction. */ |
1702 | -{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1703 | -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, | |
1704 | -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, | |
1702 | +{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1703 | +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, | |
1704 | +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, | |
1705 | 1705 | /* This *is* a commutative instruction. */ |
1706 | -{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1707 | -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, | |
1708 | -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, | |
1709 | -{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1710 | -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, | |
1711 | -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, | |
1712 | -{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1713 | -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, | |
1714 | -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, | |
1715 | - | |
1716 | -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ | |
1717 | -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ | |
1718 | - | |
1719 | -{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ | |
1720 | -{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ | |
1706 | +{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1707 | +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, | |
1708 | +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, | |
1709 | +{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1710 | +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, | |
1711 | +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, | |
1712 | +{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, | |
1713 | +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, | |
1714 | +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, | |
1715 | + | |
1716 | +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ | |
1717 | +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ | |
1718 | + | |
1719 | +{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ | |
1720 | +{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ | |
1721 | 1721 | |
1722 | 1722 | /* FPop1 and FPop2 are not instructions. Don't accept them. */ |
1723 | 1723 | |
1724 | -{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, | |
1725 | -{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1726 | -{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, | |
1727 | - | |
1728 | -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, | |
1729 | -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, | |
1730 | -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, | |
1731 | - | |
1732 | -{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, | |
1733 | -{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1734 | -{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, | |
1735 | - | |
1736 | -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, | |
1737 | -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, | |
1738 | -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, | |
1739 | - | |
1740 | -{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, | |
1741 | -{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, | |
1742 | -{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, | |
1743 | -{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, | |
1744 | -{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, | |
1745 | -{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, | |
1746 | - | |
1747 | -{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, | |
1748 | -{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, | |
1749 | -{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1750 | -{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, | |
1751 | -{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, | |
1752 | -{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, | |
1753 | -{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1754 | -{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, | |
1755 | - | |
1756 | -{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, | |
1757 | -{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, | |
1758 | -{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, | |
1759 | - | |
1760 | -{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, | |
1761 | -{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, | |
1762 | -{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, | |
1763 | -{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, | |
1764 | - | |
1765 | -{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1766 | -{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1767 | -{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1768 | -{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1769 | -{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1770 | -{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1771 | -{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1772 | -{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1773 | -{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1774 | -{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1775 | -{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1776 | -{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1777 | - | |
1778 | -{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, | |
1779 | -{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, | |
1780 | -{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1781 | -{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, | |
1782 | -{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, | |
1783 | -{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, | |
1784 | -{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1785 | -{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, | |
1786 | - | |
1787 | -#define CMPFCC(x) (((x)&0x3)<<25) | |
1788 | - | |
1789 | -{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, | |
1790 | -{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, | |
1791 | -{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, | |
1792 | -{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, | |
1793 | -{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, | |
1794 | -{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, | |
1795 | -{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, | |
1796 | -{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, | |
1797 | -{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, | |
1798 | -{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, | |
1799 | -{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, | |
1800 | -{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, | |
1801 | -{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, | |
1802 | -{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, | |
1803 | -{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, | |
1804 | -{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, | |
1805 | -{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, | |
1806 | -{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, | |
1807 | -{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, | |
1808 | -{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, | |
1809 | -{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, | |
1810 | -{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1811 | -{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1812 | -{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1813 | -{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1814 | -{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, | |
1815 | -{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1816 | -{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1817 | -{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1818 | -{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1819 | -{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, | |
1820 | -{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, | |
1821 | -{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, | |
1822 | -{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, | |
1823 | -{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, | |
1824 | -{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, | |
1825 | -{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, | |
1826 | -{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, | |
1827 | -{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, | |
1828 | -{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, | |
1724 | +{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, | |
1725 | +{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1726 | +{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, | |
1727 | + | |
1728 | +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, | |
1729 | +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, | |
1730 | +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, | |
1731 | + | |
1732 | +{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, | |
1733 | +{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1734 | +{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, | |
1735 | + | |
1736 | +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, | |
1737 | +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, | |
1738 | +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, | |
1739 | + | |
1740 | +{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, | |
1741 | +{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, | |
1742 | +{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, | |
1743 | +{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, | |
1744 | +{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, | |
1745 | +{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, | |
1746 | + | |
1747 | +{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, | |
1748 | +{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, | |
1749 | +{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1750 | +{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, | |
1751 | +{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, | |
1752 | +{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, | |
1753 | +{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1754 | +{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, | |
1755 | + | |
1756 | +{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, | |
1757 | +{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, | |
1758 | +{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, | |
1759 | + | |
1760 | +{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, | |
1761 | +{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, | |
1762 | +{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, | |
1763 | +{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, | |
1764 | + | |
1765 | +{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1766 | +{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1767 | +{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1768 | +{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1769 | +{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1770 | +{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1771 | +{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1772 | +{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1773 | +{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, | |
1774 | +{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, | |
1775 | +{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, | |
1776 | +{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, | |
1777 | + | |
1778 | +{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, | |
1779 | +{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, | |
1780 | +{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1781 | +{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, | |
1782 | +{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, | |
1783 | +{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, | |
1784 | +{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, | |
1785 | +{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, | |
1786 | + | |
1787 | +#define CMPFCC(x) (((x)&0x3)<<25) | |
1788 | + | |
1789 | +{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, | |
1790 | +{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, | |
1791 | +{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, | |
1792 | +{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, | |
1793 | +{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, | |
1794 | +{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, | |
1795 | +{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, | |
1796 | +{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, | |
1797 | +{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, | |
1798 | +{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, | |
1799 | +{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, | |
1800 | +{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, | |
1801 | +{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, | |
1802 | +{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, | |
1803 | +{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, | |
1804 | +{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, | |
1805 | +{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, | |
1806 | +{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, | |
1807 | +{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, | |
1808 | +{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, | |
1809 | +{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, | |
1810 | +{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1811 | +{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1812 | +{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1813 | +{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1814 | +{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, | |
1815 | +{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1816 | +{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1817 | +{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1818 | +{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, | |
1819 | +{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, | |
1820 | +{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, | |
1821 | +{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, | |
1822 | +{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, | |
1823 | +{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, | |
1824 | +{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, | |
1825 | +{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, | |
1826 | +{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, | |
1827 | +{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, | |
1828 | +{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, | |
1829 | 1829 | |
1830 | 1830 | /* These Extended FPop (FIFO) instructions are new in the Fujitsu |
1831 | 1831 | MB86934, replacing the CPop instructions from v6 and later |
... | ... | @@ -1835,30 +1835,30 @@ CONDFC ("fbule", "cb013", 0xe, F_CONDBR), |
1835 | 1835 | #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } |
1836 | 1836 | #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } |
1837 | 1837 | |
1838 | -EFPOP1_2 ("efitod", 0x0c8, "f,H"), | |
1839 | -EFPOP1_2 ("efitos", 0x0c4, "f,g"), | |
1840 | -EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), | |
1841 | -EFPOP1_2 ("efstoi", 0x0d1, "f,g"), | |
1842 | -EFPOP1_2 ("efstod", 0x0c9, "f,H"), | |
1843 | -EFPOP1_2 ("efdtos", 0x0c6, "B,g"), | |
1844 | -EFPOP1_2 ("efmovs", 0x001, "f,g"), | |
1845 | -EFPOP1_2 ("efnegs", 0x005, "f,g"), | |
1846 | -EFPOP1_2 ("efabss", 0x009, "f,g"), | |
1847 | -EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), | |
1848 | -EFPOP1_2 ("efsqrts", 0x029, "f,g"), | |
1849 | -EFPOP1_3 ("efaddd", 0x042, "v,B,H"), | |
1850 | -EFPOP1_3 ("efadds", 0x041, "e,f,g"), | |
1851 | -EFPOP1_3 ("efsubd", 0x046, "v,B,H"), | |
1852 | -EFPOP1_3 ("efsubs", 0x045, "e,f,g"), | |
1853 | -EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), | |
1854 | -EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), | |
1855 | -EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), | |
1856 | -EFPOP1_3 ("efmuls", 0x049, "e,f,g"), | |
1857 | -EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), | |
1858 | -EFPOP2_2 ("efcmpd", 0x052, "v,B"), | |
1859 | -EFPOP2_2 ("efcmped", 0x056, "v,B"), | |
1860 | -EFPOP2_2 ("efcmps", 0x051, "e,f"), | |
1861 | -EFPOP2_2 ("efcmpes", 0x055, "e,f"), | |
1838 | +EFPOP1_2 ("efitod", 0x0c8, "f,H"), | |
1839 | +EFPOP1_2 ("efitos", 0x0c4, "f,g"), | |
1840 | +EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), | |
1841 | +EFPOP1_2 ("efstoi", 0x0d1, "f,g"), | |
1842 | +EFPOP1_2 ("efstod", 0x0c9, "f,H"), | |
1843 | +EFPOP1_2 ("efdtos", 0x0c6, "B,g"), | |
1844 | +EFPOP1_2 ("efmovs", 0x001, "f,g"), | |
1845 | +EFPOP1_2 ("efnegs", 0x005, "f,g"), | |
1846 | +EFPOP1_2 ("efabss", 0x009, "f,g"), | |
1847 | +EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), | |
1848 | +EFPOP1_2 ("efsqrts", 0x029, "f,g"), | |
1849 | +EFPOP1_3 ("efaddd", 0x042, "v,B,H"), | |
1850 | +EFPOP1_3 ("efadds", 0x041, "e,f,g"), | |
1851 | +EFPOP1_3 ("efsubd", 0x046, "v,B,H"), | |
1852 | +EFPOP1_3 ("efsubs", 0x045, "e,f,g"), | |
1853 | +EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), | |
1854 | +EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), | |
1855 | +EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), | |
1856 | +EFPOP1_3 ("efmuls", 0x049, "e,f,g"), | |
1857 | +EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), | |
1858 | +EFPOP2_2 ("efcmpd", 0x052, "v,B"), | |
1859 | +EFPOP2_2 ("efcmped", 0x056, "v,B"), | |
1860 | +EFPOP2_2 ("efcmps", 0x051, "e,f"), | |
1861 | +EFPOP2_2 ("efcmpes", 0x055, "e,f"), | |
1862 | 1862 | |
1863 | 1863 | #undef EFPOP1_2 |
1864 | 1864 | #undef EFPOP1_3 |
... | ... | @@ -1866,8 +1866,8 @@ EFPOP2_2 ("efcmpes", 0x055, "e,f"), |
1866 | 1866 | |
1867 | 1867 | /* These are marked F_ALIAS, so that they won't conflict with sparclite insns |
1868 | 1868 | present. Otherwise, the F_ALIAS flag is ignored. */ |
1869 | -{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, | |
1870 | -{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, | |
1869 | +{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, | |
1870 | +{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, | |
1871 | 1871 | |
1872 | 1872 | /* sparclet specific insns */ |
1873 | 1873 | |
... | ... | @@ -1878,20 +1878,20 @@ COMMUTEOP ("smacd", 0x2f, sparclet), |
1878 | 1878 | COMMUTEOP ("umuld", 0x09, sparclet), |
1879 | 1879 | COMMUTEOP ("smuld", 0x0d, sparclet), |
1880 | 1880 | |
1881 | -{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, | |
1882 | -{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, | |
1881 | +{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, | |
1882 | +{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, | |
1883 | 1883 | |
1884 | 1884 | /* The manual isn't completely accurate on these insns. The `rs2' field is |
1885 | 1885 | treated as being 6 bits to account for 6 bit immediates to cpush. It is |
1886 | 1886 | assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ |
1887 | 1887 | #define BIT5 (1<<5) |
1888 | -{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, | |
1889 | -{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, | |
1890 | -{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, | |
1891 | -{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, | |
1892 | -{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, | |
1893 | -{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, | |
1894 | -{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, | |
1888 | +{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, | |
1889 | +{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, | |
1890 | +{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, | |
1891 | +{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, | |
1892 | +{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, | |
1893 | +{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, | |
1894 | +{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, | |
1895 | 1895 | #undef BIT5 |
1896 | 1896 | |
1897 | 1897 | /* sparclet coprocessor branch insns */ |
... | ... | @@ -1923,108 +1923,108 @@ SLCBCC("cbnefr", 15), |
1923 | 1923 | #undef SLCBCC2 |
1924 | 1924 | #undef SLCBCC |
1925 | 1925 | |
1926 | -{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, | |
1927 | -{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, | |
1928 | -{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, | |
1929 | -{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, | |
1926 | +{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, | |
1927 | +{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, | |
1928 | +{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, | |
1929 | +{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, | |
1930 | 1930 | |
1931 | 1931 | /* v9 synthetic insns */ |
1932 | -{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ | |
1933 | -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ | |
1934 | -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ | |
1935 | -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ | |
1936 | -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ | |
1937 | -{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ | |
1938 | -{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ | |
1939 | -{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ | |
1940 | -{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ | |
1932 | +{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ | |
1933 | +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ | |
1934 | +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ | |
1935 | +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ | |
1936 | +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ | |
1937 | +{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ | |
1938 | +{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ | |
1939 | +{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ | |
1940 | +{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ | |
1941 | 1941 | |
1942 | 1942 | /* Ultrasparc extensions */ |
1943 | -{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, | |
1943 | +{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, | |
1944 | 1944 | |
1945 | 1945 | /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ |
1946 | -{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, | |
1947 | -{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, | |
1948 | -{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, | |
1949 | -{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, | |
1950 | -{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, | |
1951 | -{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, | |
1952 | -{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, | |
1953 | -{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, | |
1954 | - | |
1955 | -{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, | |
1956 | -{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, | |
1957 | -{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, | |
1958 | -{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, | |
1959 | -{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, | |
1946 | +{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, | |
1947 | +{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, | |
1948 | +{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, | |
1949 | +{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, | |
1950 | +{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, | |
1951 | +{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, | |
1952 | +{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, | |
1953 | +{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, | |
1954 | + | |
1955 | +{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, | |
1956 | +{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, | |
1957 | +{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, | |
1958 | +{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, | |
1959 | +{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, | |
1960 | 1960 | |
1961 | 1961 | /* Note that the mixing of 32/64 bit regs is intentional. */ |
1962 | -{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, | |
1963 | -{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, | |
1964 | -{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, | |
1965 | -{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, | |
1966 | -{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, | |
1967 | -{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, | |
1968 | -{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, | |
1969 | - | |
1970 | -{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, | |
1971 | -{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, | |
1972 | -{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, | |
1973 | - | |
1974 | -{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, | |
1975 | -{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, | |
1976 | -{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, | |
1977 | -{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, | |
1978 | -{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, | |
1979 | -{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, | |
1980 | -{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, | |
1981 | -{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, | |
1982 | -{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, | |
1983 | -{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, | |
1984 | -{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, | |
1985 | -{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, | |
1986 | -{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, | |
1987 | -{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, | |
1988 | -{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, | |
1989 | -{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, | |
1990 | -{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, | |
1991 | -{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, | |
1992 | -{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, | |
1993 | -{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, | |
1994 | -{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, | |
1995 | -{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, | |
1996 | -{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, | |
1997 | -{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, | |
1998 | -{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, | |
1999 | -{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, | |
2000 | -{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, | |
2001 | -{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, | |
2002 | -{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, | |
2003 | -{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, | |
2004 | -{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, | |
2005 | -{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, | |
2006 | - | |
2007 | -{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, | |
2008 | -{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, | |
2009 | -{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, | |
2010 | -{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, | |
2011 | -{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, | |
2012 | -{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, | |
2013 | -{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, | |
2014 | -{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, | |
2015 | - | |
2016 | -{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, | |
2017 | -{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, | |
2018 | -{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, | |
2019 | -{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, | |
2020 | -{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, | |
2021 | -{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, | |
2022 | - | |
2023 | -{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, | |
2024 | - | |
2025 | -{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, | |
2026 | -{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, | |
2027 | -{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, | |
1962 | +{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, | |
1963 | +{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, | |
1964 | +{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, | |
1965 | +{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, | |
1966 | +{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, | |
1967 | +{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, | |
1968 | +{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, | |
1969 | + | |
1970 | +{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, | |
1971 | +{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, | |
1972 | +{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, | |
1973 | + | |
1974 | +{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, | |
1975 | +{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, | |
1976 | +{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, | |
1977 | +{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, | |
1978 | +{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, | |
1979 | +{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, | |
1980 | +{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, | |
1981 | +{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, | |
1982 | +{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, | |
1983 | +{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, | |
1984 | +{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, | |
1985 | +{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, | |
1986 | +{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, | |
1987 | +{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, | |
1988 | +{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, | |
1989 | +{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, | |
1990 | +{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, | |
1991 | +{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, | |
1992 | +{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, | |
1993 | +{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, | |
1994 | +{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, | |
1995 | +{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, | |
1996 | +{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, | |
1997 | +{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, | |
1998 | +{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, | |
1999 | +{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, | |
2000 | +{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, | |
2001 | +{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, | |
2002 | +{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, | |
2003 | +{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, | |
2004 | +{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, | |
2005 | +{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, | |
2006 | + | |
2007 | +{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, | |
2008 | +{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, | |
2009 | +{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, | |
2010 | +{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, | |
2011 | +{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, | |
2012 | +{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, | |
2013 | +{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, | |
2014 | +{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, | |
2015 | + | |
2016 | +{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, | |
2017 | +{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, | |
2018 | +{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, | |
2019 | +{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, | |
2020 | +{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, | |
2021 | +{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, | |
2022 | + | |
2023 | +{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, | |
2024 | + | |
2025 | +{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, | |
2026 | +{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, | |
2027 | +{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, | |
2028 | 2028 | |
2029 | 2029 | /* Cheetah instructions */ |
2030 | 2030 | { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, |
... | ... | @@ -2043,8 +2043,8 @@ SLCBCC("cbnefr", 15), |
2043 | 2043 | with v9a instructions such as "edge8" which looks like impdep1. */ |
2044 | 2044 | |
2045 | 2045 | #define IMPDEP(name, code) \ |
2046 | -{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ | |
2047 | -{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ | |
2046 | +{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ | |
2047 | +{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ | |
2048 | 2048 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ |
2049 | 2049 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } |
2050 | 2050 | |
... | ... | @@ -2303,8 +2303,8 @@ sparc_decode_sparclet_cpreg (value) |
2303 | 2303 | |
2304 | 2304 | /* Bitmask of v9 architectures. */ |
2305 | 2305 | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
2306 | - | (1 << SPARC_OPCODE_ARCH_V9A) \ | |
2307 | - | (1 << SPARC_OPCODE_ARCH_V9B)) | |
2306 | + | (1 << SPARC_OPCODE_ARCH_V9A) \ | |
2307 | + | (1 << SPARC_OPCODE_ARCH_V9B)) | |
2308 | 2308 | /* 1 if INSN is for v9 only. */ |
2309 | 2309 | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) |
2310 | 2310 | /* 1 if INSN is for v9. */ |
... | ... | @@ -2336,9 +2336,9 @@ static int compare_opcodes PARAMS ((const void *, const void *)); |
2336 | 2336 | static int compute_arch_mask PARAMS ((unsigned long)); |
2337 | 2337 | |
2338 | 2338 | /* Sign-extend a value which is N bits long. */ |
2339 | -#define SEX(value, bits) \ | |
2340 | - ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ | |
2341 | - >> ((8 * sizeof (int)) - bits) ) | |
2339 | +#define SEX(value, bits) \ | |
2340 | + ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ | |
2341 | + >> ((8 * sizeof (int)) - bits) ) | |
2342 | 2342 | |
2343 | 2343 | static const char * const reg_names[] = |
2344 | 2344 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
... | ... | @@ -2357,7 +2357,7 @@ static const char * const reg_names[] = |
2357 | 2357 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
2358 | 2358 | }; |
2359 | 2359 | |
2360 | -#define freg_names (®_names[4 * 8]) | |
2360 | +#define freg_names (®_names[4 * 8]) | |
2361 | 2361 | |
2362 | 2362 | /* These are ordered according to there register number in |
2363 | 2363 | rdpr and wrpr insns. */ |
... | ... | @@ -2403,55 +2403,55 @@ static const char * const v9a_asr_reg_names[] = |
2403 | 2403 | { |
2404 | 2404 | unsigned long int code; |
2405 | 2405 | struct |
2406 | - { | |
2407 | - unsigned int anop:2; | |
2408 | - #define op ldst.anop | |
2409 | - unsigned int anrd:5; | |
2410 | - #define rd ldst.anrd | |
2411 | - unsigned int op3:6; | |
2412 | - unsigned int anrs1:5; | |
2413 | - #define rs1 ldst.anrs1 | |
2414 | - unsigned int i:1; | |
2415 | - unsigned int anasi:8; | |
2416 | - #define asi ldst.anasi | |
2417 | - unsigned int anrs2:5; | |
2418 | - #define rs2 ldst.anrs2 | |
2419 | - #define shcnt rs2 | |
2420 | - } ldst; | |
2406 | + { | |
2407 | + unsigned int anop:2; | |
2408 | + #define op ldst.anop | |
2409 | + unsigned int anrd:5; | |
2410 | + #define rd ldst.anrd | |
2411 | + unsigned int op3:6; | |
2412 | + unsigned int anrs1:5; | |
2413 | + #define rs1 ldst.anrs1 | |
2414 | + unsigned int i:1; | |
2415 | + unsigned int anasi:8; | |
2416 | + #define asi ldst.anasi | |
2417 | + unsigned int anrs2:5; | |
2418 | + #define rs2 ldst.anrs2 | |
2419 | + #define shcnt rs2 | |
2420 | + } ldst; | |
2421 | 2421 | struct |
2422 | - { | |
2423 | - unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; | |
2424 | - unsigned int IMM13:13; | |
2425 | - #define imm13 IMM13.IMM13 | |
2426 | - } IMM13; | |
2422 | + { | |
2423 | + unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; | |
2424 | + unsigned int IMM13:13; | |
2425 | + #define imm13 IMM13.IMM13 | |
2426 | + } IMM13; | |
2427 | 2427 | struct |
2428 | - { | |
2429 | - unsigned int anop:2; | |
2430 | - unsigned int a:1; | |
2431 | - unsigned int cond:4; | |
2432 | - unsigned int op2:3; | |
2433 | - unsigned int DISP22:22; | |
2434 | - #define disp22 branch.DISP22 | |
2435 | - #define imm22 disp22 | |
2436 | - } branch; | |
2428 | + { | |
2429 | + unsigned int anop:2; | |
2430 | + unsigned int a:1; | |
2431 | + unsigned int cond:4; | |
2432 | + unsigned int op2:3; | |
2433 | + unsigned int DISP22:22; | |
2434 | + #define disp22 branch.DISP22 | |
2435 | + #define imm22 disp22 | |
2436 | + } branch; | |
2437 | 2437 | struct |
2438 | - { | |
2439 | - unsigned int anop:2; | |
2440 | - unsigned int a:1; | |
2441 | - unsigned int z:1; | |
2442 | - unsigned int rcond:3; | |
2443 | - unsigned int op2:3; | |
2444 | - unsigned int DISP16HI:2; | |
2445 | - unsigned int p:1; | |
2446 | - unsigned int _rs1:5; | |
2447 | - unsigned int DISP16LO:14; | |
2448 | - } branch16; | |
2438 | + { | |
2439 | + unsigned int anop:2; | |
2440 | + unsigned int a:1; | |
2441 | + unsigned int z:1; | |
2442 | + unsigned int rcond:3; | |
2443 | + unsigned int op2:3; | |
2444 | + unsigned int DISP16HI:2; | |
2445 | + unsigned int p:1; | |
2446 | + unsigned int _rs1:5; | |
2447 | + unsigned int DISP16LO:14; | |
2448 | + } branch16; | |
2449 | 2449 | struct |
2450 | - { | |
2451 | - unsigned int anop:2; | |
2452 | - unsigned int adisp30:30; | |
2453 | - #define disp30 call.adisp30 | |
2454 | - } call; | |
2450 | + { | |
2451 | + unsigned int anop:2; | |
2452 | + unsigned int adisp30:30; | |
2453 | + #define disp30 call.adisp30 | |
2454 | + } call; | |
2455 | 2455 | }; |
2456 | 2456 | |
2457 | 2457 | */ |
... | ... | @@ -2467,8 +2467,8 @@ is_delayed_branch (insn) |
2467 | 2467 | { |
2468 | 2468 | const struct sparc_opcode *opcode = op->opcode; |
2469 | 2469 | if ((opcode->match & insn) == opcode->match |
2470 | - && (opcode->lose & insn) == 0) | |
2471 | - return (opcode->flags & F_DELAYED); | |
2470 | + && (opcode->lose & insn) == 0) | |
2471 | + return (opcode->flags & F_DELAYED); | |
2472 | 2472 | } |
2473 | 2473 | return 0; |
2474 | 2474 | } |
... | ... | @@ -2510,13 +2510,13 @@ print_insn_sparc (memaddr, info) |
2510 | 2510 | current_arch_mask = compute_arch_mask (info->mach); |
2511 | 2511 | |
2512 | 2512 | if (!opcodes_initialized) |
2513 | - sorted_opcodes = (const struct sparc_opcode **) | |
2513 | + sorted_opcodes = (const struct sparc_opcode **) | |
2514 | 2514 | malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); |
2515 | 2515 | /* Reset the sorted table so we can resort it. */ |
2516 | 2516 | for (i = 0; i < sparc_num_opcodes; ++i) |
2517 | - sorted_opcodes[i] = &sparc_opcodes[i]; | |
2517 | + sorted_opcodes[i] = &sparc_opcodes[i]; | |
2518 | 2518 | qsort ((char *) sorted_opcodes, sparc_num_opcodes, |
2519 | - sizeof (sorted_opcodes[0]), compare_opcodes); | |
2519 | + sizeof (sorted_opcodes[0]), compare_opcodes); | |
2520 | 2520 | |
2521 | 2521 | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
2522 | 2522 | current_mach = info->mach; |
... | ... | @@ -2528,8 +2528,8 @@ print_insn_sparc (memaddr, info) |
2528 | 2528 | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); |
2529 | 2529 | if (status != 0) |
2530 | 2530 | { |
2531 | - (*info->memory_error_func) (status, memaddr, info); | |
2532 | - return -1; | |
2531 | + (*info->memory_error_func) (status, memaddr, info); | |
2532 | + return -1; | |
2533 | 2533 | } |
2534 | 2534 | } |
2535 | 2535 | |
... | ... | @@ -2542,10 +2542,10 @@ print_insn_sparc (memaddr, info) |
2542 | 2542 | |
2543 | 2543 | insn = getword (buffer); |
2544 | 2544 | |
2545 | - info->insn_info_valid = 1; /* We do return this info */ | |
2546 | - info->insn_type = dis_nonbranch; /* Assume non branch insn */ | |
2547 | - info->branch_delay_insns = 0; /* Assume no delay */ | |
2548 | - info->target = 0; /* Assume no target known */ | |
2545 | + info->insn_info_valid = 1; /* We do return this info */ | |
2546 | + info->insn_type = dis_nonbranch; /* Assume non branch insn */ | |
2547 | + info->branch_delay_insns = 0; /* Assume no delay */ | |
2548 | + info->target = 0; /* Assume no target known */ | |
2549 | 2549 | |
2550 | 2550 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
2551 | 2551 | { |
... | ... | @@ -2553,484 +2553,484 @@ print_insn_sparc (memaddr, info) |
2553 | 2553 | |
2554 | 2554 | /* If the insn isn't supported by the current architecture, skip it. */ |
2555 | 2555 | if (! (opcode->architecture & current_arch_mask)) |
2556 | - continue; | |
2556 | + continue; | |
2557 | 2557 | |
2558 | 2558 | if ((opcode->match & insn) == opcode->match |
2559 | - && (opcode->lose & insn) == 0) | |
2560 | - { | |
2561 | - /* Nonzero means that we have found an instruction which has | |
2562 | - the effect of adding or or'ing the imm13 field to rs1. */ | |
2563 | - int imm_added_to_rs1 = 0; | |
2564 | - int imm_ored_to_rs1 = 0; | |
2559 | + && (opcode->lose & insn) == 0) | |
2560 | + { | |
2561 | + /* Nonzero means that we have found an instruction which has | |
2562 | + the effect of adding or or'ing the imm13 field to rs1. */ | |
2563 | + int imm_added_to_rs1 = 0; | |
2564 | + int imm_ored_to_rs1 = 0; | |
2565 | 2565 | |
2566 | - /* Nonzero means that we have found a plus sign in the args | |
2567 | - field of the opcode table. */ | |
2568 | - int found_plus = 0; | |
2566 | + /* Nonzero means that we have found a plus sign in the args | |
2567 | + field of the opcode table. */ | |
2568 | + int found_plus = 0; | |
2569 | 2569 | |
2570 | - /* Nonzero means we have an annulled branch. */ | |
2571 | - int is_annulled = 0; | |
2570 | + /* Nonzero means we have an annulled branch. */ | |
2571 | + int is_annulled = 0; | |
2572 | 2572 | |
2573 | - /* Do we have an `add' or `or' instruction combining an | |
2573 | + /* Do we have an `add' or `or' instruction combining an | |
2574 | 2574 | immediate with rs1? */ |
2575 | - if (opcode->match == 0x80102000) /* or */ | |
2576 | - imm_ored_to_rs1 = 1; | |
2577 | - if (opcode->match == 0x80002000) /* add */ | |
2578 | - imm_added_to_rs1 = 1; | |
2579 | - | |
2580 | - if (X_RS1 (insn) != X_RD (insn) | |
2581 | - && strchr (opcode->args, 'r') != 0) | |
2582 | - /* Can't do simple format if source and dest are different. */ | |
2583 | - continue; | |
2584 | - if (X_RS2 (insn) != X_RD (insn) | |
2585 | - && strchr (opcode->args, 'O') != 0) | |
2586 | - /* Can't do simple format if source and dest are different. */ | |
2587 | - continue; | |
2588 | - | |
2589 | - (*info->fprintf_func) (stream, opcode->name); | |
2590 | - | |
2591 | - { | |
2592 | - register const char *s; | |
2593 | - | |
2594 | - if (opcode->args[0] != ',') | |
2595 | - (*info->fprintf_func) (stream, " "); | |
2596 | - for (s = opcode->args; *s != '\0'; ++s) | |
2597 | - { | |
2598 | - while (*s == ',') | |
2599 | - { | |
2600 | - (*info->fprintf_func) (stream, ","); | |
2601 | - ++s; | |
2602 | - switch (*s) { | |
2603 | - case 'a': | |
2604 | - (*info->fprintf_func) (stream, "a"); | |
2605 | - is_annulled = 1; | |
2606 | - ++s; | |
2607 | - continue; | |
2608 | - case 'N': | |
2609 | - (*info->fprintf_func) (stream, "pn"); | |
2610 | - ++s; | |
2611 | - continue; | |
2612 | - | |
2613 | - case 'T': | |
2614 | - (*info->fprintf_func) (stream, "pt"); | |
2615 | - ++s; | |
2616 | - continue; | |
2617 | - | |
2618 | - default: | |
2619 | - break; | |
2620 | - } /* switch on arg */ | |
2621 | - } /* while there are comma started args */ | |
2622 | - | |
2623 | - (*info->fprintf_func) (stream, " "); | |
2624 | - | |
2625 | - switch (*s) | |
2626 | - { | |
2627 | - case '+': | |
2628 | - found_plus = 1; | |
2629 | - | |
2630 | - /* note fall-through */ | |
2631 | - default: | |
2632 | - (*info->fprintf_func) (stream, "%c", *s); | |
2633 | - break; | |
2634 | - | |
2635 | - case '#': | |
2636 | - (*info->fprintf_func) (stream, "0"); | |
2637 | - break; | |
2638 | - | |
2639 | -#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) | |
2640 | - case '1': | |
2641 | - case 'r': | |
2642 | - reg (X_RS1 (insn)); | |
2643 | - break; | |
2644 | - | |
2645 | - case '2': | |
2646 | - case 'O': | |
2647 | - reg (X_RS2 (insn)); | |
2648 | - break; | |
2649 | - | |
2650 | - case 'd': | |
2651 | - reg (X_RD (insn)); | |
2652 | - break; | |
2653 | -#undef reg | |
2654 | - | |
2655 | -#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) | |
2656 | -#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) | |
2657 | - case 'e': | |
2658 | - freg (X_RS1 (insn)); | |
2659 | - break; | |
2660 | - case 'v': /* double/even */ | |
2661 | - case 'V': /* quad/multiple of 4 */ | |
2662 | - fregx (X_RS1 (insn)); | |
2663 | - break; | |
2664 | - | |
2665 | - case 'f': | |
2666 | - freg (X_RS2 (insn)); | |
2667 | - break; | |
2668 | - case 'B': /* double/even */ | |
2669 | - case 'R': /* quad/multiple of 4 */ | |
2670 | - fregx (X_RS2 (insn)); | |
2671 | - break; | |
2672 | - | |
2673 | - case 'g': | |
2674 | - freg (X_RD (insn)); | |
2675 | - break; | |
2676 | - case 'H': /* double/even */ | |
2677 | - case 'J': /* quad/multiple of 4 */ | |
2678 | - fregx (X_RD (insn)); | |
2679 | - break; | |
2680 | -#undef freg | |
2681 | -#undef fregx | |
2682 | - | |
2683 | -#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) | |
2684 | - case 'b': | |
2685 | - creg (X_RS1 (insn)); | |
2686 | - break; | |
2687 | - | |
2688 | - case 'c': | |
2689 | - creg (X_RS2 (insn)); | |
2690 | - break; | |
2691 | - | |
2692 | - case 'D': | |
2693 | - creg (X_RD (insn)); | |
2694 | - break; | |
2695 | -#undef creg | |
2696 | - | |
2697 | - case 'h': | |
2698 | - (*info->fprintf_func) (stream, "%%hi(%#x)", | |
2699 | - ((unsigned) 0xFFFFFFFF | |
2700 | - & ((int) X_IMM22 (insn) << 10))); | |
2701 | - break; | |
2702 | - | |
2703 | - case 'i': /* 13 bit immediate */ | |
2704 | - case 'I': /* 11 bit immediate */ | |
2705 | - case 'j': /* 10 bit immediate */ | |
2706 | - { | |
2707 | - int imm; | |
2708 | - | |
2709 | - if (*s == 'i') | |
2710 | - imm = X_SIMM (insn, 13); | |
2711 | - else if (*s == 'I') | |
2712 | - imm = X_SIMM (insn, 11); | |
2713 | - else | |
2714 | - imm = X_SIMM (insn, 10); | |
2715 | - | |
2716 | - /* Check to see whether we have a 1+i, and take | |
2717 | - note of that fact. | |
2718 | - | |
2719 | - Note: because of the way we sort the table, | |
2720 | - we will be matching 1+i rather than i+1, | |
2721 | - so it is OK to assume that i is after +, | |
2722 | - not before it. */ | |
2723 | - if (found_plus) | |
2724 | - imm_added_to_rs1 = 1; | |
2725 | - | |
2726 | - if (imm <= 9) | |
2727 | - (*info->fprintf_func) (stream, "%d", imm); | |
2728 | - else | |
2729 | - (*info->fprintf_func) (stream, "%#x", imm); | |
2730 | - } | |
2731 | - break; | |
2732 | - | |
2733 | - case 'X': /* 5 bit unsigned immediate */ | |
2734 | - case 'Y': /* 6 bit unsigned immediate */ | |
2735 | - { | |
2736 | - int imm = X_IMM (insn, *s == 'X' ? 5 : 6); | |
2737 | - | |
2738 | - if (imm <= 9) | |
2739 | - (info->fprintf_func) (stream, "%d", imm); | |
2740 | - else | |
2741 | - (info->fprintf_func) (stream, "%#x", (unsigned) imm); | |
2742 | - } | |
2743 | - break; | |
2744 | - | |
2745 | - case '3': | |
2746 | - (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); | |
2747 | - break; | |
2748 | - | |
2749 | - case 'K': | |
2750 | - { | |
2751 | - int mask = X_MEMBAR (insn); | |
2752 | - int bit = 0x40, printed_one = 0; | |
2753 | - const char *name; | |
2754 | - | |
2755 | - if (mask == 0) | |
2756 | - (info->fprintf_func) (stream, "0"); | |
2757 | - else | |
2758 | - while (bit) | |
2759 | - { | |
2760 | - if (mask & bit) | |
2761 | - { | |
2762 | - if (printed_one) | |
2763 | - (info->fprintf_func) (stream, "|"); | |
2764 | - name = sparc_decode_membar (bit); | |
2765 | - (info->fprintf_func) (stream, "%s", name); | |
2766 | - printed_one = 1; | |
2767 | - } | |
2768 | - bit >>= 1; | |
2769 | - } | |
2770 | - break; | |
2771 | - } | |
2772 | - | |
2773 | - case 'k': | |
2774 | - info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; | |
2775 | - (*info->print_address_func) (info->target, info); | |
2776 | - break; | |
2777 | - | |
2778 | - case 'G': | |
2779 | - info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; | |
2780 | - (*info->print_address_func) (info->target, info); | |
2781 | - break; | |
2782 | - | |
2783 | - case '6': | |
2784 | - case '7': | |
2785 | - case '8': | |
2786 | - case '9': | |
2787 | - (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); | |
2788 | - break; | |
2789 | - | |
2790 | - case 'z': | |
2791 | - (*info->fprintf_func) (stream, "%%icc"); | |
2792 | - break; | |
2793 | - | |
2794 | - case 'Z': | |
2795 | - (*info->fprintf_func) (stream, "%%xcc"); | |
2796 | - break; | |
2797 | - | |
2798 | - case 'E': | |
2799 | - (*info->fprintf_func) (stream, "%%ccr"); | |
2800 | - break; | |
2801 | - | |
2802 | - case 's': | |
2803 | - (*info->fprintf_func) (stream, "%%fprs"); | |
2804 | - break; | |
2805 | - | |
2806 | - case 'o': | |
2807 | - (*info->fprintf_func) (stream, "%%asi"); | |
2808 | - break; | |
2809 | - | |
2810 | - case 'W': | |
2811 | - (*info->fprintf_func) (stream, "%%tick"); | |
2812 | - break; | |
2813 | - | |
2814 | - case 'P': | |
2815 | - (*info->fprintf_func) (stream, "%%pc"); | |
2816 | - break; | |
2817 | - | |
2818 | - case '?': | |
2819 | - if (X_RS1 (insn) == 31) | |
2820 | - (*info->fprintf_func) (stream, "%%ver"); | |
2821 | - else if ((unsigned) X_RS1 (insn) < 16) | |
2822 | - (*info->fprintf_func) (stream, "%%%s", | |
2823 | - v9_priv_reg_names[X_RS1 (insn)]); | |
2824 | - else | |
2825 | - (*info->fprintf_func) (stream, "%%reserved"); | |
2826 | - break; | |
2827 | - | |
2828 | - case '!': | |
2829 | - if ((unsigned) X_RD (insn) < 15) | |
2830 | - (*info->fprintf_func) (stream, "%%%s", | |
2831 | - v9_priv_reg_names[X_RD (insn)]); | |
2832 | - else | |
2833 | - (*info->fprintf_func) (stream, "%%reserved"); | |
2834 | - break; | |
2835 | - | |
2836 | - case '/': | |
2837 | - if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) | |
2838 | - (*info->fprintf_func) (stream, "%%reserved"); | |
2839 | - else | |
2840 | - (*info->fprintf_func) (stream, "%%%s", | |
2841 | - v9a_asr_reg_names[X_RS1 (insn)-16]); | |
2842 | - break; | |
2843 | - | |
2844 | - case '_': | |
2845 | - if (X_RD (insn) < 16 || X_RD (insn) > 25) | |
2846 | - (*info->fprintf_func) (stream, "%%reserved"); | |
2847 | - else | |
2848 | - (*info->fprintf_func) (stream, "%%%s", | |
2849 | - v9a_asr_reg_names[X_RD (insn)-16]); | |
2850 | - break; | |
2851 | - | |
2852 | - case '*': | |
2853 | - { | |
2854 | - const char *name = sparc_decode_prefetch (X_RD (insn)); | |
2855 | - | |
2856 | - if (name) | |
2857 | - (*info->fprintf_func) (stream, "%s", name); | |
2858 | - else | |
2859 | - (*info->fprintf_func) (stream, "%d", X_RD (insn)); | |
2860 | - break; | |
2861 | - } | |
2862 | - | |
2863 | - case 'M': | |
2864 | - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); | |
2865 | - break; | |
2866 | - | |
2867 | - case 'm': | |
2868 | - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); | |
2869 | - break; | |
2870 | - | |
2871 | - case 'L': | |
2872 | - info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; | |
2873 | - (*info->print_address_func) (info->target, info); | |
2874 | - break; | |
2875 | - | |
2876 | - case 'n': | |
2877 | - (*info->fprintf_func) | |
2878 | - (stream, "%#x", SEX (X_DISP22 (insn), 22)); | |
2879 | - break; | |
2880 | - | |
2881 | - case 'l': | |
2882 | - info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; | |
2883 | - (*info->print_address_func) (info->target, info); | |
2884 | - break; | |
2885 | - | |
2886 | - case 'A': | |
2887 | - { | |
2888 | - const char *name; | |
2889 | - | |
2890 | - if ((info->mach == bfd_mach_sparc_v8plusa) || | |
2575 | + if (opcode->match == 0x80102000) /* or */ | |
2576 | + imm_ored_to_rs1 = 1; | |
2577 | + if (opcode->match == 0x80002000) /* add */ | |
2578 | + imm_added_to_rs1 = 1; | |
2579 | + | |
2580 | + if (X_RS1 (insn) != X_RD (insn) | |
2581 | + && strchr (opcode->args, 'r') != 0) | |
2582 | + /* Can't do simple format if source and dest are different. */ | |
2583 | + continue; | |
2584 | + if (X_RS2 (insn) != X_RD (insn) | |
2585 | + && strchr (opcode->args, 'O') != 0) | |
2586 | + /* Can't do simple format if source and dest are different. */ | |
2587 | + continue; | |
2588 | + | |
2589 | + (*info->fprintf_func) (stream, opcode->name); | |
2590 | + | |
2591 | + { | |
2592 | + register const char *s; | |
2593 | + | |
2594 | + if (opcode->args[0] != ',') | |
2595 | + (*info->fprintf_func) (stream, " "); | |
2596 | + for (s = opcode->args; *s != '\0'; ++s) | |
2597 | + { | |
2598 | + while (*s == ',') | |
2599 | + { | |
2600 | + (*info->fprintf_func) (stream, ","); | |
2601 | + ++s; | |
2602 | + switch (*s) { | |
2603 | + case 'a': | |
2604 | + (*info->fprintf_func) (stream, "a"); | |
2605 | + is_annulled = 1; | |
2606 | + ++s; | |
2607 | + continue; | |
2608 | + case 'N': | |
2609 | + (*info->fprintf_func) (stream, "pn"); | |
2610 | + ++s; | |
2611 | + continue; | |
2612 | + | |
2613 | + case 'T': | |
2614 | + (*info->fprintf_func) (stream, "pt"); | |
2615 | + ++s; | |
2616 | + continue; | |
2617 | + | |
2618 | + default: | |
2619 | + break; | |
2620 | + } /* switch on arg */ | |
2621 | + } /* while there are comma started args */ | |
2622 | + | |
2623 | + (*info->fprintf_func) (stream, " "); | |
2624 | + | |
2625 | + switch (*s) | |
2626 | + { | |
2627 | + case '+': | |
2628 | + found_plus = 1; | |
2629 | + | |
2630 | + /* note fall-through */ | |
2631 | + default: | |
2632 | + (*info->fprintf_func) (stream, "%c", *s); | |
2633 | + break; | |
2634 | + | |
2635 | + case '#': | |
2636 | + (*info->fprintf_func) (stream, "0"); | |
2637 | + break; | |
2638 | + | |
2639 | +#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) | |
2640 | + case '1': | |
2641 | + case 'r': | |
2642 | + reg (X_RS1 (insn)); | |
2643 | + break; | |
2644 | + | |
2645 | + case '2': | |
2646 | + case 'O': | |
2647 | + reg (X_RS2 (insn)); | |
2648 | + break; | |
2649 | + | |
2650 | + case 'd': | |
2651 | + reg (X_RD (insn)); | |
2652 | + break; | |
2653 | +#undef reg | |
2654 | + | |
2655 | +#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) | |
2656 | +#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) | |
2657 | + case 'e': | |
2658 | + freg (X_RS1 (insn)); | |
2659 | + break; | |
2660 | + case 'v': /* double/even */ | |
2661 | + case 'V': /* quad/multiple of 4 */ | |
2662 | + fregx (X_RS1 (insn)); | |
2663 | + break; | |
2664 | + | |
2665 | + case 'f': | |
2666 | + freg (X_RS2 (insn)); | |
2667 | + break; | |
2668 | + case 'B': /* double/even */ | |
2669 | + case 'R': /* quad/multiple of 4 */ | |
2670 | + fregx (X_RS2 (insn)); | |
2671 | + break; | |
2672 | + | |
2673 | + case 'g': | |
2674 | + freg (X_RD (insn)); | |
2675 | + break; | |
2676 | + case 'H': /* double/even */ | |
2677 | + case 'J': /* quad/multiple of 4 */ | |
2678 | + fregx (X_RD (insn)); | |
2679 | + break; | |
2680 | +#undef freg | |
2681 | +#undef fregx | |
2682 | + | |
2683 | +#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) | |
2684 | + case 'b': | |
2685 | + creg (X_RS1 (insn)); | |
2686 | + break; | |
2687 | + | |
2688 | + case 'c': | |
2689 | + creg (X_RS2 (insn)); | |
2690 | + break; | |
2691 | + | |
2692 | + case 'D': | |
2693 | + creg (X_RD (insn)); | |
2694 | + break; | |
2695 | +#undef creg | |
2696 | + | |
2697 | + case 'h': | |
2698 | + (*info->fprintf_func) (stream, "%%hi(%#x)", | |
2699 | + ((unsigned) 0xFFFFFFFF | |
2700 | + & ((int) X_IMM22 (insn) << 10))); | |
2701 | + break; | |
2702 | + | |
2703 | + case 'i': /* 13 bit immediate */ | |
2704 | + case 'I': /* 11 bit immediate */ | |
2705 | + case 'j': /* 10 bit immediate */ | |
2706 | + { | |
2707 | + int imm; | |
2708 | + | |
2709 | + if (*s == 'i') | |
2710 | + imm = X_SIMM (insn, 13); | |
2711 | + else if (*s == 'I') | |
2712 | + imm = X_SIMM (insn, 11); | |
2713 | + else | |
2714 | + imm = X_SIMM (insn, 10); | |
2715 | + | |
2716 | + /* Check to see whether we have a 1+i, and take | |
2717 | + note of that fact. | |
2718 | + | |
2719 | + Note: because of the way we sort the table, | |
2720 | + we will be matching 1+i rather than i+1, | |
2721 | + so it is OK to assume that i is after +, | |
2722 | + not before it. */ | |
2723 | + if (found_plus) | |
2724 | + imm_added_to_rs1 = 1; | |
2725 | + | |
2726 | + if (imm <= 9) | |
2727 | + (*info->fprintf_func) (stream, "%d", imm); | |
2728 | + else | |
2729 | + (*info->fprintf_func) (stream, "%#x", imm); | |
2730 | + } | |
2731 | + break; | |
2732 | + | |
2733 | + case 'X': /* 5 bit unsigned immediate */ | |
2734 | + case 'Y': /* 6 bit unsigned immediate */ | |
2735 | + { | |
2736 | + int imm = X_IMM (insn, *s == 'X' ? 5 : 6); | |
2737 | + | |
2738 | + if (imm <= 9) | |
2739 | + (info->fprintf_func) (stream, "%d", imm); | |
2740 | + else | |
2741 | + (info->fprintf_func) (stream, "%#x", (unsigned) imm); | |
2742 | + } | |
2743 | + break; | |
2744 | + | |
2745 | + case '3': | |
2746 | + (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); | |
2747 | + break; | |
2748 | + | |
2749 | + case 'K': | |
2750 | + { | |
2751 | + int mask = X_MEMBAR (insn); | |
2752 | + int bit = 0x40, printed_one = 0; | |
2753 | + const char *name; | |
2754 | + | |
2755 | + if (mask == 0) | |
2756 | + (info->fprintf_func) (stream, "0"); | |
2757 | + else | |
2758 | + while (bit) | |
2759 | + { | |
2760 | + if (mask & bit) | |
2761 | + { | |
2762 | + if (printed_one) | |
2763 | + (info->fprintf_func) (stream, "|"); | |
2764 | + name = sparc_decode_membar (bit); | |
2765 | + (info->fprintf_func) (stream, "%s", name); | |
2766 | + printed_one = 1; | |
2767 | + } | |
2768 | + bit >>= 1; | |
2769 | + } | |
2770 | + break; | |
2771 | + } | |
2772 | + | |
2773 | + case 'k': | |
2774 | + info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; | |
2775 | + (*info->print_address_func) (info->target, info); | |
2776 | + break; | |
2777 | + | |
2778 | + case 'G': | |
2779 | + info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; | |
2780 | + (*info->print_address_func) (info->target, info); | |
2781 | + break; | |
2782 | + | |
2783 | + case '6': | |
2784 | + case '7': | |
2785 | + case '8': | |
2786 | + case '9': | |
2787 | + (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); | |
2788 | + break; | |
2789 | + | |
2790 | + case 'z': | |
2791 | + (*info->fprintf_func) (stream, "%%icc"); | |
2792 | + break; | |
2793 | + | |
2794 | + case 'Z': | |
2795 | + (*info->fprintf_func) (stream, "%%xcc"); | |
2796 | + break; | |
2797 | + | |
2798 | + case 'E': | |
2799 | + (*info->fprintf_func) (stream, "%%ccr"); | |
2800 | + break; | |
2801 | + | |
2802 | + case 's': | |
2803 | + (*info->fprintf_func) (stream, "%%fprs"); | |
2804 | + break; | |
2805 | + | |
2806 | + case 'o': | |
2807 | + (*info->fprintf_func) (stream, "%%asi"); | |
2808 | + break; | |
2809 | + | |
2810 | + case 'W': | |
2811 | + (*info->fprintf_func) (stream, "%%tick"); | |
2812 | + break; | |
2813 | + | |
2814 | + case 'P': | |
2815 | + (*info->fprintf_func) (stream, "%%pc"); | |
2816 | + break; | |
2817 | + | |
2818 | + case '?': | |
2819 | + if (X_RS1 (insn) == 31) | |
2820 | + (*info->fprintf_func) (stream, "%%ver"); | |
2821 | + else if ((unsigned) X_RS1 (insn) < 16) | |
2822 | + (*info->fprintf_func) (stream, "%%%s", | |
2823 | + v9_priv_reg_names[X_RS1 (insn)]); | |
2824 | + else | |
2825 | + (*info->fprintf_func) (stream, "%%reserved"); | |
2826 | + break; | |
2827 | + | |
2828 | + case '!': | |
2829 | + if ((unsigned) X_RD (insn) < 15) | |
2830 | + (*info->fprintf_func) (stream, "%%%s", | |
2831 | + v9_priv_reg_names[X_RD (insn)]); | |
2832 | + else | |
2833 | + (*info->fprintf_func) (stream, "%%reserved"); | |
2834 | + break; | |
2835 | + | |
2836 | + case '/': | |
2837 | + if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) | |
2838 | + (*info->fprintf_func) (stream, "%%reserved"); | |
2839 | + else | |
2840 | + (*info->fprintf_func) (stream, "%%%s", | |
2841 | + v9a_asr_reg_names[X_RS1 (insn)-16]); | |
2842 | + break; | |
2843 | + | |
2844 | + case '_': | |
2845 | + if (X_RD (insn) < 16 || X_RD (insn) > 25) | |
2846 | + (*info->fprintf_func) (stream, "%%reserved"); | |
2847 | + else | |
2848 | + (*info->fprintf_func) (stream, "%%%s", | |
2849 | + v9a_asr_reg_names[X_RD (insn)-16]); | |
2850 | + break; | |
2851 | + | |
2852 | + case '*': | |
2853 | + { | |
2854 | + const char *name = sparc_decode_prefetch (X_RD (insn)); | |
2855 | + | |
2856 | + if (name) | |
2857 | + (*info->fprintf_func) (stream, "%s", name); | |
2858 | + else | |
2859 | + (*info->fprintf_func) (stream, "%d", X_RD (insn)); | |
2860 | + break; | |
2861 | + } | |
2862 | + | |
2863 | + case 'M': | |
2864 | + (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); | |
2865 | + break; | |
2866 | + | |
2867 | + case 'm': | |
2868 | + (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); | |
2869 | + break; | |
2870 | + | |
2871 | + case 'L': | |
2872 | + info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; | |
2873 | + (*info->print_address_func) (info->target, info); | |
2874 | + break; | |
2875 | + | |
2876 | + case 'n': | |
2877 | + (*info->fprintf_func) | |
2878 | + (stream, "%#x", SEX (X_DISP22 (insn), 22)); | |
2879 | + break; | |
2880 | + | |
2881 | + case 'l': | |
2882 | + info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; | |
2883 | + (*info->print_address_func) (info->target, info); | |
2884 | + break; | |
2885 | + | |
2886 | + case 'A': | |
2887 | + { | |
2888 | + const char *name; | |
2889 | + | |
2890 | + if ((info->mach == bfd_mach_sparc_v8plusa) || | |
2891 | 2891 | ((info->mach >= bfd_mach_sparc_v9) && |
2892 | 2892 | (info->mach <= bfd_mach_sparc_v9b))) |
2893 | - name = sparc_decode_asi_v9 (X_ASI (insn)); | |
2894 | - else | |
2895 | - name = sparc_decode_asi_v8 (X_ASI (insn)); | |
2896 | - | |
2897 | - if (name) | |
2898 | - (*info->fprintf_func) (stream, "%s", name); | |
2899 | - else | |
2900 | - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); | |
2901 | - break; | |
2902 | - } | |
2903 | - | |
2904 | - case 'C': | |
2905 | - (*info->fprintf_func) (stream, "%%csr"); | |
2906 | - break; | |
2907 | - | |
2908 | - case 'F': | |
2909 | - (*info->fprintf_func) (stream, "%%fsr"); | |
2910 | - break; | |
2911 | - | |
2912 | - case 'p': | |
2913 | - (*info->fprintf_func) (stream, "%%psr"); | |
2914 | - break; | |
2915 | - | |
2916 | - case 'q': | |
2917 | - (*info->fprintf_func) (stream, "%%fq"); | |
2918 | - break; | |
2919 | - | |
2920 | - case 'Q': | |
2921 | - (*info->fprintf_func) (stream, "%%cq"); | |
2922 | - break; | |
2923 | - | |
2924 | - case 't': | |
2925 | - (*info->fprintf_func) (stream, "%%tbr"); | |
2926 | - break; | |
2927 | - | |
2928 | - case 'w': | |
2929 | - (*info->fprintf_func) (stream, "%%wim"); | |
2930 | - break; | |
2931 | - | |
2932 | - case 'x': | |
2933 | - (*info->fprintf_func) (stream, "%d", | |
2934 | - ((X_LDST_I (insn) << 8) | |
2935 | - + X_ASI (insn))); | |
2936 | - break; | |
2937 | - | |
2938 | - case 'y': | |
2939 | - (*info->fprintf_func) (stream, "%%y"); | |
2940 | - break; | |
2941 | - | |
2942 | - case 'u': | |
2943 | - case 'U': | |
2944 | - { | |
2945 | - int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); | |
2946 | - const char *name = sparc_decode_sparclet_cpreg (val); | |
2947 | - | |
2948 | - if (name) | |
2949 | - (*info->fprintf_func) (stream, "%s", name); | |
2950 | - else | |
2951 | - (*info->fprintf_func) (stream, "%%cpreg(%d)", val); | |
2952 | - break; | |
2953 | - } | |
2954 | - } | |
2955 | - } | |
2956 | - } | |
2957 | - | |
2958 | - /* If we are adding or or'ing something to rs1, then | |
2959 | - check to see whether the previous instruction was | |
2960 | - a sethi to the same register as in the sethi. | |
2961 | - If so, attempt to print the result of the add or | |
2962 | - or (in this context add and or do the same thing) | |
2963 | - and its symbolic value. */ | |
2964 | - if (imm_ored_to_rs1 || imm_added_to_rs1) | |
2965 | - { | |
2966 | - unsigned long prev_insn; | |
2967 | - int errcode; | |
2968 | - | |
2969 | - errcode = | |
2970 | - (*info->read_memory_func) | |
2971 | - (memaddr - 4, buffer, sizeof (buffer), info); | |
2972 | - prev_insn = getword (buffer); | |
2973 | - | |
2974 | - if (errcode == 0) | |
2975 | - { | |
2976 | - /* If it is a delayed branch, we need to look at the | |
2977 | - instruction before the delayed branch. This handles | |
2978 | - sequences such as | |
2979 | - | |
2980 | - sethi %o1, %hi(_foo), %o1 | |
2981 | - call _printf | |
2982 | - or %o1, %lo(_foo), %o1 | |
2983 | - */ | |
2984 | - | |
2985 | - if (is_delayed_branch (prev_insn)) | |
2986 | - { | |
2987 | - errcode = (*info->read_memory_func) | |
2988 | - (memaddr - 8, buffer, sizeof (buffer), info); | |
2989 | - prev_insn = getword (buffer); | |
2990 | - } | |
2991 | - } | |
2992 | - | |
2993 | - /* If there was a problem reading memory, then assume | |
2994 | - the previous instruction was not sethi. */ | |
2995 | - if (errcode == 0) | |
2996 | - { | |
2997 | - /* Is it sethi to the same register? */ | |
2998 | - if ((prev_insn & 0xc1c00000) == 0x01000000 | |
2999 | - && X_RD (prev_insn) == X_RS1 (insn)) | |
3000 | - { | |
3001 | - (*info->fprintf_func) (stream, "\t! "); | |
3002 | - info->target = | |
3003 | - ((unsigned) 0xFFFFFFFF | |
3004 | - & ((int) X_IMM22 (prev_insn) << 10)); | |
3005 | - if (imm_added_to_rs1) | |
3006 | - info->target += X_SIMM (insn, 13); | |
3007 | - else | |
3008 | - info->target |= X_SIMM (insn, 13); | |
3009 | - (*info->print_address_func) (info->target, info); | |
3010 | - info->insn_type = dis_dref; | |
3011 | - info->data_size = 4; /* FIXME!!! */ | |
3012 | - } | |
3013 | - } | |
3014 | - } | |
3015 | - | |
3016 | - if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) | |
3017 | - { | |
3018 | - /* FIXME -- check is_annulled flag */ | |
3019 | - if (opcode->flags & F_UNBR) | |
3020 | - info->insn_type = dis_branch; | |
3021 | - if (opcode->flags & F_CONDBR) | |
3022 | - info->insn_type = dis_condbranch; | |
3023 | - if (opcode->flags & F_JSR) | |
3024 | - info->insn_type = dis_jsr; | |
3025 | - if (opcode->flags & F_DELAYED) | |
3026 | - info->branch_delay_insns = 1; | |
3027 | - } | |
3028 | - | |
3029 | - return sizeof (buffer); | |
3030 | - } | |
2893 | + name = sparc_decode_asi_v9 (X_ASI (insn)); | |
2894 | + else | |
2895 | + name = sparc_decode_asi_v8 (X_ASI (insn)); | |
2896 | + | |
2897 | + if (name) | |
2898 | + (*info->fprintf_func) (stream, "%s", name); | |
2899 | + else | |
2900 | + (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); | |
2901 | + break; | |
2902 | + } | |
2903 | + | |
2904 | + case 'C': | |
2905 | + (*info->fprintf_func) (stream, "%%csr"); | |
2906 | + break; | |
2907 | + | |
2908 | + case 'F': | |
2909 | + (*info->fprintf_func) (stream, "%%fsr"); | |
2910 | + break; | |
2911 | + | |
2912 | + case 'p': | |
2913 | + (*info->fprintf_func) (stream, "%%psr"); | |
2914 | + break; | |
2915 | + | |
2916 | + case 'q': | |
2917 | + (*info->fprintf_func) (stream, "%%fq"); | |
2918 | + break; | |
2919 | + | |
2920 | + case 'Q': | |
2921 | + (*info->fprintf_func) (stream, "%%cq"); | |
2922 | + break; | |
2923 | + | |
2924 | + case 't': | |
2925 | + (*info->fprintf_func) (stream, "%%tbr"); | |
2926 | + break; | |
2927 | + | |
2928 | + case 'w': | |
2929 | + (*info->fprintf_func) (stream, "%%wim"); | |
2930 | + break; | |
2931 | + | |
2932 | + case 'x': | |
2933 | + (*info->fprintf_func) (stream, "%d", | |
2934 | + ((X_LDST_I (insn) << 8) | |
2935 | + + X_ASI (insn))); | |
2936 | + break; | |
2937 | + | |
2938 | + case 'y': | |
2939 | + (*info->fprintf_func) (stream, "%%y"); | |
2940 | + break; | |
2941 | + | |
2942 | + case 'u': | |
2943 | + case 'U': | |
2944 | + { | |
2945 | + int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); | |
2946 | + const char *name = sparc_decode_sparclet_cpreg (val); | |
2947 | + | |
2948 | + if (name) | |
2949 | + (*info->fprintf_func) (stream, "%s", name); | |
2950 | + else | |
2951 | + (*info->fprintf_func) (stream, "%%cpreg(%d)", val); | |
2952 | + break; | |
2953 | + } | |
2954 | + } | |
2955 | + } | |
2956 | + } | |
2957 | + | |
2958 | + /* If we are adding or or'ing something to rs1, then | |
2959 | + check to see whether the previous instruction was | |
2960 | + a sethi to the same register as in the sethi. | |
2961 | + If so, attempt to print the result of the add or | |
2962 | + or (in this context add and or do the same thing) | |
2963 | + and its symbolic value. */ | |
2964 | + if (imm_ored_to_rs1 || imm_added_to_rs1) | |
2965 | + { | |
2966 | + unsigned long prev_insn; | |
2967 | + int errcode; | |
2968 | + | |
2969 | + errcode = | |
2970 | + (*info->read_memory_func) | |
2971 | + (memaddr - 4, buffer, sizeof (buffer), info); | |
2972 | + prev_insn = getword (buffer); | |
2973 | + | |
2974 | + if (errcode == 0) | |
2975 | + { | |
2976 | + /* If it is a delayed branch, we need to look at the | |
2977 | + instruction before the delayed branch. This handles | |
2978 | + sequences such as | |
2979 | + | |
2980 | + sethi %o1, %hi(_foo), %o1 | |
2981 | + call _printf | |
2982 | + or %o1, %lo(_foo), %o1 | |
2983 | + */ | |
2984 | + | |
2985 | + if (is_delayed_branch (prev_insn)) | |
2986 | + { | |
2987 | + errcode = (*info->read_memory_func) | |
2988 | + (memaddr - 8, buffer, sizeof (buffer), info); | |
2989 | + prev_insn = getword (buffer); | |
2990 | + } | |
2991 | + } | |
2992 | + | |
2993 | + /* If there was a problem reading memory, then assume | |
2994 | + the previous instruction was not sethi. */ | |
2995 | + if (errcode == 0) | |
2996 | + { | |
2997 | + /* Is it sethi to the same register? */ | |
2998 | + if ((prev_insn & 0xc1c00000) == 0x01000000 | |
2999 | + && X_RD (prev_insn) == X_RS1 (insn)) | |
3000 | + { | |
3001 | + (*info->fprintf_func) (stream, "\t! "); | |
3002 | + info->target = | |
3003 | + ((unsigned) 0xFFFFFFFF | |
3004 | + & ((int) X_IMM22 (prev_insn) << 10)); | |
3005 | + if (imm_added_to_rs1) | |
3006 | + info->target += X_SIMM (insn, 13); | |
3007 | + else | |
3008 | + info->target |= X_SIMM (insn, 13); | |
3009 | + (*info->print_address_func) (info->target, info); | |
3010 | + info->insn_type = dis_dref; | |
3011 | + info->data_size = 4; /* FIXME!!! */ | |
3012 | + } | |
3013 | + } | |
3014 | + } | |
3015 | + | |
3016 | + if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) | |
3017 | + { | |
3018 | + /* FIXME -- check is_annulled flag */ | |
3019 | + if (opcode->flags & F_UNBR) | |
3020 | + info->insn_type = dis_branch; | |
3021 | + if (opcode->flags & F_CONDBR) | |
3022 | + info->insn_type = dis_condbranch; | |
3023 | + if (opcode->flags & F_JSR) | |
3024 | + info->insn_type = dis_jsr; | |
3025 | + if (opcode->flags & F_DELAYED) | |
3026 | + info->branch_delay_insns = 1; | |
3027 | + } | |
3028 | + | |
3029 | + return sizeof (buffer); | |
3030 | + } | |
3031 | 3031 | } |
3032 | 3032 | |
3033 | - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ | |
3033 | + info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ | |
3034 | 3034 | (*info->fprintf_func) (stream, _("unknown")); |
3035 | 3035 | return sizeof (buffer); |
3036 | 3036 | } |
... | ... | @@ -3051,10 +3051,10 @@ compute_arch_mask (mach) |
3051 | 3051 | case bfd_mach_sparc_sparclite : |
3052 | 3052 | case bfd_mach_sparc_sparclite_le : |
3053 | 3053 | /* sparclites insns are recognized by default (because that's how |
3054 | - they've always been treated, for better or worse). Kludge this by | |
3055 | - indicating generic v8 is also selected. */ | |
3054 | + they've always been treated, for better or worse). Kludge this by | |
3055 | + indicating generic v8 is also selected. */ | |
3056 | 3056 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
3057 | - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); | |
3057 | + | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); | |
3058 | 3058 | case bfd_mach_sparc_v8plus : |
3059 | 3059 | case bfd_mach_sparc_v9 : |
3060 | 3060 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); |
... | ... | @@ -3087,14 +3087,14 @@ compare_opcodes (const void *a, const void *b) |
3087 | 3087 | if (op0->architecture & current_arch_mask) |
3088 | 3088 | { |
3089 | 3089 | if (! (op1->architecture & current_arch_mask)) |
3090 | - return -1; | |
3090 | + return -1; | |
3091 | 3091 | } |
3092 | 3092 | else |
3093 | 3093 | { |
3094 | 3094 | if (op1->architecture & current_arch_mask) |
3095 | - return 1; | |
3095 | + return 1; | |
3096 | 3096 | else if (op0->architecture != op1->architecture) |
3097 | - return op0->architecture - op1->architecture; | |
3097 | + return op0->architecture - op1->architecture; | |
3098 | 3098 | } |
3099 | 3099 | |
3100 | 3100 | /* If a bit is set in both match and lose, there is something |
... | ... | @@ -3102,10 +3102,10 @@ compare_opcodes (const void *a, const void *b) |
3102 | 3102 | if (match0 & lose0) |
3103 | 3103 | { |
3104 | 3104 | fprintf |
3105 | - (stderr, | |
3106 | - /* xgettext:c-format */ | |
3107 | - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
3108 | - op0->name, match0, lose0); | |
3105 | + (stderr, | |
3106 | + /* xgettext:c-format */ | |
3107 | + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
3108 | + op0->name, match0, lose0); | |
3109 | 3109 | op0->lose &= ~op0->match; |
3110 | 3110 | lose0 = op0->lose; |
3111 | 3111 | } |
... | ... | @@ -3113,10 +3113,10 @@ compare_opcodes (const void *a, const void *b) |
3113 | 3113 | if (match1 & lose1) |
3114 | 3114 | { |
3115 | 3115 | fprintf |
3116 | - (stderr, | |
3117 | - /* xgettext:c-format */ | |
3118 | - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
3119 | - op1->name, match1, lose1); | |
3116 | + (stderr, | |
3117 | + /* xgettext:c-format */ | |
3118 | + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), | |
3119 | + op1->name, match1, lose1); | |
3120 | 3120 | op1->lose &= ~op1->match; |
3121 | 3121 | lose1 = op1->lose; |
3122 | 3122 | } |
... | ... | @@ -3130,7 +3130,7 @@ compare_opcodes (const void *a, const void *b) |
3130 | 3130 | int x1 = (match1 & x) != 0; |
3131 | 3131 | |
3132 | 3132 | if (x0 != x1) |
3133 | - return x1 - x0; | |
3133 | + return x1 - x0; | |
3134 | 3134 | } |
3135 | 3135 | |
3136 | 3136 | for (i = 0; i < 32; ++i) |
... | ... | @@ -3140,7 +3140,7 @@ compare_opcodes (const void *a, const void *b) |
3140 | 3140 | int x1 = (lose1 & x) != 0; |
3141 | 3141 | |
3142 | 3142 | if (x0 != x1) |
3143 | - return x1 - x0; | |
3143 | + return x1 - x0; | |
3144 | 3144 | } |
3145 | 3145 | |
3146 | 3146 | /* They are functionally equal. So as long as the opcode table is |
... | ... | @@ -3160,12 +3160,12 @@ compare_opcodes (const void *a, const void *b) |
3160 | 3160 | if (i) |
3161 | 3161 | { |
3162 | 3162 | if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
3163 | - return i; | |
3163 | + return i; | |
3164 | 3164 | else |
3165 | - fprintf (stderr, | |
3166 | - /* xgettext:c-format */ | |
3167 | - _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), | |
3168 | - op0->name, op1->name); | |
3165 | + fprintf (stderr, | |
3166 | + /* xgettext:c-format */ | |
3167 | + _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), | |
3168 | + op0->name, op1->name); | |
3169 | 3169 | } |
3170 | 3170 | |
3171 | 3171 | /* Fewer arguments are preferred. */ |
... | ... | @@ -3183,15 +3183,15 @@ compare_opcodes (const void *a, const void *b) |
3183 | 3183 | |
3184 | 3184 | if (p0 && p1) |
3185 | 3185 | { |
3186 | - /* There is a plus in both operands. Note that a plus | |
3187 | - sign cannot be the first character in args, | |
3188 | - so the following [-1]'s are valid. */ | |
3189 | - if (p0[-1] == 'i' && p1[1] == 'i') | |
3190 | - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ | |
3191 | - return 1; | |
3192 | - if (p0[1] == 'i' && p1[-1] == 'i') | |
3193 | - /* op0 is 1+i and op1 is i+1, so op0 goes first. */ | |
3194 | - return -1; | |
3186 | + /* There is a plus in both operands. Note that a plus | |
3187 | + sign cannot be the first character in args, | |
3188 | + so the following [-1]'s are valid. */ | |
3189 | + if (p0[-1] == 'i' && p1[1] == 'i') | |
3190 | + /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ | |
3191 | + return 1; | |
3192 | + if (p0[1] == 'i' && p1[-1] == 'i') | |
3193 | + /* op0 is 1+i and op1 is i+1, so op0 goes first. */ | |
3194 | + return -1; | |
3195 | 3195 | } |
3196 | 3196 | } |
3197 | 3197 | |
... | ... | @@ -3252,14 +3252,14 @@ build_hash_table (opcode_table, hash_table, num_opcodes) |
3252 | 3252 | for (i = 0; i < HASH_SIZE; ++i) |
3253 | 3253 | { |
3254 | 3254 | if (hash_count[i] < min_count) |
3255 | - min_count = hash_count[i]; | |
3256 | - if (hash_count[i] > max_count) | |
3257 | - max_count = hash_count[i]; | |
3258 | - total += hash_count[i]; | |
3255 | + min_count = hash_count[i]; | |
3256 | + if (hash_count[i] > max_count) | |
3257 | + max_count = hash_count[i]; | |
3258 | + total += hash_count[i]; | |
3259 | 3259 | } |
3260 | 3260 | |
3261 | 3261 | printf ("Opcode hash table stats: min %d, max %d, ave %f\n", |
3262 | - min_count, max_count, (double) total / HASH_SIZE); | |
3262 | + min_count, max_count, (double) total / HASH_SIZE); | |
3263 | 3263 | } |
3264 | 3264 | #endif |
3265 | 3265 | } | ... | ... |
sparc.ld
1 | 1 | OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", |
2 | - "elf32-sparc") | |
2 | + "elf32-sparc") | |
3 | 3 | OUTPUT_ARCH(sparc) |
4 | 4 | SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib); |
5 | 5 | ENTRY(_start) |
... | ... | @@ -7,13 +7,13 @@ SECTIONS |
7 | 7 | { |
8 | 8 | /* Read-only sections, merged into text segment: */ |
9 | 9 | . = 0x60000000 + SIZEOF_HEADERS; |
10 | - .interp : { *(.interp) } | |
11 | - .hash : { *(.hash) } | |
12 | - .dynsym : { *(.dynsym) } | |
13 | - .dynstr : { *(.dynstr) } | |
14 | - .gnu.version : { *(.gnu.version) } | |
15 | - .gnu.version_d : { *(.gnu.version_d) } | |
16 | - .gnu.version_r : { *(.gnu.version_r) } | |
10 | + .interp : { *(.interp) } | |
11 | + .hash : { *(.hash) } | |
12 | + .dynsym : { *(.dynsym) } | |
13 | + .dynstr : { *(.dynstr) } | |
14 | + .gnu.version : { *(.gnu.version) } | |
15 | + .gnu.version_d : { *(.gnu.version_d) } | |
16 | + .gnu.version_r : { *(.gnu.version_r) } | |
17 | 17 | .rel.text : |
18 | 18 | { *(.rel.text) *(.rel.gnu.linkonce.t*) } |
19 | 19 | .rela.text : |
... | ... | @@ -26,21 +26,21 @@ SECTIONS |
26 | 26 | { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } |
27 | 27 | .rela.rodata : |
28 | 28 | { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } |
29 | - .rel.got : { *(.rel.got) } | |
30 | - .rela.got : { *(.rela.got) } | |
31 | - .rel.ctors : { *(.rel.ctors) } | |
32 | - .rela.ctors : { *(.rela.ctors) } | |
33 | - .rel.dtors : { *(.rel.dtors) } | |
34 | - .rela.dtors : { *(.rela.dtors) } | |
35 | - .rel.init : { *(.rel.init) } | |
36 | - .rela.init : { *(.rela.init) } | |
37 | - .rel.fini : { *(.rel.fini) } | |
38 | - .rela.fini : { *(.rela.fini) } | |
39 | - .rel.bss : { *(.rel.bss) } | |
40 | - .rela.bss : { *(.rela.bss) } | |
41 | - .rel.plt : { *(.rel.plt) } | |
42 | - .rela.plt : { *(.rela.plt) } | |
43 | - .init : { *(.init) } =0x47ff041f | |
29 | + .rel.got : { *(.rel.got) } | |
30 | + .rela.got : { *(.rela.got) } | |
31 | + .rel.ctors : { *(.rel.ctors) } | |
32 | + .rela.ctors : { *(.rela.ctors) } | |
33 | + .rel.dtors : { *(.rel.dtors) } | |
34 | + .rela.dtors : { *(.rela.dtors) } | |
35 | + .rel.init : { *(.rel.init) } | |
36 | + .rela.init : { *(.rela.init) } | |
37 | + .rel.fini : { *(.rel.fini) } | |
38 | + .rela.fini : { *(.rela.fini) } | |
39 | + .rel.bss : { *(.rel.bss) } | |
40 | + .rela.bss : { *(.rela.bss) } | |
41 | + .rel.plt : { *(.rel.plt) } | |
42 | + .rela.plt : { *(.rela.plt) } | |
43 | + .init : { *(.init) } =0x47ff041f | |
44 | 44 | .text : |
45 | 45 | { |
46 | 46 | *(.text) |
... | ... | @@ -74,7 +74,7 @@ SECTIONS |
74 | 74 | { |
75 | 75 | *(.dtors) |
76 | 76 | } |
77 | - .plt : { *(.plt) } | |
77 | + .plt : { *(.plt) } | |
78 | 78 | .got : { *(.got.plt) *(.got) } |
79 | 79 | .dynamic : { *(.dynamic) } |
80 | 80 | /* We want the small data sections together, so single-instruction offsets | ... | ... |
sparc64.ld
1 | 1 | OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", |
2 | - "elf64-sparc") | |
2 | + "elf64-sparc") | |
3 | 3 | OUTPUT_ARCH(sparc:v9) |
4 | 4 | SEARCH_DIR(/lib64); SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib64); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib64); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib); |
5 | 5 | ENTRY(_start) |
... | ... | @@ -7,13 +7,13 @@ SECTIONS |
7 | 7 | { |
8 | 8 | /* Read-only sections, merged into text segment: */ |
9 | 9 | . = 0x60000000 + SIZEOF_HEADERS; |
10 | - .interp : { *(.interp) } | |
11 | - .hash : { *(.hash) } | |
12 | - .dynsym : { *(.dynsym) } | |
13 | - .dynstr : { *(.dynstr) } | |
14 | - .gnu.version : { *(.gnu.version) } | |
15 | - .gnu.version_d : { *(.gnu.version_d) } | |
16 | - .gnu.version_r : { *(.gnu.version_r) } | |
10 | + .interp : { *(.interp) } | |
11 | + .hash : { *(.hash) } | |
12 | + .dynsym : { *(.dynsym) } | |
13 | + .dynstr : { *(.dynstr) } | |
14 | + .gnu.version : { *(.gnu.version) } | |
15 | + .gnu.version_d : { *(.gnu.version_d) } | |
16 | + .gnu.version_r : { *(.gnu.version_r) } | |
17 | 17 | .rel.text : |
18 | 18 | { *(.rel.text) *(.rel.gnu.linkonce.t*) } |
19 | 19 | .rela.text : |
... | ... | @@ -26,21 +26,21 @@ SECTIONS |
26 | 26 | { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } |
27 | 27 | .rela.rodata : |
28 | 28 | { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } |
29 | - .rel.got : { *(.rel.got) } | |
30 | - .rela.got : { *(.rela.got) } | |
31 | - .rel.ctors : { *(.rel.ctors) } | |
32 | - .rela.ctors : { *(.rela.ctors) } | |
33 | - .rel.dtors : { *(.rel.dtors) } | |
34 | - .rela.dtors : { *(.rela.dtors) } | |
35 | - .rel.init : { *(.rel.init) } | |
36 | - .rela.init : { *(.rela.init) } | |
37 | - .rel.fini : { *(.rel.fini) } | |
38 | - .rela.fini : { *(.rela.fini) } | |
39 | - .rel.bss : { *(.rel.bss) } | |
40 | - .rela.bss : { *(.rela.bss) } | |
41 | - .rel.plt : { *(.rel.plt) } | |
42 | - .rela.plt : { *(.rela.plt) } | |
43 | - .init : { *(.init) } =0x47ff041f | |
29 | + .rel.got : { *(.rel.got) } | |
30 | + .rela.got : { *(.rela.got) } | |
31 | + .rel.ctors : { *(.rel.ctors) } | |
32 | + .rela.ctors : { *(.rela.ctors) } | |
33 | + .rel.dtors : { *(.rel.dtors) } | |
34 | + .rela.dtors : { *(.rela.dtors) } | |
35 | + .rel.init : { *(.rel.init) } | |
36 | + .rela.init : { *(.rela.init) } | |
37 | + .rel.fini : { *(.rel.fini) } | |
38 | + .rela.fini : { *(.rela.fini) } | |
39 | + .rel.bss : { *(.rel.bss) } | |
40 | + .rela.bss : { *(.rela.bss) } | |
41 | + .rel.plt : { *(.rel.plt) } | |
42 | + .rela.plt : { *(.rela.plt) } | |
43 | + .init : { *(.init) } =0x47ff041f | |
44 | 44 | .text : |
45 | 45 | { |
46 | 46 | *(.text) |
... | ... | @@ -82,7 +82,7 @@ SECTIONS |
82 | 82 | { |
83 | 83 | *(.dtors) |
84 | 84 | } |
85 | - .plt : { *(.plt) } | |
85 | + .plt : { *(.plt) } | |
86 | 86 | .got : { *(.got.plt) *(.got) } |
87 | 87 | .dynamic : { *(.dynamic) } |
88 | 88 | /* We want the small data sections together, so single-instruction offsets | ... | ... |