gwj / at91sam9263 · Commits

Commit a750fc0b9184a520d00d9e949160a0c6d3232ecd

Authored by j_mayer
1 parent 08fa4bab

Great rework and cleanups to ease PowerPC implementations definitions. 

* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 11 changed files with 4459 additions and 3302 deletions
hw/ppc.c
  View file @a750fc0
... ... @@ -376,11 +376,11 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
376 376 /* Level sensitive - active high */
377 377 #if defined(PPC_DEBUG_IRQ)
378 378 if (loglevel & CPU_LOG_INT) {
379   - fprintf(logfile, "%s: set the external IRQ state to %d\n",
  379 + fprintf(logfile, "%s: set the debug pin state to %d\n",
380 380 __func__, level);
381 381 }
382 382 #endif
383   - ppc_set_irq(env, EXCP_40x_DEBUG, level);
  383 + ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
384 384 break;
385 385 default:
386 386 /* Unknown pin - do nothing */
... ... @@ -904,6 +904,9 @@ struct ppc_dcrn_t {
904 904 void *opaque;
905 905 };
906 906  
  907 +/* XXX: on 460, DCR addresses are 32 bits wide,
  908 + * using DCRIPR to get the 22 upper bits of the DCR address
  909 + */
907 910 #define DCRN_NB 1024
908 911 struct ppc_dcr_t {
909 912 ppc_dcrn_t dcrn[DCRN_NB];
... ...
linux-user/main.c
  View file @a750fc0
... ... @@ -712,6 +712,17 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env)
712 712 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
713 713 }
714 714  
  715 +/* XXX: to be fixed */
  716 +int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
  717 +{
  718 + return -1;
  719 +}
  720 +
  721 +int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
  722 +{
  723 + return -1;
  724 +}
  725 +
715 726 void cpu_loop(CPUPPCState *env)
716 727 {
717 728 target_siginfo_t info;
... ... @@ -761,7 +772,7 @@ void cpu_loop(CPUPPCState *env)
761 772 case EXCP_MACHINE_CHECK:
762 773 fprintf(stderr, "Machine check exeption... Stop emulation\n");
763 774 if (loglevel)
764   - fprintf(logfile, "RESET asked... Stop emulation\n");
  775 + fprintf(logfile, "Machine check exception. Stop emulation\n");
765 776 info.si_signo = TARGET_SIGBUS;
766 777 info.si_errno = 0;
767 778 info.si_code = TARGET_BUS_OBJERR;
... ... @@ -914,7 +925,7 @@ void cpu_loop(CPUPPCState *env)
914 925 info.si_code = TARGET_ILL_ILLOPC;
915 926 break;
916 927 case EXCP_INVAL_LSWX:
917   - info.si_code = TARGET_ILL_ILLOPN;
  928 + info.si_code = TARGET_ILL_ILLOPN;
918 929 break;
919 930 case EXCP_INVAL_SPR:
920 931 info.si_code = TARGET_ILL_PRVREG;
... ... @@ -1003,7 +1014,7 @@ void cpu_loop(CPUPPCState *env)
1003 1014 if (loglevel)
1004 1015 fprintf(logfile, "Tried to go into supervisor mode !\n");
1005 1016 abort();
1006   - }
  1017 + }
1007 1018 break;
1008 1019 case EXCP_BRANCH:
1009 1020 /* We stopped because of a jump... */
... ...
target-ppc/STATUS
  View file @a750fc0
... ... @@ -4,267 +4,462 @@ The goal of this file is to provide a reference status to avoid regressions.
4 4 ===============================================================================
5 5 PowerPC core emulation status
6 6  
7   -32 bits PowerPC
8   -PowerPC 601:
9   -INSN
10   -SPR
11   -MMU
12   -EXCP
13   -
14   -PowerPC 602:
15   -INSN
16   -SPR
17   -MMU
18   -EXCP
19   -
20   -PowerPC 603:
21   -INSN OK
22   -SPR OK
23   -MMU OK
24   -EXCP OK
25   -
26   -PowerPC 604:
27   -INSN OK
28   -SPR OK
29   -MMU OK
30   -EXCP OK
31   -
32   -PowerPC 740:
33   -INSN OK
34   -SPR OK
35   -MMU OK
36   -EXCP OK
37   -
38   -PowerPC 745:
39   -INSN
40   -SPR
41   -MMU
42   -EXCP
43   -
44   -PowerPC 750:
45   -INSN OK
46   -SPR OK
47   -MMU OK
48   -EXCP OK
49   -
50   -PowerPC 755:
51   -INSN
52   -SPR
53   -MMU
54   -EXCP
  7 +INSN: instruction set.
  8 + OK => all instructions are emulated
  9 + KO => some insns are missing or some should be removed
  10 + ? => unchecked
  11 +SPR: special purpose registers set
  12 + OK => all SPR registered (but some may be fake)
  13 + KO => some SPR are missing or should be removed
  14 + ? => uncheked
  15 +MSR: MSR bits definitions
  16 + OK => all MSR bits properly defined
  17 + KO => MSR definition is incorrect
  18 + ? => unchecked
  19 +IRQ: input signals definitions (mostly interrupts)
  20 + OK => input signals are properly defined
  21 + KO => input signals are not implemented (system emulation does not work)
  22 + ? => input signals definitions may be incorrect
  23 +MMU: MMU model implementation
  24 + OK => MMU model is implemented and Linux is able to boot
  25 + KO => MMU model not implemented or bugged
  26 + ? => MMU model not tested
  27 +EXCP: exceptions model implementation
  28 + OK => exception model is implemented and Linux is able to boot
  29 + KO => exception model not implemented or known to be buggy
  30 + ? => exception model may be incorrect or is untested
55 31  
56   -PowerPC 7400:
57   -INSN KO
58   -SPR KO
59   -MMU OK
60   -EXCP OK
  32 +Embedded PowerPC cores
  33 +***
  34 +PowerPC 401:
  35 +INSN OK
  36 +SPR OK 401A1
  37 +MSR OK
  38 +IRQ KO partially implemented
  39 +MMU OK
  40 +EXCP ?
61 41  
62   -PowerPC 7410:
63   -INSN KO
64   -SPR KO
65   -MMU OK
66   -EXCP OK
67   -
68   -PowerPC 7450:
69   -INSN KO
70   -SPR KO
71   -MMU OK
72   -EXCP OK
73   -
74   -PowerPC 7455:
75   -INSN KO
76   -SPR KO
77   -MMU OK
78   -EXCP OK
79   -
80   -PowerPC 7457:
81   -INSN KO
82   -SPR KO
83   -MMU OK
84   -EXCP OK
85   -
86   -PowerPC 7457A:
87   -INSN KO
88   -SPR KO
89   -MMU OK
90   -EXCP OK
  42 +PowerPC 401x2:
  43 +INSN OK
  44 +SPR OK 401B2 401C2 401D2 401E2 401F2
  45 +MSR OK
  46 +IRQ KO partially implemented
  47 +MMU OK
  48 +EXCP ?
91 49  
92   -64 bits PowerPC
93   -PowerPC 970:
94   -INSN KO
95   -SPR KO
96   -MMU KO
97   -EXCP KO
98   -
99   -PowerPC 620: (lack of precise informations)
100   -INSN KO
101   -SPR KO
102   -MMU KO
103   -EXCP KO
104   -
105   -PowerPC 630: (lack of precise informations)
106   -INSN KO
107   -SPR KO
108   -MMU KO
109   -EXCP KO
110   -
111   -PowerPC 631: (lack of precise informations)
112   -INSN KO
113   -SPR KO
114   -MMU KO
115   -EXCP KO
116   -
117   -POWER4: (lack of precise informations)
118   -INSN KO
119   -SPR KO
120   -MMU KO
121   -EXCP KO
122   -
123   -POWER4+: (lack of precise informations)
124   -INSN KO
125   -SPR KO
126   -MMU KO
127   -EXCP KO
128   -
129   -POWER5: (lack of precise informations)
130   -INSN KO
131   -SPR KO
132   -MMU KO
133   -EXCP KO
134   -
135   -POWER5+: (lack of precise informations)
136   -INSN KO
137   -SPR KO
138   -MMU KO
139   -EXCP KO
140   -
141   -POWER6: (lack of precise informations)
142   -INSN KO
143   -SPR KO
144   -MMU KO
145   -EXCP KO
146   -
147   -RS64: (lack of precise informations)
148   -INSN KO
149   -SPR KO
150   -MMU KO
151   -EXCP KO
152   -
153   -RS64-II: (lack of precise informations)
154   -INSN KO
155   -SPR KO
156   -MMU KO
157   -EXCP KO
158   -
159   -RS64-III: (lack of precise informations)
160   -INSN KO
161   -SPR KO
162   -MMU KO
163   -EXCP KO
164   -
165   -RS64-IV: (lack of precise informations)
166   -INSN KO
167   -SPR KO
168   -MMU KO
169   -EXCP KO
  50 +PowerPC IOP480:
  51 +INSN OK
  52 +SPR OK IOP480
  53 +MSR OK
  54 +IRQ KO partially implemented
  55 +MMU OK
  56 +EXCP ?
170 57  
171   -Embedded PowerPC cores
172   -PowerPC 401:
173   -INSN OK
174   -SPR OK
175   -MMU OK
176   -EXCP ?
  58 +To be checked: 401G2 401B3 Cobra
177 59  
  60 +***
178 61 PowerPC 403:
179   -INSN OK
180   -SPR OK
181   -MMU OK
182   -EXCP ?
  62 +INSN OK
  63 +SPR OK 403GA 403GB
  64 +MMU OK
  65 +MSR OK
  66 +IRQ KO not implemented
  67 +EXCP ?
183 68  
  69 +PowerPC 403GCX:
  70 +INSN OK
  71 +SPR OK 403GCX
  72 +MMU OK
  73 +MSR OK
  74 +IRQ KO not implemented
  75 +EXCP ?
  76 +
  77 +To be checked: 403GC
  78 +
  79 +***
184 80 PowerPC 405:
185   -INSN OK
186   -SPR OK
187   -MMU OK
188   -EXCP OK
  81 +Checked: 405CRa 405CRb 405CRc 405EP 405GPa 405GPb 405GPc 405GPd 405GPe 405GPR
  82 + Npe405H Npe405H2 Npe405L
  83 +INSN OK
  84 +SPR OK
  85 +MSR OK
  86 +IRQ OK
  87 +MMU OK
  88 +EXCP OK
  89 +=> Linux 2.4 boots (at least 1 proprietary firmware).
  90 +
  91 +To be checked: 405D2 405D4 405EZ 405LP Npe4GS3 STB03 STB04 STB25
  92 + x2vp4 x2vp7 x2vp20 x2vp50
  93 +
  94 +XXX: find what is IBM e407b4
189 95  
  96 +***
190 97 PowerPC 440:
  98 +Checked: 440EPa 440EPb 440GXa 440GXb 440GXc 440GXf 440SP 440SP2
  99 +INSN OK
  100 +SPR OK
  101 +MSR OK
  102 +IRQ KO not implemented
  103 +MMU ?
  104 +EXCP ?
  105 +
  106 +PowerPC 440GP:
  107 +Checked: 440GPb 440GPc
  108 +INSN OK
  109 +SPR OK
  110 +MSR OK
  111 +IRQ KO not implemented
  112 +MMU ?
  113 +EXCP ?
  114 +
  115 +PowerPC 440x4:
  116 +Checked: 440A4 440B4 440G4 440H4
191 117 INSN OK
192 118 SPR OK
  119 +MSR OK
  120 +IRQ KO not implemented
193 121 MMU ?
194 122 EXCP ?
195 123  
196   -PowerPC 460: (lack of precise informations)
  124 +PowerPC 440x5:
  125 +Checked: 440A5 440F5 440G5 440H6 440GRa
  126 +INSN OK
  127 +SPR OK
  128 +MSR OK
  129 +IRQ KO not implemented
  130 +MMU ?
  131 +EXCP ?
  132 +
  133 +To be checked: 440EPx 440GRx 440SPE
  134 +
  135 +***
  136 +PowerPC 460: (disabled: lack of detailed specifications)
  137 +INSN KO
  138 +SPR KO
  139 +MSR KO
  140 +IRQ KO
  141 +MMU KO
  142 +EXCP KO
  143 +
  144 +PowerPC 460F: (disabled: lack of detailed specifications)
197 145 INSN KO
198 146 SPR KO
  147 +MSR KO
  148 +IRQ KO
199 149 MMU KO
200 150 EXCP KO
201 151  
202   -Freescale (to be completed) ...
  152 +***
  153 +PowerPC e200: (not implemented)
  154 +INSN KO
  155 +SPR KO
  156 +MSR KO
  157 +IRQ KO
  158 +MMU KO
  159 +EXCP KO
203 160  
204   -Original POWER
205   -POWER: (lack of precise informations)
  161 +***
  162 +PowerPC e300: (not implemented)
206 163 INSN KO
207 164 SPR KO
  165 +MSR KO
  166 +IRQ KO
208 167 MMU KO
209 168 EXCP KO
210 169  
211   -POWER2: (lack of precise informations)
  170 +***
  171 +PowerPC e500: (not implemented)
212 172 INSN KO
213 173 SPR KO
  174 +MSR KO
  175 +IRQ KO
214 176 MMU KO
215 177 EXCP KO
216 178  
217   -PowerPC CPU known to work (ie booting at least Linux 2.4):
218   -* main stream PowerPC cores
219   -- PowerPC 603 & derivatives
220   -- PowerPC 604 & derivatives
221   -- PowerPC 740 & derivatives
222   -- PowerPC 750 & derivatives
223   -- PowerPC 405
224   -
225   -PowerPC that should work but are not supported by standard Linux kernel
226   -(then remain mostly untested)
227   -- PowerPC 745
228   -- PowerPC 755
229   -
230   -Work in progress:
231   -* embedded PowerPC cores
232   -- BookE PowerPC
233   -- e500 core (Freescale PowerQUICC)
234   -* main stream PowerPC cores
235   -- PowerPC 601
236   -- PowerPC 602
  179 +***
  180 +PowerPC e600: (not implemented)
  181 +INSN KO
  182 +SPR KO
  183 +MSR KO
  184 +IRQ KO
  185 +MMU KO
  186 +EXCP KO
237 187  
238   -TODO:
239   -* embedded PowerPC cores
240   -- PowerPC 401
241   -- PowerPC 403
242   -- PowerPC 440
243   -- PowerPC 460
244   -* main stream PowerPC cores
245   -- PowerPC 7400 (aka G4)
246   -- PowerPC 7410
247   -- PowerPC 7450
248   -- PowerPC 7455
249   -- PowerPC 7457
250   -- PowerPC 7457A
251   -* original POWER
252   -- POWER
253   -- POWER2
254   -* 64 bits PowerPC cores
255   -- PowerPC 620
256   -- PowerPC 630 (aka POWER3)
257   -- PowerPC 631 (aka POWER3+)
258   -- POWER4
259   -- POWER4+
260   -- POWER5
261   -- POWER5+
262   -- PowerPC 970
263   -* RS64 series
264   -- RS64
265   -- RS64-II
266   -- RS64-III
267   -- RS64-IV
  188 +***
  189 +32 bits PowerPC
  190 +PowerPC 601: (601 601v2)
  191 +INSN OK
  192 +SPR OK is HID15 only on 601v2 ?
  193 +MSR OK
  194 +IRQ KO not implemented
  195 +MMU ?
  196 +EXCP ?
  197 +Remarks: some instructions should have a specific behavior (not implemented)
  198 +
  199 +PowerPC 602: 602
  200 +INSN OK
  201 +SPR OK
  202 +MSR OK
  203 +IRQ OK
  204 +MMU ?
  205 +EXCP ? at least timer and external interrupt are OK
  206 +Remarks: Linux crashes when entering user-mode. But it seems it does not
  207 + know about this CPU. As this CPU is close to 603e, it should be OK.
  208 +
  209 +PowerPC 603: (603)
  210 +INSN OK
  211 +SPR OK
  212 +MSR OK
  213 +IRQ OK
  214 +MMU OK
  215 +EXCP OK
  216 +Remarks: Linux 2.4 boots and properly recognizes the CPU
  217 +
  218 +PowerPC 603e: (603e11)
  219 +INSN OK
  220 +SPR OK
  221 +MSR OK
  222 +IRQ OK
  223 +MMU OK
  224 +EXCP OK
  225 +Remarks: Linux 2.4 boots and properly recognizes the CPU
  226 +
  227 +PowerPC G2:
  228 +INSN OK
  229 +SPR OK
  230 +MSR OK
  231 +IRQ OK
  232 +MMU OK
  233 +EXCP OK
  234 +Remarks: Linux 2.4 boots, recognizes the CPU as a 82xx.
  235 +
  236 +PowerPC G2le:
  237 +INSN OK
  238 +SPR OK
  239 +MSR OK
  240 +IRQ OK
  241 +MMU OK
  242 +EXCP OK
  243 +Remarks: Linux 2.4 does not boots. Same symptoms as 602.
  244 +
  245 +PowerPC 604:
  246 +INSN OK
  247 +SPR OK
  248 +MSR OK
  249 +IRQ OK
  250 +MMU OK
  251 +EXCP OK
  252 +Remarks: Linux 2.4 boots and properly recognizes the CPU.
  253 +
  254 +PowerPC 7x0:
  255 +INSN OK
  256 +SPR OK
  257 +MSR OK
  258 +IRQ OK
  259 +MMU OK
  260 +EXCP OK
  261 +Remarks: Linux 2.4 boots and properly recognizes the CPU.
  262 +
  263 +PowerPC 750fx:
  264 +INSN OK
  265 +SPR OK
  266 +MSR OK
  267 +IRQ OK
  268 +MMU OK
  269 +EXCP OK
  270 +Remarks: Linux 2.4 boots but does not properly recognizes the CPU.
  271 +
  272 +PowerPC 7x5:
  273 +INSN ?
  274 +SPR ?
  275 +MSR ?
  276 +IRQ OK
  277 +MMU ?
  278 +EXCP OK
  279 +=> Linux 2.4 does not boot.
  280 +
  281 +PowerPC 7400:
  282 +INSN KO Altivec missing
  283 +SPR OK
  284 +MSR OK
  285 +IRQ OK
  286 +MMU OK
  287 +EXCP ? Altivec, ...
  288 +=> Linux 2.4 boots and properly recognize the CPU.
  289 +
  290 +PowerPC 7410:
  291 +INSN KO Altivec missing
  292 +SPR OK
  293 +MSR OK
  294 +IRQ OK
  295 +MMU OK
  296 +EXCP ? Altivec, ...
  297 +=> Linux 2.4 boots and properly recognize the CPU.
  298 + Note that UM says tlbld & tlbli are implemented bus this may be a mistake
  299 + as TLB load are managed by the hardware and it does not implement the
  300 + needed registers.
  301 +
  302 +PowerPC 7441:
  303 +INSN KO Altivec missing + TLB load insns missing
  304 +SPR OK
  305 +MSR OK
  306 +IRQ OK
  307 +MMU KO not implemented
  308 +EXCP ? Altivec, ...
  309 +
  310 +PowerPC 7450/7451:
  311 +INSN KO Altivec missing + TLB load insns missing
  312 +SPR OK
  313 +MSR OK
  314 +IRQ OK
  315 +MMU KO not implemented
  316 +EXCP ? Altivec, ...
  317 +
  318 +PowerPC 7445/7447:
  319 +INSN KO Altivec missing + TLB load insns missing
  320 +SPR OK
  321 +MSR OK
  322 +IRQ OK
  323 +MMU KO not implemented
  324 +EXCP ? Altivec, ...
  325 +
  326 +PowerPC 7455/7457:
  327 +INSN KO Altivec missing + TLB load insns missing
  328 +SPR OK
  329 +MSR OK
  330 +IRQ OK
  331 +MMU KO not implemented
  332 +EXCP ? Altivec, ...
  333 +
  334 +64 bits PowerPC
  335 +PowerPC 620: (disabled)
  336 +INSN KO
  337 +SPR KO
  338 +MSR ?
  339 +IRQ KO
  340 +MMU KO
  341 +EXCP KO
  342 +
  343 +PowerPC 970: (disabled)
  344 +INSN KO Altivec missing and more
  345 +SPR KO
  346 +MSR ?
  347 +IRQ OK
  348 +MMU KO partially implemented
  349 +EXCP KO
  350 +
  351 +PowerPC 970FX: (disabled)
  352 +INSN KO Altivec missing and more
  353 +SPR KO
  354 +MSR ?
  355 +IRQ OK
  356 +MMU KO partially implemented
  357 +EXCP KO
  358 +
  359 +PowerPC 630: (disabled: lack of detailed specifications)
  360 +INSN KO
  361 +SPR KO
  362 +MSR KO
  363 +IRQ KO
  364 +MMU KO
  365 +EXCP KO
  366 +
  367 +PowerPC 631: (disabled: lack of detailed specifications)
  368 +INSN KO
  369 +SPR KO
  370 +MSR KO
  371 +IRQ KO
  372 +MMU KO
  373 +EXCP KO
  374 +
  375 +POWER4: (disabled: lack of detailed specifications)
  376 +INSN KO
  377 +SPR KO
  378 +MSR KO
  379 +IRQ KO
  380 +MMU KO
  381 +EXCP KO
  382 +
  383 +POWER4+: (disabled: lack of detailed specifications)
  384 +INSN KO
  385 +SPR KO
  386 +MSR KO
  387 +IRQ KO
  388 +MMU KO
  389 +EXCP KO
  390 +
  391 +POWER5: (disabled: lack of detailed specifications)
  392 +INSN KO
  393 +SPR KO
  394 +MSR KO
  395 +IRQ KO
  396 +MMU KO
  397 +EXCP KO
  398 +
  399 +POWER5+: (disabled: lack of detailed specifications)
  400 +INSN KO
  401 +SPR KO
  402 +MSR KO
  403 +IRQ KO
  404 +MMU KO
  405 +EXCP KO
  406 +
  407 +POWER6: (disabled: lack of detailed specifications)
  408 +INSN KO
  409 +SPR KO
  410 +MSR KO
  411 +IRQ KO
  412 +MMU KO
  413 +EXCP KO
  414 +
  415 +RS64: (disabled: lack of detailed specifications)
  416 +INSN KO
  417 +SPR KO
  418 +MSR KO
  419 +IRQ KO
  420 +MMU KO
  421 +EXCP KO
  422 +
  423 +RS64-II: (disabled: lack of detailed specifications)
  424 +INSN KO
  425 +SPR KO
  426 +MSR KO
  427 +IRQ KO
  428 +MMU KO
  429 +EXCP KO
  430 +
  431 +RS64-III: (disabled: lack of detailed specifications)
  432 +INSN KO
  433 +SPR KO
  434 +MSR KO
  435 +IRQ KO
  436 +MMU KO
  437 +EXCP KO
  438 +
  439 +RS64-IV: (disabled: lack of detailed specifications)
  440 +INSN KO
  441 +SPR KO
  442 +MSR KO
  443 +IRQ KO
  444 +MMU KO
  445 +EXCP KO
  446 +
  447 +Original POWER
  448 +POWER: (disabled: lack of detailed specifications)
  449 +INSN KO
  450 +SPR KO
  451 +MSR KO
  452 +IRQ KO
  453 +MMU KO
  454 +EXCP KO
  455 +
  456 +POWER2: (disabled: lack of detailed specifications)
  457 +INSN KO
  458 +SPR KO
  459 +MSR KO
  460 +IRQ KO
  461 +MMU KO
  462 +EXCP KO
268 463  
269 464 ===============================================================================
270 465 PowerPC microcontrollers emulation status
... ...
target-ppc/cpu.h
  View file @a750fc0
... ... @@ -89,528 +89,89 @@ typedef uint32_t ppc_gpr_t;
89 89 #define DCACHE_LINE_SIZE 32
90 90  
91 91 /*****************************************************************************/
92   -/* PVR definitions for most known PowerPC */
  92 +/* MMU model */
93 93 enum {
94   - /* PowerPC 401 cores */
95   - CPU_PPC_401A1 = 0x00210000,
96   - CPU_PPC_401B2 = 0x00220000,
97   -#if 0
98   - CPU_PPC_401B3 = xxx,
99   -#endif
100   - CPU_PPC_401C2 = 0x00230000,
101   - CPU_PPC_401D2 = 0x00240000,
102   - CPU_PPC_401E2 = 0x00250000,
103   - CPU_PPC_401F2 = 0x00260000,
104   - CPU_PPC_401G2 = 0x00270000,
105   -#if 0
106   - CPU_PPC_401GF = xxx,
107   -#endif
108   -#define CPU_PPC_401 CPU_PPC_401G2
109   - CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
110   - CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
111   - /* PowerPC 403 cores */
112   - CPU_PPC_403GA = 0x00200011,
113   - CPU_PPC_403GB = 0x00200100,
114   - CPU_PPC_403GC = 0x00200200,
115   - CPU_PPC_403GCX = 0x00201400,
116   -#if 0
117   - CPU_PPC_403GP = xxx,
118   -#endif
119   -#define CPU_PPC_403 CPU_PPC_403GCX
120   - /* PowerPC 405 cores */
121   -#if 0
122   - CPU_PPC_405A3 = xxx,
123   -#endif
124   -#if 0
125   - CPU_PPC_405A4 = xxx,
126   -#endif
127   -#if 0
128   - CPU_PPC_405B3 = xxx,
129   -#endif
130   - CPU_PPC_405D2 = 0x20010000,
131   - CPU_PPC_405D4 = 0x41810000,
132   - CPU_PPC_405CR = 0x40110145,
133   -#define CPU_PPC_405GP CPU_PPC_405CR
134   - CPU_PPC_405EP = 0x51210950,
135   -#if 0
136   - CPU_PPC_405EZ = xxx,
137   -#endif
138   - CPU_PPC_405GPR = 0x50910951,
139   -#if 0
140   - CPU_PPC_405LP = xxx,
141   -#endif
142   -#define CPU_PPC_405 CPU_PPC_405D4
143   - CPU_PPC_NPE405H = 0x414100C0,
144   - CPU_PPC_NPE405H2 = 0x41410140,
145   - CPU_PPC_NPE405L = 0x416100C0,
146   -#if 0
147   - CPU_PPC_LC77700 = xxx,
148   -#endif
149   - /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
150   -#if 0
151   - CPU_PPC_STB01000 = xxx,
152   -#endif
153   -#if 0
154   - CPU_PPC_STB01010 = xxx,
155   -#endif
156   -#if 0
157   - CPU_PPC_STB0210 = xxx,
158   -#endif
159   - CPU_PPC_STB03 = 0x40310000,
160   -#if 0
161   - CPU_PPC_STB043 = xxx,
162   -#endif
163   -#if 0
164   - CPU_PPC_STB045 = xxx,
165   -#endif
166   - CPU_PPC_STB25 = 0x51510950,
167   -#if 0
168   - CPU_PPC_STB130 = xxx,
169   -#endif
170   - /* Xilinx cores */
171   - CPU_PPC_X2VP4 = 0x20010820,
172   -#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
173   - CPU_PPC_X2VP20 = 0x20010860,
174   -#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
175   - /* PowerPC 440 cores */
176   - CPU_PPC_440EP = 0x422218D3,
177   -#define CPU_PPC_440GR CPU_PPC_440EP
178   - CPU_PPC_440GP = 0x40120481,
179   -#if 0
180   - CPU_PPC_440GRX = xxx,
181   -#endif
182   - CPU_PPC_440GX = 0x51B21850,
183   - CPU_PPC_440GXc = 0x51B21892,
184   - CPU_PPC_440GXf = 0x51B21894,
185   - CPU_PPC_440SP = 0x53221850,
186   - CPU_PPC_440SP2 = 0x53221891,
187   - CPU_PPC_440SPE = 0x53421890,
188   - /* PowerPC 460 cores */
189   -#if 0
190   - CPU_PPC_464H90 = xxx,
191   -#endif
192   -#if 0
193   - CPU_PPC_464H90FP = xxx,
194   -#endif
195   - /* PowerPC MPC 5xx cores */
196   - CPU_PPC_5xx = 0x00020020,
197   - /* PowerPC MPC 8xx cores (aka PowerQUICC) */
198   - CPU_PPC_8xx = 0x00500000,
199   - /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
200   - CPU_PPC_82xx_HIP3 = 0x00810101,
201   - CPU_PPC_82xx_HIP4 = 0x80811014,
202   - CPU_PPC_827x = 0x80822013,
203   - /* eCores */
204   - CPU_PPC_e200 = 0x81120000,
205   - CPU_PPC_e500v110 = 0x80200010,
206   - CPU_PPC_e500v120 = 0x80200020,
207   - CPU_PPC_e500v210 = 0x80210010,
208   - CPU_PPC_e500v220 = 0x80210020,
209   -#define CPU_PPC_e500 CPU_PPC_e500v220
210   - CPU_PPC_e600 = 0x80040010,
211   - /* PowerPC 6xx cores */
212   - CPU_PPC_601 = 0x00010001,
213   - CPU_PPC_602 = 0x00050100,
214   - CPU_PPC_603 = 0x00030100,
215   - CPU_PPC_603E = 0x00060101,
216   - CPU_PPC_603P = 0x00070000,
217   - CPU_PPC_603E7v = 0x00070100,
218   - CPU_PPC_603E7v2 = 0x00070201,
219   - CPU_PPC_603E7 = 0x00070200,
220   - CPU_PPC_603R = 0x00071201,
221   - CPU_PPC_G2 = 0x00810011,
222   - CPU_PPC_G2H4 = 0x80811010,
223   - CPU_PPC_G2gp = 0x80821010,
224   - CPU_PPC_G2ls = 0x90810010,
225   - CPU_PPC_G2LE = 0x80820010,
226   - CPU_PPC_G2LEgp = 0x80822010,
227   - CPU_PPC_G2LEls = 0xA0822010,
228   - CPU_PPC_604 = 0x00040000,
229   - CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
230   - CPU_PPC_604R = 0x000a0101,
231   - /* PowerPC 74x/75x cores (aka G3) */
232   - CPU_PPC_74x = 0x00080000,
233   - CPU_PPC_740E = 0x00080100,
234   - CPU_PPC_74xP = 0x10080000,
235   - CPU_PPC_750E = 0x00080200,
236   - CPU_PPC_750CXE21 = 0x00082201,
237   - CPU_PPC_750CXE22 = 0x00082212,
238   - CPU_PPC_750CXE23 = 0x00082203,
239   - CPU_PPC_750CXE24 = 0x00082214,
240   - CPU_PPC_750CXE24b = 0x00083214,
241   - CPU_PPC_750CXE31 = 0x00083211,
242   - CPU_PPC_750CXE31b = 0x00083311,
243   -#define CPU_PPC_750CXE CPU_PPC_750CXE31b
244   - CPU_PPC_750CXR = 0x00083410,
245   - CPU_PPC_750FX10 = 0x70000100,
246   - CPU_PPC_750FX20 = 0x70000200,
247   - CPU_PPC_750FX21 = 0x70000201,
248   - CPU_PPC_750FX22 = 0x70000202,
249   - CPU_PPC_750FX23 = 0x70000203,
250   -#define CPU_PPC_750FX CPU_PPC_750FX23
251   - CPU_PPC_750FL = 0x700A0203,
252   - CPU_PPC_750GX10 = 0x70020100,
253   - CPU_PPC_750GX11 = 0x70020101,
254   - CPU_PPC_750GX12 = 0x70020102,
255   -#define CPU_PPC_750GX CPU_PPC_750GX12
256   - CPU_PPC_750GL = 0x70020102,
257   - CPU_PPC_750L30 = 0x00088300,
258   - CPU_PPC_750L32 = 0x00088302,
259   -#define CPU_PPC_750L CPU_PPC_750L32
260   - CPU_PPC_750CL = 0x00087200,
261   - CPU_PPC_755_10 = 0x00083100,
262   - CPU_PPC_755_11 = 0x00083101,
263   - CPU_PPC_755_20 = 0x00083200,
264   - CPU_PPC_755D = 0x00083202,
265   - CPU_PPC_755E = 0x00083203,
266   -#define CPU_PPC_755 CPU_PPC_755E
267   - /* PowerPC 74xx cores (aka G4) */
268   - CPU_PPC_7400 = 0x000C0100,
269   - CPU_PPC_7410C = 0x800C1102,
270   - CPU_PPC_7410D = 0x800C1103,
271   - CPU_PPC_7410E = 0x800C1104,
272   -#define CPU_PPC_7410 CPU_PPC_7410E
273   - CPU_PPC_7441 = 0x80000210,
274   - CPU_PPC_7445 = 0x80010100,
275   - CPU_PPC_7447 = 0x80020100,
276   - CPU_PPC_7447A = 0x80030101,
277   - CPU_PPC_7448 = 0x80040100,
278   - CPU_PPC_7450 = 0x80000200,
279   - CPU_PPC_7450b = 0x80000201,
280   - CPU_PPC_7451 = 0x80000203,
281   - CPU_PPC_7451G = 0x80000210,
282   - CPU_PPC_7455 = 0x80010201,
283   - CPU_PPC_7455F = 0x80010303,
284   - CPU_PPC_7455G = 0x80010304,
285   - CPU_PPC_7457 = 0x80020101,
286   - CPU_PPC_7457C = 0x80020102,
287   - CPU_PPC_7457A = 0x80030000,
288   - /* 64 bits PowerPC */
289   - CPU_PPC_620 = 0x00140000,
290   - CPU_PPC_630 = 0x00400000,
291   - CPU_PPC_631 = 0x00410000,
292   - CPU_PPC_POWER4 = 0x00350000,
293   - CPU_PPC_POWER4P = 0x00380000,
294   - CPU_PPC_POWER5 = 0x003A0000,
295   - CPU_PPC_POWER5P = 0x003B0000,
296   -#if 0
297   - CPU_PPC_POWER6 = xxx,
298   -#endif
299   - CPU_PPC_970 = 0x00390000,
300   - CPU_PPC_970FX10 = 0x00391100,
301   - CPU_PPC_970FX20 = 0x003C0200,
302   - CPU_PPC_970FX21 = 0x003C0201,
303   - CPU_PPC_970FX30 = 0x003C0300,
304   - CPU_PPC_970FX31 = 0x003C0301,
305   -#define CPU_PPC_970FX CPU_PPC_970FX31
306   - CPU_PPC_970MP10 = 0x00440100,
307   - CPU_PPC_970MP11 = 0x00440101,
308   -#define CPU_PPC_970MP CPU_PPC_970MP11
309   - CPU_PPC_CELL10 = 0x00700100,
310   - CPU_PPC_CELL20 = 0x00700400,
311   - CPU_PPC_CELL30 = 0x00700500,
312   - CPU_PPC_CELL31 = 0x00700501,
313   -#define CPU_PPC_CELL32 CPU_PPC_CELL31
314   -#define CPU_PPC_CELL CPU_PPC_CELL32
315   - CPU_PPC_RS64 = 0x00330000,
316   - CPU_PPC_RS64II = 0x00340000,
317   - CPU_PPC_RS64III = 0x00360000,
318   - CPU_PPC_RS64IV = 0x00370000,
319   - /* Original POWER */
320   - /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
321   - * POWER2 (RIOS2) & RSC2 (P2SC) here
322   - */
323   -#if 0
324   - CPU_POWER = xxx,
325   -#endif
326   -#if 0
327   - CPU_POWER2 = xxx,
328   -#endif
329   -};
330   -
331   -/* System version register (used on MPC 8xxx) */
332   -enum {
333   - PPC_SVR_8540 = 0x80300000,
334   - PPC_SVR_8541E = 0x807A0010,
335   - PPC_SVR_8543v10 = 0x80320010,
336   - PPC_SVR_8543v11 = 0x80320011,
337   - PPC_SVR_8543v20 = 0x80320020,
338   - PPC_SVR_8543Ev10 = 0x803A0010,
339   - PPC_SVR_8543Ev11 = 0x803A0011,
340   - PPC_SVR_8543Ev20 = 0x803A0020,
341   - PPC_SVR_8545 = 0x80310220,
342   - PPC_SVR_8545E = 0x80390220,
343   - PPC_SVR_8547E = 0x80390120,
344   - PPC_SCR_8548v10 = 0x80310010,
345   - PPC_SCR_8548v11 = 0x80310011,
346   - PPC_SCR_8548v20 = 0x80310020,
347   - PPC_SVR_8548Ev10 = 0x80390010,
348   - PPC_SVR_8548Ev11 = 0x80390011,
349   - PPC_SVR_8548Ev20 = 0x80390020,
350   - PPC_SVR_8555E = 0x80790010,
351   - PPC_SVR_8560v10 = 0x80700010,
352   - PPC_SVR_8560v20 = 0x80700020,
  94 + POWERPC_MMU_UNKNOWN = 0,
  95 + /* Standard 32 bits PowerPC MMU */
  96 + POWERPC_MMU_32B,
  97 + /* Standard 64 bits PowerPC MMU */
  98 + POWERPC_MMU_64B,
  99 + /* PowerPC 601 MMU */
  100 + POWERPC_MMU_601,
  101 + /* PowerPC 6xx MMU with software TLB */
  102 + POWERPC_MMU_SOFT_6xx,
  103 + /* PowerPC 74xx MMU with software TLB */
  104 + POWERPC_MMU_SOFT_74xx,
  105 + /* PowerPC 4xx MMU with software TLB */
  106 + POWERPC_MMU_SOFT_4xx,
  107 + /* PowerPC 4xx MMU with software TLB and zones protections */
  108 + POWERPC_MMU_SOFT_4xx_Z,
  109 + /* PowerPC 4xx MMU in real mode only */
  110 + POWERPC_MMU_REAL_4xx,
  111 + /* BookE MMU model */
  112 + POWERPC_MMU_BOOKE,
  113 + /* BookE FSL MMU model */
  114 + POWERPC_MMU_BOOKE_FSL,
  115 + /* 64 bits "bridge" PowerPC MMU */
  116 + POWERPC_MMU_64BRIDGE,
353 117 };
354 118  
355 119 /*****************************************************************************/
356   -/* Instruction types */
357   -enum {
358   - PPC_NONE = 0x00000000,
359   - /* integer operations instructions */
360   - /* flow control instructions */
361   - /* virtual memory instructions */
362   - /* ld/st with reservation instructions */
363   - /* cache control instructions */
364   - /* spr/msr access instructions */
365   - PPC_INSNS_BASE = 0x0000000000000001ULL,
366   -#define PPC_INTEGER PPC_INSNS_BASE
367   -#define PPC_FLOW PPC_INSNS_BASE
368   -#define PPC_MEM PPC_INSNS_BASE
369   -#define PPC_RES PPC_INSNS_BASE
370   -#define PPC_CACHE PPC_INSNS_BASE
371   -#define PPC_MISC PPC_INSNS_BASE
372   - /* floating point operations instructions */
373   - PPC_FLOAT = 0x0000000000000002ULL,
374   - /* more floating point operations instructions */
375   - PPC_FLOAT_EXT = 0x0000000000000004ULL,
376   - /* external control instructions */
377   - PPC_EXTERN = 0x0000000000000008ULL,
378   - /* segment register access instructions */
379   - PPC_SEGMENT = 0x0000000000000010ULL,
380   - /* Optional cache control instructions */
381   - PPC_CACHE_OPT = 0x0000000000000020ULL,
382   - /* Optional floating point op instructions */
383   - PPC_FLOAT_OPT = 0x0000000000000040ULL,
384   - /* Optional memory control instructions */
385   - PPC_MEM_TLBIA = 0x0000000000000080ULL,
386   - PPC_MEM_TLBIE = 0x0000000000000100ULL,
387   - PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
388   - /* eieio & sync */
389   - PPC_MEM_SYNC = 0x0000000000000400ULL,
390   - /* PowerPC 6xx TLB management instructions */
391   - PPC_6xx_TLB = 0x0000000000000800ULL,
392   - /* Altivec support */
393   - PPC_ALTIVEC = 0x0000000000001000ULL,
394   - /* Time base support */
395   - PPC_TB = 0x0000000000002000ULL,
396   - /* Embedded PowerPC dedicated instructions */
397   - PPC_EMB_COMMON = 0x0000000000004000ULL,
398   - /* PowerPC 40x exception model */
399   - PPC_40x_EXCP = 0x0000000000008000ULL,
400   - /* PowerPC 40x specific instructions */
401   - PPC_40x_SPEC = 0x0000000000010000ULL,
402   - /* PowerPC 405 Mac instructions */
403   - PPC_405_MAC = 0x0000000000020000ULL,
404   - /* PowerPC 440 specific instructions */
405   - PPC_440_SPEC = 0x0000000000040000ULL,
406   - /* Specific extensions */
407   - /* Power-to-PowerPC bridge (601) */
408   - PPC_POWER_BR = 0x0000000000080000ULL,
409   - /* PowerPC 602 specific */
410   - PPC_602_SPEC = 0x0000000000100000ULL,
411   - /* Deprecated instructions */
412   - /* Original POWER instruction set */
413   - PPC_POWER = 0x0000000000200000ULL,
414   - /* POWER2 instruction set extension */
415   - PPC_POWER2 = 0x0000000000400000ULL,
416   - /* Power RTC support */
417   - PPC_POWER_RTC = 0x0000000000800000ULL,
418   - /* 64 bits PowerPC instructions */
419   - /* 64 bits PowerPC instruction set */
420   - PPC_64B = 0x0000000001000000ULL,
421   - /* 64 bits hypervisor extensions */
422   - PPC_64H = 0x0000000002000000ULL,
423   - /* 64 bits PowerPC "bridge" features */
424   - PPC_64_BRIDGE = 0x0000000004000000ULL,
425   - /* BookE (embedded) PowerPC specification */
426   - PPC_BOOKE = 0x0000000008000000ULL,
427   - /* eieio */
428   - PPC_MEM_EIEIO = 0x0000000010000000ULL,
429   - /* e500 vector instructions */
430   - PPC_E500_VECTOR = 0x0000000020000000ULL,
431   - /* PowerPC 4xx dedicated instructions */
432   - PPC_4xx_COMMON = 0x0000000040000000ULL,
433   - /* PowerPC 2.03 specification extensions */
434   - PPC_203 = 0x0000000080000000ULL,
435   - /* PowerPC 2.03 SPE extension */
436   - PPC_SPE = 0x0000000100000000ULL,
437   - /* PowerPC 2.03 SPE floating-point extension */
438   - PPC_SPEFPU = 0x0000000200000000ULL,
439   - /* SLB management */
440   - PPC_SLBI = 0x0000000400000000ULL,
441   - /* PowerPC 40x ibct instructions */
442   - PPC_40x_ICBT = 0x0000000800000000ULL,
443   -};
444   -
445   -/* CPU run-time flags (MMU and exception model) */
  120 +/* Exception model */
446 121 enum {
447   - /* MMU model */
448   - PPC_FLAGS_MMU_MASK = 0x000000FF,
449   - /* Standard 32 bits PowerPC MMU */
450   - PPC_FLAGS_MMU_32B = 0x00000000,
451   - /* Standard 64 bits PowerPC MMU */
452   - PPC_FLAGS_MMU_64B = 0x00000001,
453   - /* PowerPC 601 MMU */
454   - PPC_FLAGS_MMU_601 = 0x00000002,
455   - /* PowerPC 6xx MMU with software TLB */
456   - PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
457   - /* PowerPC 4xx MMU with software TLB */
458   - PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
459   - /* PowerPC 403 MMU */
460   - PPC_FLAGS_MMU_403 = 0x00000005,
461   - /* BookE FSL MMU model */
462   - PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
463   - /* BookE MMU model */
464   - PPC_FLAGS_MMU_BOOKE = 0x00000007,
465   - /* 64 bits "bridge" PowerPC MMU */
466   - PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
467   - /* PowerPC 401 MMU (real mode only) */
468   - PPC_FLAGS_MMU_401 = 0x00000009,
469   - /* Exception model */
470   - PPC_FLAGS_EXCP_MASK = 0x0000FF00,
  122 + POWERPC_EXCP_UNKNOWN = 0,
471 123 /* Standard PowerPC exception model */
472   - PPC_FLAGS_EXCP_STD = 0x00000000,
  124 + POWERPC_EXCP_STD,
473 125 /* PowerPC 40x exception model */
474   - PPC_FLAGS_EXCP_40x = 0x00000100,
  126 + POWERPC_EXCP_40x,
475 127 /* PowerPC 601 exception model */
476   - PPC_FLAGS_EXCP_601 = 0x00000200,
  128 + POWERPC_EXCP_601,
477 129 /* PowerPC 602 exception model */
478   - PPC_FLAGS_EXCP_602 = 0x00000300,
  130 + POWERPC_EXCP_602,
479 131 /* PowerPC 603 exception model */
480   - PPC_FLAGS_EXCP_603 = 0x00000400,
  132 + POWERPC_EXCP_603,
  133 + /* PowerPC 603e exception model */
  134 + POWERPC_EXCP_603E,
  135 + /* PowerPC G2 exception model */
  136 + POWERPC_EXCP_G2,
481 137 /* PowerPC 604 exception model */
482   - PPC_FLAGS_EXCP_604 = 0x00000500,
  138 + POWERPC_EXCP_604,
483 139 /* PowerPC 7x0 exception model */
484   - PPC_FLAGS_EXCP_7x0 = 0x00000600,
  140 + POWERPC_EXCP_7x0,
485 141 /* PowerPC 7x5 exception model */
486   - PPC_FLAGS_EXCP_7x5 = 0x00000700,
  142 + POWERPC_EXCP_7x5,
487 143 /* PowerPC 74xx exception model */
488   - PPC_FLAGS_EXCP_74xx = 0x00000800,
  144 + POWERPC_EXCP_74xx,
489 145 /* PowerPC 970 exception model */
490   - PPC_FLAGS_EXCP_970 = 0x00000900,
  146 + POWERPC_EXCP_970,
491 147 /* BookE exception model */
492   - PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
493   - /* Input pins model */
494   - PPC_FLAGS_INPUT_MASK = 0x000F0000,
  148 + POWERPC_EXCP_BOOKE,
  149 +};
  150 +
  151 +/*****************************************************************************/
  152 +/* Input pins model */
  153 +enum {
  154 + PPC_FLAGS_INPUT_UNKNOWN = 0,
495 155 /* PowerPC 6xx bus */
496   - PPC_FLAGS_INPUT_6xx = 0x00000000,
  156 + PPC_FLAGS_INPUT_6xx,
497 157 /* BookE bus */
498   - PPC_FLAGS_INPUT_BookE = 0x00010000,
499   - /* PowerPC 4xx bus */
500   - PPC_FLAGS_INPUT_40x = 0x00020000,
  158 + PPC_FLAGS_INPUT_BookE,
  159 + /* PowerPC 405 bus */
  160 + PPC_FLAGS_INPUT_405,
501 161 /* PowerPC 970 bus */
502   - PPC_FLAGS_INPUT_970 = 0x00030000,
  162 + PPC_FLAGS_INPUT_970,
  163 + /* PowerPC 401 bus */
  164 + PPC_FLAGS_INPUT_401,
503 165 };
504 166  
505   -#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
506   -#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
507   -#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
  167 +#define PPC_INPUT(env) (env->bus_model)
508 168  
509   -/*****************************************************************************/
510   -/* Supported instruction set definitions */
511   -/* This generates an empty opcode table... */
512   -#define PPC_INSNS_TODO (PPC_NONE)
513   -#define PPC_FLAGS_TODO (0x00000000)
514   -
515   -/* PowerPC 40x instruction set */
516   -#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
517   -/* PowerPC 401 */
518   -#define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
519   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
520   -#define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x | \
521   - PPC_FLAGS_INPUT_40x)
522   -/* PowerPC 403 */
523   -#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
524   - PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | \
525   - PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT)
526   -#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
527   - PPC_FLAGS_INPUT_40x)
528   -/* PowerPC 405 */
529   -#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
530   - PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
531   - PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC | \
532   - PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC)
533   -#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
534   - PPC_FLAGS_INPUT_40x)
535   -/* PowerPC 440 */
536   -#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
537   - PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | \
538   - PPC_440_SPEC)
539   -#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
540   - PPC_FLAGS_INPUT_BookE)
541   -/* Generic BookE PowerPC */
542   -#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
543   - PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT | \
544   - PPC_CACHE_OPT)
545   -#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
546   - PPC_FLAGS_INPUT_BookE)
547   -/* e500 core */
548   -#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
549   - PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR)
550   -#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
551   - PPC_FLAGS_INPUT_BookE)
552   -/* Non-embedded PowerPC */
553   -#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
554   - PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
555   -/* PowerPC 601 */
556   -#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
557   -#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
558   - PPC_FLAGS_INPUT_6xx)
559   -/* PowerPC 602 */
560   -#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
561   - PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
562   -#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
563   - PPC_FLAGS_INPUT_6xx)
564   -/* PowerPC 603 */
565   -#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
566   - PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
567   -#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
568   - PPC_FLAGS_INPUT_6xx)
569   -/* PowerPC G2 */
570   -#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
571   - PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
572   -#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
573   - PPC_FLAGS_INPUT_6xx)
574   -/* PowerPC 604 */
575   -#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
576   - PPC_MEM_TLBSYNC | PPC_TB)
577   -#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
578   - PPC_FLAGS_INPUT_6xx)
579   -/* PowerPC 740/750 (aka G3) */
580   -#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
581   - PPC_MEM_TLBSYNC | PPC_TB)
582   -#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
583   - PPC_FLAGS_INPUT_6xx)
584   -/* PowerPC 745/755 */
585   -#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
586   - PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
587   -#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
588   - PPC_FLAGS_INPUT_6xx)
589   -/* PowerPC 74xx (aka G4) */
590   -#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
591   - PPC_MEM_TLBSYNC | PPC_TB)
592   -#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
593   - PPC_FLAGS_INPUT_6xx)
594   -/* PowerPC 970 (aka G5) */
595   -#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
596   - PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
597   - PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
598   -#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
599   - PPC_FLAGS_INPUT_970)
600   -
601   -/* Default PowerPC will be 604/970 */
602   -#define PPC_INSNS_PPC32 PPC_INSNS_604
603   -#define PPC_FLAGS_PPC32 PPC_FLAGS_604
604   -#define PPC_INSNS_PPC64 PPC_INSNS_970
605   -#define PPC_FLAGS_PPC64 PPC_FLAGS_970
606   -#define PPC_INSNS_DEFAULT PPC_INSNS_604
607   -#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
608 169 typedef struct ppc_def_t ppc_def_t;
  170 +typedef struct opc_handler_t opc_handler_t;
609 171  
610 172 /*****************************************************************************/
611 173 /* Types used to describe some PowerPC registers */
612 174 typedef struct CPUPPCState CPUPPCState;
613   -typedef struct opc_handler_t opc_handler_t;
614 175 typedef struct ppc_tb_t ppc_tb_t;
615 176 typedef struct ppc_spr_t ppc_spr_t;
616 177 typedef struct ppc_dcr_t ppc_dcr_t;
... ... @@ -832,7 +393,11 @@ struct CPUPPCState {
832 393  
833 394 /* Those resources are used during exception processing */
834 395 /* CPU model definition */
835   - uint64_t msr_mask;
  396 + target_ulong msr_mask;
  397 + uint8_t mmu_model;
  398 + uint8_t excp_model;
  399 + uint8_t bus_model;
  400 + uint8_t pad;
836 401 uint32_t flags;
837 402  
838 403 int exception_index;
... ... @@ -985,7 +550,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
985 550 #define SPR_LR (0x008)
986 551 #define SPR_CTR (0x009)
987 552 #define SPR_DSISR (0x012)
988   -#define SPR_DAR (0x013)
  553 +#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
989 554 #define SPR_601_RTCU (0x014)
990 555 #define SPR_601_RTCL (0x015)
991 556 #define SPR_DECR (0x016)
... ... @@ -1203,6 +768,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1203 768 #define SPR_440_ITV1 (0x375)
1204 769 #define SPR_440_ITV2 (0x376)
1205 770 #define SPR_440_ITV3 (0x377)
  771 +#define SPR_440_CCR1 (0x378)
  772 +#define SPR_DCRIPR (0x37B)
1206 773 #define SPR_PPR (0x380)
1207 774 #define SPR_440_DNV0 (0x390)
1208 775 #define SPR_440_DNV1 (0x391)
... ... @@ -1219,38 +786,63 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1219 786 #define SPR_BOOKE_DCDBTRH (0x39D)
1220 787 #define SPR_BOOKE_ICDBTRL (0x39E)
1221 788 #define SPR_BOOKE_ICDBTRH (0x39F)
  789 +#define SPR_UMMCR2 (0x3A0)
  790 +#define SPR_UPMC5 (0x3A1)
  791 +#define SPR_UPMC6 (0x3A2)
  792 +#define SPR_UBAMR (0x3A7)
1222 793 #define SPR_UMMCR0 (0x3A8)
1223 794 #define SPR_UPMC1 (0x3A9)
1224 795 #define SPR_UPMC2 (0x3AA)
1225   -#define SPR_USIA (0x3AB)
  796 +#define SPR_USIAR (0x3AB)
1226 797 #define SPR_UMMCR1 (0x3AC)
1227 798 #define SPR_UPMC3 (0x3AD)
1228 799 #define SPR_UPMC4 (0x3AE)
1229 800 #define SPR_USDA (0x3AF)
1230 801 #define SPR_40x_ZPR (0x3B0)
1231 802 #define SPR_BOOKE_MAS7 (0x3B0)
  803 +#define SPR_620_PMR0 (0x3B0)
  804 +#define SPR_MMCR2 (0x3B0)
  805 +#define SPR_PMC5 (0x3B1)
1232 806 #define SPR_40x_PID (0x3B1)
  807 +#define SPR_620_PMR1 (0x3B1)
  808 +#define SPR_PMC6 (0x3B2)
1233 809 #define SPR_440_MMUCR (0x3B2)
  810 +#define SPR_620_PMR2 (0x3B2)
1234 811 #define SPR_4xx_CCR0 (0x3B3)
1235 812 #define SPR_BOOKE_EPLC (0x3B3)
  813 +#define SPR_620_PMR3 (0x3B3)
1236 814 #define SPR_405_IAC3 (0x3B4)
1237 815 #define SPR_BOOKE_EPSC (0x3B4)
  816 +#define SPR_620_PMR4 (0x3B4)
1238 817 #define SPR_405_IAC4 (0x3B5)
  818 +#define SPR_620_PMR5 (0x3B5)
1239 819 #define SPR_405_DVC1 (0x3B6)
  820 +#define SPR_620_PMR6 (0x3B6)
1240 821 #define SPR_405_DVC2 (0x3B7)
  822 +#define SPR_620_PMR7 (0x3B7)
  823 +#define SPR_BAMR (0x3B7)
1241 824 #define SPR_MMCR0 (0x3B8)
  825 +#define SPR_620_PMR8 (0x3B8)
1242 826 #define SPR_PMC1 (0x3B9)
1243 827 #define SPR_40x_SGR (0x3B9)
  828 +#define SPR_620_PMR9 (0x3B9)
1244 829 #define SPR_PMC2 (0x3BA)
1245 830 #define SPR_40x_DCWR (0x3BA)
1246   -#define SPR_SIA (0x3BB)
  831 +#define SPR_620_PMRA (0x3BA)
  832 +#define SPR_SIAR (0x3BB)
1247 833 #define SPR_405_SLER (0x3BB)
  834 +#define SPR_620_PMRB (0x3BB)
1248 835 #define SPR_MMCR1 (0x3BC)
1249 836 #define SPR_405_SU0R (0x3BC)
  837 +#define SPR_620_PMRC (0x3BC)
  838 +#define SPR_401_SKR (0x3BC)
1250 839 #define SPR_PMC3 (0x3BD)
1251 840 #define SPR_405_DBCR1 (0x3BD)
  841 +#define SPR_620_PMRD (0x3BD)
1252 842 #define SPR_PMC4 (0x3BE)
  843 +#define SPR_620_PMRE (0x3BE)
1253 844 #define SPR_SDA (0x3BF)
  845 +#define SPR_620_PMRF (0x3BF)
1254 846 #define SPR_403_VTBL (0x3CC)
1255 847 #define SPR_403_VTBU (0x3CD)
1256 848 #define SPR_DMISS (0x3D0)
... ... @@ -1258,18 +850,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1258 850 #define SPR_HASH1 (0x3D2)
1259 851 #define SPR_HASH2 (0x3D3)
1260 852 #define SPR_BOOKE_ICDBDR (0x3D3)
  853 +#define SPR_TLBMISS (0x3D4)
1261 854 #define SPR_IMISS (0x3D4)
1262 855 #define SPR_40x_ESR (0x3D4)
  856 +#define SPR_PTEHI (0x3D5)
1263 857 #define SPR_ICMP (0x3D5)
1264 858 #define SPR_40x_DEAR (0x3D5)
  859 +#define SPR_PTELO (0x3D6)
1265 860 #define SPR_RPA (0x3D6)
1266 861 #define SPR_40x_EVPR (0x3D6)
  862 +#define SPR_L3PM (0x3D7)
1267 863 #define SPR_403_CDBCR (0x3D7)
  864 +#define SPR_L3OHCR (0x3D8)
1268 865 #define SPR_TCR (0x3D8)
1269 866 #define SPR_40x_TSR (0x3D8)
1270 867 #define SPR_IBR (0x3DA)
1271 868 #define SPR_40x_TCR (0x3DA)
1272   -#define SPR_ESASR (0x3DB)
  869 +#define SPR_ESASRR (0x3DB)
1273 870 #define SPR_40x_PIT (0x3DB)
1274 871 #define SPR_403_TBL (0x3DC)
1275 872 #define SPR_403_TBU (0x3DD)
... ... @@ -1277,6 +874,10 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1277 874 #define SPR_40x_SRR2 (0x3DE)
1278 875 #define SPR_SER (0x3DF)
1279 876 #define SPR_40x_SRR3 (0x3DF)
  877 +#define SPR_L3ITCR0 (0x3E8)
  878 +#define SPR_L3ITCR1 (0x3E9)
  879 +#define SPR_L3ITCR2 (0x3EA)
  880 +#define SPR_L3ITCR3 (0x3EB)
1280 881 #define SPR_HID0 (0x3F0)
1281 882 #define SPR_40x_DBSR (0x3F0)
1282 883 #define SPR_HID1 (0x3F1)
... ... @@ -1284,9 +885,11 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1284 885 #define SPR_40x_DBCR0 (0x3F2)
1285 886 #define SPR_601_HID2 (0x3F2)
1286 887 #define SPR_E500_L1CSR0 (0x3F2)
  888 +#define SPR_ICTRL (0x3F3)
1287 889 #define SPR_HID2 (0x3F3)
1288 890 #define SPR_E500_L1CSR1 (0x3F3)
1289 891 #define SPR_440_DBDR (0x3F3)
  892 +#define SPR_LDSTDB (0x3F4)
1290 893 #define SPR_40x_IAC1 (0x3F4)
1291 894 #define SPR_BOOKE_MMUCSR0 (0x3F4)
1292 895 #define SPR_DABR (0x3F5)
... ... @@ -1295,12 +898,18 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1295 898 #define SPR_40x_IAC2 (0x3F5)
1296 899 #define SPR_601_HID5 (0x3F5)
1297 900 #define SPR_40x_DAC1 (0x3F6)
  901 +#define SPR_MSSCR0 (0x3F6)
  902 +#define SPR_MSSSR0 (0x3F7)
1298 903 #define SPR_DABRX (0x3F7)
1299 904 #define SPR_40x_DAC2 (0x3F7)
1300 905 #define SPR_BOOKE_MMUCFG (0x3F7)
1301   -#define SPR_L2PM (0x3F8)
  906 +#define SPR_LDSTCR (0x3F8)
  907 +#define SPR_L2PMCR (0x3F8)
1302 908 #define SPR_750_HID2 (0x3F8)
  909 +#define SPR_620_HID8 (0x3F8)
1303 910 #define SPR_L2CR (0x3F9)
  911 +#define SPR_620_HID9 (0x3F9)
  912 +#define SPR_L3CR (0x3FA)
1304 913 #define SPR_IABR2 (0x3FA)
1305 914 #define SPR_40x_DCCR (0x3FA)
1306 915 #define SPR_ICTC (0x3FB)
... ... @@ -1310,6 +919,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1310 919 #define SPR_SP (0x3FD)
1311 920 #define SPR_THRM2 (0x3FD)
1312 921 #define SPR_403_PBU1 (0x3FD)
  922 +#define SPR_604_HID13 (0x3FD)
1313 923 #define SPR_LT (0x3FE)
1314 924 #define SPR_THRM3 (0x3FE)
1315 925 #define SPR_FPECR (0x3FE)
... ... @@ -1317,6 +927,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
1317 927 #define SPR_PIR (0x3FF)
1318 928 #define SPR_403_PBU2 (0x3FF)
1319 929 #define SPR_601_HID15 (0x3FF)
  930 +#define SPR_604_HID15 (0x3FF)
1320 931 #define SPR_E500_SVR (0x3FF)
1321 932  
1322 933 /*****************************************************************************/
... ... @@ -1367,6 +978,11 @@ enum {
1367 978 #define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1368 979 /* 405 specific exceptions */
1369 980 #define EXCP_405_APU 0x0F20 /* APU unavailable exception */
  981 +/* 440 specific exceptions */
  982 +#define EXCP_440_CRIT 0x0100 /* Critical interrupt */
  983 +#define EXCP_440_SPEU 0x1600 /* SPE unavailable exception */
  984 +#define EXCP_440_SPED 0x1700 /* SPE floating-point data exception */
  985 +#define EXCP_440_SPER 0x1800 /* SPE floating-point round exception */
1370 986 /* TLB assist exceptions (602/603) */
1371 987 #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1372 988 #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
... ... @@ -1377,7 +993,7 @@ enum {
1377 993 /* Altivec related exceptions */
1378 994 #define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1379 995 /* 601 specific exceptions */
1380   -#define EXCP_601_IO 0x0600 /* IO error exception */
  996 +#define EXCP_601_IO 0x0A00 /* IO error exception */
1381 997 #define EXCP_601_RUNM 0x2000 /* Run mode exception */
1382 998 /* 602 specific exceptions */
1383 999 #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
... ... @@ -1468,6 +1084,15 @@ enum {
1468 1084 };
1469 1085  
1470 1086 enum {
  1087 + /* PowerPC 401/403 input pins */
  1088 + PPC401_INPUT_RESET = 0,
  1089 + PPC401_INPUT_CINT = 1,
  1090 + PPC401_INPUT_INT = 2,
  1091 + PPC401_INPUT_BERR = 3,
  1092 + PPC401_INPUT_HALT = 4,
  1093 +};
  1094 +
  1095 +enum {
1471 1096 /* PowerPC 405 input pins */
1472 1097 PPC405_INPUT_RESET_CORE = 0,
1473 1098 PPC405_INPUT_RESET_CHIP = 1,
... ... @@ -1479,6 +1104,18 @@ enum {
1479 1104 };
1480 1105  
1481 1106 enum {
  1107 + /* PowerPC 620 (and probably others) input pins */
  1108 + PPC620_INPUT_HRESET = 0,
  1109 + PPC620_INPUT_SRESET = 1,
  1110 + PPC620_INPUT_CKSTP = 2,
  1111 + PPC620_INPUT_TBEN = 3,
  1112 + PPC620_INPUT_WAKEUP = 4,
  1113 + PPC620_INPUT_MCP = 5,
  1114 + PPC620_INPUT_SMI = 6,
  1115 + PPC620_INPUT_INT = 7,
  1116 +};
  1117 +
  1118 +enum {
1482 1119 /* PowerPC 970 input pins */
1483 1120 PPC970_INPUT_HRESET = 0,
1484 1121 PPC970_INPUT_SRESET = 1,
... ...
target-ppc/exec.h
  View file @a750fc0
... ... @@ -106,6 +106,8 @@ void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
106 106 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
107 107 target_ulong pte0, target_ulong pte1);
108 108 void ppc4xx_tlb_invalidate_all (CPUState *env);
  109 +void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
  110 + uint32_t pid);
109 111  
110 112 static inline void env_to_regs (void)
111 113 {
... ...
target-ppc/helper.c
  View file @a750fc0
... ... @@ -586,8 +586,8 @@ static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
586 586 static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
587 587 {
588 588 #if defined(TARGET_PPC64)
589   - if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
590   - PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE)
  589 + if (env->mmu_model == POWERPC_MMU_64B ||
  590 + env->mmu_model == POWERPC_MMU_64BRIDGE)
591 591 return find_pte64(ctx, h, rw);
592 592 #endif
593 593  
... ... @@ -669,7 +669,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
669 669 int ret, ret2;
670 670  
671 671 #if defined(TARGET_PPC64)
672   - if (PPC_MMU(env) == PPC_FLAGS_MMU_64B) {
  672 + if (env->mmu_model == POWERPC_MMU_64B) {
673 673 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
674 674 if (ret < 0)
675 675 return ret;
... ... @@ -724,8 +724,8 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
724 724 hash = (~hash) & vsid_mask;
725 725 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
726 726 #if defined(TARGET_PPC64)
727   - if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
728   - PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE) {
  727 + if (env->mmu_model == POWERPC_MMU_64B ||
  728 + env->mmu_model == POWERPC_MMU_64BRIDGE) {
729 729 /* Only 5 bits of the page index are used in the AVPN */
730 730 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
731 731 } else
... ... @@ -735,7 +735,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
735 735 }
736 736 /* Initialize real address with an invalid value */
737 737 ctx->raddr = (target_ulong)-1;
738   - if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
  738 + if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
739 739 /* Software TLB search */
740 740 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
741 741 } else {
... ... @@ -865,7 +865,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
865 865  
866 866 /* Default return value is no match */
867 867 ret = -1;
868   - for (i = 0; i < 64; i++) {
  868 + for (i = 0; i < env->nb_tlb; i++) {
869 869 tlb = &env->tlb[i].tlbe;
870 870 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
871 871 ret = i;
... ... @@ -876,6 +876,26 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
876 876 return ret;
877 877 }
878 878  
  879 +void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
  880 + uint32_t pid)
  881 +{
  882 + ppcemb_tlb_t *tlb;
  883 + target_phys_addr_t raddr;
  884 + target_ulong page, end;
  885 + int i;
  886 +
  887 + for (i = 0; i < env->nb_tlb; i++) {
  888 + tlb = &env->tlb[i].tlbe;
  889 + if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
  890 + end = tlb->EPN + tlb->size;
  891 + for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
  892 + tlb_flush_page(env, page);
  893 + tlb->prot &= ~PAGE_VALID;
  894 + break;
  895 + }
  896 + }
  897 +}
  898 +
879 899 /* Helpers specific to PowerPC 40x implementations */
880 900 void ppc4xx_tlb_invalidate_all (CPUState *env)
881 901 {
... ... @@ -1069,23 +1089,23 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1069 1089 ctx->raddr = eaddr;
1070 1090 ctx->prot = PAGE_READ;
1071 1091 ret = 0;
1072   - switch (PPC_MMU(env)) {
1073   - case PPC_FLAGS_MMU_32B:
1074   - case PPC_FLAGS_MMU_SOFT_6xx:
1075   - case PPC_FLAGS_MMU_601:
1076   - case PPC_FLAGS_MMU_SOFT_4xx:
1077   - case PPC_FLAGS_MMU_401:
  1092 + switch (env->mmu_model) {
  1093 + case POWERPC_MMU_32B:
  1094 + case POWERPC_MMU_SOFT_6xx:
  1095 + case POWERPC_MMU_601:
  1096 + case POWERPC_MMU_SOFT_4xx:
  1097 + case POWERPC_MMU_REAL_4xx:
1078 1098 ctx->prot |= PAGE_WRITE;
1079 1099 break;
1080 1100 #if defined(TARGET_PPC64)
1081   - case PPC_FLAGS_MMU_64B:
1082   - case PPC_FLAGS_MMU_64BRIDGE:
  1101 + case POWERPC_MMU_64B:
  1102 + case POWERPC_MMU_64BRIDGE:
1083 1103 /* Real address are 60 bits long */
1084   - ctx->raddr &= 0x0FFFFFFFFFFFFFFFUL;
  1104 + ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1085 1105 ctx->prot |= PAGE_WRITE;
1086 1106 break;
1087 1107 #endif
1088   - case PPC_FLAGS_MMU_403:
  1108 + case POWERPC_MMU_SOFT_4xx_Z:
1089 1109 if (unlikely(msr_pe != 0)) {
1090 1110 /* 403 family add some particular protections,
1091 1111 * using PBL/PBU registers for accesses with no translation.
... ... @@ -1108,10 +1128,10 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1108 1128 ctx->prot |= PAGE_WRITE;
1109 1129 }
1110 1130 }
1111   - case PPC_FLAGS_MMU_BOOKE:
  1131 + case POWERPC_MMU_BOOKE:
1112 1132 ctx->prot |= PAGE_WRITE;
1113 1133 break;
1114   - case PPC_FLAGS_MMU_BOOKE_FSL:
  1134 + case POWERPC_MMU_BOOKE_FSL:
1115 1135 /* XXX: TODO */
1116 1136 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1117 1137 break;
... ... @@ -1138,40 +1158,40 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1138 1158 ret = check_physical(env, ctx, eaddr, rw);
1139 1159 } else {
1140 1160 ret = -1;
1141   - switch (PPC_MMU(env)) {
1142   - case PPC_FLAGS_MMU_32B:
1143   - case PPC_FLAGS_MMU_SOFT_6xx:
  1161 + switch (env->mmu_model) {
  1162 + case POWERPC_MMU_32B:
  1163 + case POWERPC_MMU_SOFT_6xx:
1144 1164 /* Try to find a BAT */
1145 1165 if (check_BATs)
1146 1166 ret = get_bat(env, ctx, eaddr, rw, access_type);
1147 1167 /* No break here */
1148 1168 #if defined(TARGET_PPC64)
1149   - case PPC_FLAGS_MMU_64B:
1150   - case PPC_FLAGS_MMU_64BRIDGE:
  1169 + case POWERPC_MMU_64B:
  1170 + case POWERPC_MMU_64BRIDGE:
1151 1171 #endif
1152 1172 if (ret < 0) {
1153 1173 /* We didn't match any BAT entry or don't have BATs */
1154 1174 ret = get_segment(env, ctx, eaddr, rw, access_type);
1155 1175 }
1156 1176 break;
1157   - case PPC_FLAGS_MMU_SOFT_4xx:
1158   - case PPC_FLAGS_MMU_403:
  1177 + case POWERPC_MMU_SOFT_4xx:
  1178 + case POWERPC_MMU_SOFT_4xx_Z:
1159 1179 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1160 1180 rw, access_type);
1161 1181 break;
1162   - case PPC_FLAGS_MMU_601:
  1182 + case POWERPC_MMU_601:
1163 1183 /* XXX: TODO */
1164 1184 cpu_abort(env, "601 MMU model not implemented\n");
1165 1185 return -1;
1166   - case PPC_FLAGS_MMU_BOOKE:
  1186 + case POWERPC_MMU_BOOKE:
1167 1187 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1168 1188 rw, access_type);
1169 1189 break;
1170   - case PPC_FLAGS_MMU_BOOKE_FSL:
  1190 + case POWERPC_MMU_BOOKE_FSL:
1171 1191 /* XXX: TODO */
1172 1192 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1173 1193 return -1;
1174   - case PPC_FLAGS_MMU_401:
  1194 + case POWERPC_MMU_REAL_4xx:
1175 1195 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1176 1196 return -1;
1177 1197 default:
... ... @@ -1234,46 +1254,46 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1234 1254 switch (ret) {
1235 1255 case -1:
1236 1256 /* No matches in page tables or TLB */
1237   - switch (PPC_MMU(env)) {
1238   - case PPC_FLAGS_MMU_SOFT_6xx:
  1257 + switch (env->mmu_model) {
  1258 + case POWERPC_MMU_SOFT_6xx:
1239 1259 exception = EXCP_I_TLBMISS;
1240 1260 env->spr[SPR_IMISS] = address;
1241 1261 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1242 1262 error_code = 1 << 18;
1243 1263 goto tlb_miss;
1244   - case PPC_FLAGS_MMU_SOFT_4xx:
1245   - case PPC_FLAGS_MMU_403:
  1264 + case POWERPC_MMU_SOFT_4xx:
  1265 + case POWERPC_MMU_SOFT_4xx_Z:
1246 1266 exception = EXCP_40x_ITLBMISS;
1247 1267 error_code = 0;
1248 1268 env->spr[SPR_40x_DEAR] = address;
1249 1269 env->spr[SPR_40x_ESR] = 0x00000000;
1250 1270 break;
1251   - case PPC_FLAGS_MMU_32B:
  1271 + case POWERPC_MMU_32B:
1252 1272 error_code = 0x40000000;
1253 1273 break;
1254 1274 #if defined(TARGET_PPC64)
1255   - case PPC_FLAGS_MMU_64B:
  1275 + case POWERPC_MMU_64B:
1256 1276 /* XXX: TODO */
1257 1277 cpu_abort(env, "MMU model not implemented\n");
1258 1278 return -1;
1259   - case PPC_FLAGS_MMU_64BRIDGE:
  1279 + case POWERPC_MMU_64BRIDGE:
1260 1280 /* XXX: TODO */
1261 1281 cpu_abort(env, "MMU model not implemented\n");
1262 1282 return -1;
1263 1283 #endif
1264   - case PPC_FLAGS_MMU_601:
  1284 + case POWERPC_MMU_601:
1265 1285 /* XXX: TODO */
1266 1286 cpu_abort(env, "MMU model not implemented\n");
1267 1287 return -1;
1268   - case PPC_FLAGS_MMU_BOOKE:
  1288 + case POWERPC_MMU_BOOKE:
1269 1289 /* XXX: TODO */
1270 1290 cpu_abort(env, "MMU model not implemented\n");
1271 1291 return -1;
1272   - case PPC_FLAGS_MMU_BOOKE_FSL:
  1292 + case POWERPC_MMU_BOOKE_FSL:
1273 1293 /* XXX: TODO */
1274 1294 cpu_abort(env, "MMU model not implemented\n");
1275 1295 return -1;
1276   - case PPC_FLAGS_MMU_401:
  1296 + case POWERPC_MMU_REAL_4xx:
1277 1297 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1278 1298 "exceptions\n");
1279 1299 return -1;
... ... @@ -1306,8 +1326,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1306 1326 switch (ret) {
1307 1327 case -1:
1308 1328 /* No matches in page tables or TLB */
1309   - switch (PPC_MMU(env)) {
1310   - case PPC_FLAGS_MMU_SOFT_6xx:
  1329 + switch (env->mmu_model) {
  1330 + case POWERPC_MMU_SOFT_6xx:
1311 1331 if (rw == 1) {
1312 1332 exception = EXCP_DS_TLBMISS;
1313 1333 error_code = 1 << 16;
... ... @@ -1323,8 +1343,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1323 1343 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1324 1344 /* Do not alter DAR nor DSISR */
1325 1345 goto out;
1326   - case PPC_FLAGS_MMU_SOFT_4xx:
1327   - case PPC_FLAGS_MMU_403:
  1346 + case POWERPC_MMU_SOFT_4xx:
  1347 + case POWERPC_MMU_SOFT_4xx_Z:
1328 1348 exception = EXCP_40x_DTLBMISS;
1329 1349 error_code = 0;
1330 1350 env->spr[SPR_40x_DEAR] = address;
... ... @@ -1333,32 +1353,32 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1333 1353 else
1334 1354 env->spr[SPR_40x_ESR] = 0x00000000;
1335 1355 break;
1336   - case PPC_FLAGS_MMU_32B:
  1356 + case POWERPC_MMU_32B:
1337 1357 error_code = 0x40000000;
1338 1358 break;
1339 1359 #if defined(TARGET_PPC64)
1340   - case PPC_FLAGS_MMU_64B:
  1360 + case POWERPC_MMU_64B:
1341 1361 /* XXX: TODO */
1342 1362 cpu_abort(env, "MMU model not implemented\n");
1343 1363 return -1;
1344   - case PPC_FLAGS_MMU_64BRIDGE:
  1364 + case POWERPC_MMU_64BRIDGE:
1345 1365 /* XXX: TODO */
1346 1366 cpu_abort(env, "MMU model not implemented\n");
1347 1367 return -1;
1348 1368 #endif
1349   - case PPC_FLAGS_MMU_601:
  1369 + case POWERPC_MMU_601:
1350 1370 /* XXX: TODO */
1351 1371 cpu_abort(env, "MMU model not implemented\n");
1352 1372 return -1;
1353   - case PPC_FLAGS_MMU_BOOKE:
  1373 + case POWERPC_MMU_BOOKE:
1354 1374 /* XXX: TODO */
1355 1375 cpu_abort(env, "MMU model not implemented\n");
1356 1376 return -1;
1357   - case PPC_FLAGS_MMU_BOOKE_FSL:
  1377 + case POWERPC_MMU_BOOKE_FSL:
1358 1378 /* XXX: TODO */
1359 1379 cpu_abort(env, "MMU model not implemented\n");
1360 1380 return -1;
1361   - case PPC_FLAGS_MMU_401:
  1381 + case POWERPC_MMU_REAL_4xx:
1362 1382 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1363 1383 "exceptions\n");
1364 1384 return -1;
... ... @@ -1544,9 +1564,9 @@ void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1544 1564 /* TLB management */
1545 1565 void ppc_tlb_invalidate_all (CPUPPCState *env)
1546 1566 {
1547   - if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
  1567 + if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
1548 1568 ppc6xx_tlb_invalidate_all(env);
1549   - } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
  1569 + } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
1550 1570 ppc4xx_tlb_invalidate_all(env);
1551 1571 } else {
1552 1572 tlb_flush(env, 1);
... ... @@ -1707,9 +1727,11 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
1707 1727 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1708 1728 }
1709 1729 #endif
1710   - switch (PPC_EXCP(env)) {
1711   - case PPC_FLAGS_EXCP_602:
1712   - case PPC_FLAGS_EXCP_603:
  1730 + switch (env->excp_model) {
  1731 + case POWERPC_EXCP_602:
  1732 + case POWERPC_EXCP_603:
  1733 + case POWERPC_EXCP_603E:
  1734 + case POWERPC_EXCP_G2:
1713 1735 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1714 1736 /* Swap temporary saved registers with GPRs */
1715 1737 swap_gpr_tgpr(env);
... ... @@ -1750,19 +1772,21 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
1750 1772 do_compute_hflags(env);
1751 1773  
1752 1774 enter_pm = 0;
1753   - switch (PPC_EXCP(env)) {
1754   - case PPC_FLAGS_EXCP_603:
  1775 + switch (env->excp_model) {
  1776 + case POWERPC_EXCP_603:
  1777 + case POWERPC_EXCP_603E:
  1778 + case POWERPC_EXCP_G2:
1755 1779 /* Don't handle SLEEP mode: we should disable all clocks...
1756 1780 * No dynamic power-management.
1757 1781 */
1758 1782 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1759 1783 enter_pm = 1;
1760 1784 break;
1761   - case PPC_FLAGS_EXCP_604:
  1785 + case POWERPC_EXCP_604:
1762 1786 if (msr_pow == 1)
1763 1787 enter_pm = 1;
1764 1788 break;
1765   - case PPC_FLAGS_EXCP_7x0:
  1789 + case POWERPC_EXCP_7x0:
1766 1790 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1767 1791 enter_pm = 1;
1768 1792 break;
... ... @@ -1854,12 +1878,12 @@ void do_interrupt (CPUState *env)
1854 1878 switch (excp) {
1855 1879 /* Generic PowerPC exceptions */
1856 1880 case EXCP_RESET: /* 0x0100 */
1857   - switch (PPC_EXCP(env)) {
1858   - case PPC_FLAGS_EXCP_40x:
  1881 + switch (env->excp_model) {
  1882 + case POWERPC_EXCP_40x:
1859 1883 srr_0 = &env->spr[SPR_40x_SRR2];
1860 1884 srr_1 = &env->spr[SPR_40x_SRR3];
1861 1885 break;
1862   - case PPC_FLAGS_EXCP_BOOKE:
  1886 + case POWERPC_EXCP_BOOKE:
1863 1887 idx = 0;
1864 1888 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1865 1889 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
... ... @@ -1872,12 +1896,12 @@ void do_interrupt (CPUState *env)
1872 1896 }
1873 1897 goto store_next;
1874 1898 case EXCP_MACHINE_CHECK: /* 0x0200 */
1875   - switch (PPC_EXCP(env)) {
1876   - case PPC_FLAGS_EXCP_40x:
  1899 + switch (env->excp_model) {
  1900 + case POWERPC_EXCP_40x:
1877 1901 srr_0 = &env->spr[SPR_40x_SRR2];
1878 1902 srr_1 = &env->spr[SPR_40x_SRR3];
1879 1903 break;
1880   - case PPC_FLAGS_EXCP_BOOKE:
  1904 + case POWERPC_EXCP_BOOKE:
1881 1905 idx = 1;
1882 1906 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1883 1907 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
... ... @@ -1920,7 +1944,7 @@ void do_interrupt (CPUState *env)
1920 1944 idx = 4;
1921 1945 goto store_next;
1922 1946 case EXCP_ALIGN: /* 0x0600 */
1923   - if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
  1947 + if (likely(env->excp_model != POWERPC_EXCP_601)) {
1924 1948 /* Store exception cause */
1925 1949 idx = 5;
1926 1950 /* Get rS/rD and rA from faulting opcode */
... ... @@ -2028,26 +2052,27 @@ void do_interrupt (CPUState *env)
2028 2052 goto store_next;
2029 2053 /* Implementation specific exceptions */
2030 2054 case 0x0A00:
2031   - if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
2032   - env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
  2055 + switch (env->excp_model) {
  2056 + case POWERPC_EXCP_G2:
2033 2057 /* Critical interrupt on G2 */
2034 2058 /* XXX: TODO */
2035 2059 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
2036 2060 goto store_next;
2037   - } else {
  2061 + default:
2038 2062 cpu_abort(env, "Invalid exception 0x0A00 !\n");
  2063 + break;
2039 2064 }
2040 2065 return;
2041 2066 case 0x0F20:
2042 2067 idx = 9;
2043   - switch (PPC_EXCP(env)) {
2044   - case PPC_FLAGS_EXCP_40x:
  2068 + switch (env->excp_model) {
  2069 + case POWERPC_EXCP_40x:
2045 2070 /* APU unavailable on 405 */
2046 2071 /* XXX: TODO */
2047 2072 cpu_abort(env,
2048 2073 "APU unavailable exception is not implemented yet !\n");
2049 2074 goto store_next;
2050   - case PPC_FLAGS_EXCP_74xx:
  2075 + case POWERPC_EXCP_74xx:
2051 2076 /* Altivec unavailable */
2052 2077 /* XXX: TODO */
2053 2078 cpu_abort(env, "Altivec unavailable exception "
... ... @@ -2060,8 +2085,8 @@ void do_interrupt (CPUState *env)
2060 2085 return;
2061 2086 case 0x1000:
2062 2087 idx = 10;
2063   - switch (PPC_EXCP(env)) {
2064   - case PPC_FLAGS_EXCP_40x:
  2088 + switch (env->excp_model) {
  2089 + case POWERPC_EXCP_40x:
2065 2090 /* PIT on 4xx */
2066 2091 msr &= ~0xFFFF0000;
2067 2092 #if defined (DEBUG_EXCEPTIONS)
... ... @@ -2069,11 +2094,13 @@ void do_interrupt (CPUState *env)
2069 2094 fprintf(logfile, "PIT exception\n");
2070 2095 #endif
2071 2096 goto store_next;
2072   - case PPC_FLAGS_EXCP_602:
2073   - case PPC_FLAGS_EXCP_603:
  2097 + case POWERPC_EXCP_602:
  2098 + case POWERPC_EXCP_603:
  2099 + case POWERPC_EXCP_603E:
  2100 + case POWERPC_EXCP_G2:
2074 2101 /* ITLBMISS on 602/603 */
2075 2102 goto store_gprs;
2076   - case PPC_FLAGS_EXCP_7x5:
  2103 + case POWERPC_EXCP_7x5:
2077 2104 /* ITLBMISS on 745/755 */
2078 2105 goto tlb_miss;
2079 2106 default:
... ... @@ -2083,8 +2110,8 @@ void do_interrupt (CPUState *env)
2083 2110 return;
2084 2111 case 0x1010:
2085 2112 idx = 11;
2086   - switch (PPC_EXCP(env)) {
2087   - case PPC_FLAGS_EXCP_40x:
  2113 + switch (env->excp_model) {
  2114 + case POWERPC_EXCP_40x:
2088 2115 /* FIT on 4xx */
2089 2116 msr &= ~0xFFFF0000;
2090 2117 #if defined (DEBUG_EXCEPTIONS)
... ... @@ -2099,8 +2126,8 @@ void do_interrupt (CPUState *env)
2099 2126 return;
2100 2127 case 0x1020:
2101 2128 idx = 12;
2102   - switch (PPC_EXCP(env)) {
2103   - case PPC_FLAGS_EXCP_40x:
  2129 + switch (env->excp_model) {
  2130 + case POWERPC_EXCP_40x:
2104 2131 /* Watchdog on 4xx */
2105 2132 msr &= ~0xFFFF0000;
2106 2133 #if defined (DEBUG_EXCEPTIONS)
... ... @@ -2108,7 +2135,7 @@ void do_interrupt (CPUState *env)
2108 2135 fprintf(logfile, "WDT exception\n");
2109 2136 #endif
2110 2137 goto store_next;
2111   - case PPC_FLAGS_EXCP_BOOKE:
  2138 + case POWERPC_EXCP_BOOKE:
2112 2139 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2113 2140 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2114 2141 break;
... ... @@ -2119,16 +2146,18 @@ void do_interrupt (CPUState *env)
2119 2146 return;
2120 2147 case 0x1100:
2121 2148 idx = 13;
2122   - switch (PPC_EXCP(env)) {
2123   - case PPC_FLAGS_EXCP_40x:
  2149 + switch (env->excp_model) {
  2150 + case POWERPC_EXCP_40x:
2124 2151 /* DTLBMISS on 4xx */
2125 2152 msr &= ~0xFFFF0000;
2126 2153 goto store_next;
2127   - case PPC_FLAGS_EXCP_602:
2128   - case PPC_FLAGS_EXCP_603:
  2154 + case POWERPC_EXCP_602:
  2155 + case POWERPC_EXCP_603:
  2156 + case POWERPC_EXCP_603E:
  2157 + case POWERPC_EXCP_G2:
2129 2158 /* DLTLBMISS on 602/603 */
2130 2159 goto store_gprs;
2131   - case PPC_FLAGS_EXCP_7x5:
  2160 + case POWERPC_EXCP_7x5:
2132 2161 /* DLTLBMISS on 745/755 */
2133 2162 goto tlb_miss;
2134 2163 default:
... ... @@ -2138,13 +2167,15 @@ void do_interrupt (CPUState *env)
2138 2167 return;
2139 2168 case 0x1200:
2140 2169 idx = 14;
2141   - switch (PPC_EXCP(env)) {
2142   - case PPC_FLAGS_EXCP_40x:
  2170 + switch (env->excp_model) {
  2171 + case POWERPC_EXCP_40x:
2143 2172 /* ITLBMISS on 4xx */
2144 2173 msr &= ~0xFFFF0000;
2145 2174 goto store_next;
2146   - case PPC_FLAGS_EXCP_602:
2147   - case PPC_FLAGS_EXCP_603:
  2175 + case POWERPC_EXCP_602:
  2176 + case POWERPC_EXCP_603:
  2177 + case POWERPC_EXCP_603E:
  2178 + case POWERPC_EXCP_G2:
2148 2179 /* DSTLBMISS on 602/603 */
2149 2180 store_gprs:
2150 2181 /* Swap temporary saved registers with GPRs */
... ... @@ -2177,7 +2208,7 @@ void do_interrupt (CPUState *env)
2177 2208 }
2178 2209 #endif
2179 2210 goto tlb_miss;
2180   - case PPC_FLAGS_EXCP_7x5:
  2211 + case POWERPC_EXCP_7x5:
2181 2212 /* DSTLBMISS on 745/755 */
2182 2213 tlb_miss:
2183 2214 msr &= ~0xF83F0000;
... ... @@ -2192,13 +2223,15 @@ void do_interrupt (CPUState *env)
2192 2223 }
2193 2224 return;
2194 2225 case 0x1300:
2195   - switch (PPC_EXCP(env)) {
2196   - case PPC_FLAGS_EXCP_601:
2197   - case PPC_FLAGS_EXCP_602:
2198   - case PPC_FLAGS_EXCP_603:
2199   - case PPC_FLAGS_EXCP_604:
2200   - case PPC_FLAGS_EXCP_7x0:
2201   - case PPC_FLAGS_EXCP_7x5:
  2226 + switch (env->excp_model) {
  2227 + case POWERPC_EXCP_601:
  2228 + case POWERPC_EXCP_602:
  2229 + case POWERPC_EXCP_603:
  2230 + case POWERPC_EXCP_603E:
  2231 + case POWERPC_EXCP_G2:
  2232 + case POWERPC_EXCP_604:
  2233 + case POWERPC_EXCP_7x0:
  2234 + case POWERPC_EXCP_7x5:
2202 2235 /* IABR on 6xx/7xx */
2203 2236 /* XXX: TODO */
2204 2237 cpu_abort(env, "IABR exception is not implemented yet !\n");
... ... @@ -2209,13 +2242,15 @@ void do_interrupt (CPUState *env)
2209 2242 }
2210 2243 return;
2211 2244 case 0x1400:
2212   - switch (PPC_EXCP(env)) {
2213   - case PPC_FLAGS_EXCP_601:
2214   - case PPC_FLAGS_EXCP_602:
2215   - case PPC_FLAGS_EXCP_603:
2216   - case PPC_FLAGS_EXCP_604:
2217   - case PPC_FLAGS_EXCP_7x0:
2218   - case PPC_FLAGS_EXCP_7x5:
  2245 + switch (env->excp_model) {
  2246 + case POWERPC_EXCP_601:
  2247 + case POWERPC_EXCP_602:
  2248 + case POWERPC_EXCP_603:
  2249 + case POWERPC_EXCP_603E:
  2250 + case POWERPC_EXCP_G2:
  2251 + case POWERPC_EXCP_604:
  2252 + case POWERPC_EXCP_7x0:
  2253 + case POWERPC_EXCP_7x5:
2219 2254 /* SMI on 6xx/7xx */
2220 2255 /* XXX: TODO */
2221 2256 cpu_abort(env, "SMI exception is not implemented yet !\n");
... ... @@ -2226,20 +2261,20 @@ void do_interrupt (CPUState *env)
2226 2261 }
2227 2262 return;
2228 2263 case 0x1500:
2229   - switch (PPC_EXCP(env)) {
2230   - case PPC_FLAGS_EXCP_602:
  2264 + switch (env->excp_model) {
  2265 + case POWERPC_EXCP_602:
2231 2266 /* Watchdog on 602 */
2232 2267 /* XXX: TODO */
2233 2268 cpu_abort(env,
2234 2269 "602 watchdog exception is not implemented yet !\n");
2235 2270 goto store_next;
2236   - case PPC_FLAGS_EXCP_970:
  2271 + case POWERPC_EXCP_970:
2237 2272 /* Soft patch exception on 970 */
2238 2273 /* XXX: TODO */
2239 2274 cpu_abort(env,
2240 2275 "970 soft-patch exception is not implemented yet !\n");
2241 2276 goto store_next;
2242   - case PPC_FLAGS_EXCP_74xx:
  2277 + case POWERPC_EXCP_74xx:
2243 2278 /* VPU assist on 74xx */
2244 2279 /* XXX: TODO */
2245 2280 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
... ... @@ -2250,14 +2285,14 @@ void do_interrupt (CPUState *env)
2250 2285 }
2251 2286 return;
2252 2287 case 0x1600:
2253   - switch (PPC_EXCP(env)) {
2254   - case PPC_FLAGS_EXCP_602:
  2288 + switch (env->excp_model) {
  2289 + case POWERPC_EXCP_602:
2255 2290 /* Emulation trap on 602 */
2256 2291 /* XXX: TODO */
2257 2292 cpu_abort(env, "602 emulation trap exception "
2258 2293 "is not implemented yet !\n");
2259 2294 goto store_next;
2260   - case PPC_FLAGS_EXCP_970:
  2295 + case POWERPC_EXCP_970:
2261 2296 /* Maintenance exception on 970 */
2262 2297 /* XXX: TODO */
2263 2298 cpu_abort(env,
... ... @@ -2269,15 +2304,15 @@ void do_interrupt (CPUState *env)
2269 2304 }
2270 2305 return;
2271 2306 case 0x1700:
2272   - switch (PPC_EXCP(env)) {
2273   - case PPC_FLAGS_EXCP_7x0:
2274   - case PPC_FLAGS_EXCP_7x5:
  2307 + switch (env->excp_model) {
  2308 + case POWERPC_EXCP_7x0:
  2309 + case POWERPC_EXCP_7x5:
2275 2310 /* Thermal management interrupt on G3 */
2276 2311 /* XXX: TODO */
2277 2312 cpu_abort(env, "G3 thermal management exception "
2278 2313 "is not implemented yet !\n");
2279 2314 goto store_next;
2280   - case PPC_FLAGS_EXCP_970:
  2315 + case POWERPC_EXCP_970:
2281 2316 /* VPU assist on 970 */
2282 2317 /* XXX: TODO */
2283 2318 cpu_abort(env,
... ... @@ -2289,8 +2324,8 @@ void do_interrupt (CPUState *env)
2289 2324 }
2290 2325 return;
2291 2326 case 0x1800:
2292   - switch (PPC_EXCP(env)) {
2293   - case PPC_FLAGS_EXCP_970:
  2327 + switch (env->excp_model) {
  2328 + case POWERPC_EXCP_970:
2294 2329 /* Thermal exception on 970 */
2295 2330 /* XXX: TODO */
2296 2331 cpu_abort(env, "970 thermal management exception "
... ... @@ -2302,19 +2337,19 @@ void do_interrupt (CPUState *env)
2302 2337 }
2303 2338 return;
2304 2339 case 0x2000:
2305   - switch (PPC_EXCP(env)) {
2306   - case PPC_FLAGS_EXCP_40x:
  2340 + switch (env->excp_model) {
  2341 + case POWERPC_EXCP_40x:
2307 2342 /* DEBUG on 4xx */
2308 2343 /* XXX: TODO */
2309 2344 cpu_abort(env, "40x debug exception is not implemented yet !\n");
2310 2345 goto store_next;
2311   - case PPC_FLAGS_EXCP_601:
  2346 + case POWERPC_EXCP_601:
2312 2347 /* Run mode exception on 601 */
2313 2348 /* XXX: TODO */
2314 2349 cpu_abort(env,
2315 2350 "601 run mode exception is not implemented yet !\n");
2316 2351 goto store_next;
2317   - case PPC_FLAGS_EXCP_BOOKE:
  2352 + case POWERPC_EXCP_BOOKE:
2318 2353 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2319 2354 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2320 2355 break;
... ... @@ -2361,7 +2396,7 @@ void do_interrupt (CPUState *env)
2361 2396 msr_dr = 0;
2362 2397 msr_ri = 0;
2363 2398 msr_le = msr_ile;
2364   - if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
  2399 + if (env->excp_model == POWERPC_EXCP_BOOKE) {
2365 2400 msr_cm = msr_icm;
2366 2401 if (idx == -1 || (idx >= 16 && idx < 32)) {
2367 2402 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
... ...
target-ppc/op.c
  View file @a750fc0
... ... @@ -2319,7 +2319,6 @@ void OPPROTO op_405_check_satu (void)
2319 2319 RETURN();
2320 2320 }
2321 2321  
2322   -#if !defined(CONFIG_USER_ONLY)
2323 2322 void OPPROTO op_load_dcr (void)
2324 2323 {
2325 2324 do_load_dcr();
... ... @@ -2332,6 +2331,7 @@ void OPPROTO op_store_dcr (void)
2332 2331 RETURN();
2333 2332 }
2334 2333  
  2334 +#if !defined(CONFIG_USER_ONLY)
2335 2335 /* Return from critical interrupt :
2336 2336 * same as rfi, except nip & MSR are loaded from SRR2/3 instead of SRR0/1
2337 2337 */
... ...
target-ppc/op_helper.c
  View file @a750fc0
... ... @@ -1206,6 +1206,41 @@ void do_405_check_sat (void)
1206 1206 }
1207 1207 }
1208 1208  
  1209 +/* XXX: to be improved to check access rights when in user-mode */
  1210 +void do_load_dcr (void)
  1211 +{
  1212 + target_ulong val;
  1213 +
  1214 + if (unlikely(env->dcr_env == NULL)) {
  1215 + if (loglevel != 0) {
  1216 + fprintf(logfile, "No DCR environment\n");
  1217 + }
  1218 + do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
  1219 + } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
  1220 + if (loglevel != 0) {
  1221 + fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
  1222 + }
  1223 + do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
  1224 + } else {
  1225 + T0 = val;
  1226 + }
  1227 +}
  1228 +
  1229 +void do_store_dcr (void)
  1230 +{
  1231 + if (unlikely(env->dcr_env == NULL)) {
  1232 + if (loglevel != 0) {
  1233 + fprintf(logfile, "No DCR environment\n");
  1234 + }
  1235 + do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
  1236 + } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
  1237 + if (loglevel != 0) {
  1238 + fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
  1239 + }
  1240 + do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
  1241 + }
  1242 +}
  1243 +
1209 1244 #if !defined(CONFIG_USER_ONLY)
1210 1245 void do_40x_rfci (void)
1211 1246 {
... ... @@ -1268,40 +1303,6 @@ void do_rfmci (void)
1268 1303 env->interrupt_request = CPU_INTERRUPT_EXITTB;
1269 1304 }
1270 1305  
1271   -void do_load_dcr (void)
1272   -{
1273   - target_ulong val;
1274   -
1275   - if (unlikely(env->dcr_env == NULL)) {
1276   - if (loglevel != 0) {
1277   - fprintf(logfile, "No DCR environment\n");
1278   - }
1279   - do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1280   - } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1281   - if (loglevel != 0) {
1282   - fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1283   - }
1284   - do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1285   - } else {
1286   - T0 = val;
1287   - }
1288   -}
1289   -
1290   -void do_store_dcr (void)
1291   -{
1292   - if (unlikely(env->dcr_env == NULL)) {
1293   - if (loglevel != 0) {
1294   - fprintf(logfile, "No DCR environment\n");
1295   - }
1296   - do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1297   - } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1298   - if (loglevel != 0) {
1299   - fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1300   - }
1301   - do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1302   - }
1303   -}
1304   -
1305 1306 void do_load_403_pb (int num)
1306 1307 {
1307 1308 T0 = env->pb[num];
... ... @@ -2238,7 +2239,7 @@ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2238 2239 if (unlikely(ret != 0)) {
2239 2240 if (likely(retaddr)) {
2240 2241 /* now we have a real cpu fault */
2241   - pc = (target_phys_addr_t)retaddr;
  2242 + pc = (target_phys_addr_t)(unsigned long)retaddr;
2242 2243 tb = tb_find_pc(pc);
2243 2244 if (likely(tb)) {
2244 2245 /* the PC is inside the translated code. It means that we have
... ... @@ -2261,16 +2262,14 @@ void do_tlbie (void)
2261 2262 {
2262 2263 T0 = (uint32_t)T0;
2263 2264 #if !defined(FLUSH_ALL_TLBS)
2264   - if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
  2265 + /* XXX: Remove thoses tests */
  2266 + if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
2265 2267 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2266 2268 if (env->id_tlbs == 1)
2267 2269 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2268   - } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2269   - /* XXX: TODO */
2270   -#if 0
2271   - ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2272   - env->spr[SPR_BOOKE_PID]);
2273   -#endif
  2270 + } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
  2271 + ppc4xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
  2272 + env->spr[SPR_40x_PID]);
2274 2273 } else {
2275 2274 /* tlbie invalidate TLBs for all segments */
2276 2275 T0 &= TARGET_PAGE_MASK;
... ... @@ -2305,11 +2304,11 @@ void do_tlbie_64 (void)
2305 2304 {
2306 2305 T0 = (uint64_t)T0;
2307 2306 #if !defined(FLUSH_ALL_TLBS)
2308   - if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
  2307 + if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
2309 2308 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2310 2309 if (env->id_tlbs == 1)
2311 2310 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2312   - } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
  2311 + } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
2313 2312 /* XXX: TODO */
2314 2313 #if 0
2315 2314 ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
... ... @@ -2541,7 +2540,7 @@ void do_4xx_tlbwe_hi (void)
2541 2540 "are not supported (%d)\n",
2542 2541 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2543 2542 }
2544   - tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
  2543 + tlb->EPN = T1 & ~(tlb->size - 1);
2545 2544 if (T1 & 0x40)
2546 2545 tlb->prot |= PAGE_VALID;
2547 2546 else
... ... @@ -2676,14 +2675,14 @@ void do_440_tlbwe (int word)
2676 2675  
2677 2676 void do_440_tlbsx (void)
2678 2677 {
2679   - T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR]);
  2678 + T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
2680 2679 }
2681 2680  
2682 2681 void do_440_tlbsx_ (void)
2683 2682 {
2684 2683 int tmp = xer_so;
2685 2684  
2686   - T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR]);
  2685 + T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
2687 2686 if (T0 != -1)
2688 2687 tmp |= 0x02;
2689 2688 env->crf[0] = tmp;
... ...
target-ppc/op_helper.h
  View file @a750fc0
... ... @@ -167,9 +167,9 @@ void do_440_tlbwe (int word);
167 167 /* PowerPC 4xx specific helpers */
168 168 void do_405_check_ov (void);
169 169 void do_405_check_sat (void);
170   -#if !defined(CONFIG_USER_ONLY)
171 170 void do_load_dcr (void);
172 171 void do_store_dcr (void);
  172 +#if !defined(CONFIG_USER_ONLY)
173 173 void do_40x_rfci (void);
174 174 void do_rfci (void);
175 175 void do_rfdi (void);
... ...
target-ppc/translate.c
  View file @a750fc0
... ... @@ -27,11 +27,14 @@
27 27 #include "exec-all.h"
28 28 #include "disas.h"
29 29  
  30 +/* Include definitions for instructions classes and implementations flags */
30 31 //#define DO_SINGLE_STEP
31 32 //#define PPC_DEBUG_DISAS
32 33 //#define DEBUG_MEMORY_ACCESSES
33 34 //#define DO_PPC_STATISTICS
34 35  
  36 +/*****************************************************************************/
  37 +/* Code translation helpers */
35 38 #if defined(USE_DIRECT_JUMP)
36 39 #define TBPARAM(x)
37 40 #else
... ... @@ -175,8 +178,10 @@ struct opc_handler_t {
175 178 uint64_t type;
176 179 /* handler */
177 180 void (*handler)(DisasContext *ctx);
178   -#if defined(DO_PPC_STATISTICS)
  181 +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
179 182 const unsigned char *oname;
  183 +#endif
  184 +#if defined(DO_PPC_STATISTICS)
180 185 uint64_t count;
181 186 #endif
182 187 };
... ... @@ -249,6 +254,7 @@ typedef struct opcode_t {
249 254 const unsigned char *oname;
250 255 } opcode_t;
251 256  
  257 +/*****************************************************************************/
252 258 /*** Instruction decoding ***/
253 259 #define EXTRACT_HELPER(name, shift, nb) \
254 260 static inline uint32_t name (uint32_t opcode) \
... ... @@ -365,6 +371,106 @@ static inline target_ulong MASK (uint32_t start, uint32_t end)
365 371 return ret;
366 372 }
367 373  
  374 +/*****************************************************************************/
  375 +/* PowerPC Instructions types definitions */
  376 +enum {
  377 + PPC_NONE = 0x0000000000000000ULL,
  378 + /* integer operations instructions */
  379 + /* flow control instructions */
  380 + /* virtual memory instructions */
  381 + /* ld/st with reservation instructions */
  382 + /* cache control instructions */
  383 + /* spr/msr access instructions */
  384 + PPC_INSNS_BASE = 0x0000000000000001ULL,
  385 +#define PPC_INTEGER PPC_INSNS_BASE
  386 +#define PPC_FLOW PPC_INSNS_BASE
  387 +#define PPC_MEM PPC_INSNS_BASE
  388 +#define PPC_RES PPC_INSNS_BASE
  389 +#define PPC_CACHE PPC_INSNS_BASE
  390 +#define PPC_MISC PPC_INSNS_BASE
  391 + /* Optional floating point instructions */
  392 + PPC_FLOAT = 0x0000000000000002ULL,
  393 + PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
  394 + PPC_FLOAT_FRES = 0x0000000000000008ULL,
  395 + PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
  396 + PPC_FLOAT_FSEL = 0x0000000000000020ULL,
  397 + PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
  398 + /* external control instructions */
  399 + PPC_EXTERN = 0x0000000000000080ULL,
  400 + /* segment register access instructions */
  401 + PPC_SEGMENT = 0x0000000000000100ULL,
  402 + /* Optional cache control instruction */
  403 + PPC_CACHE_DCBA = 0x0000000000000200ULL,
  404 + /* Optional memory control instructions */
  405 + PPC_MEM_TLBIA = 0x0000000000000400ULL,
  406 + PPC_MEM_TLBIE = 0x0000000000000800ULL,
  407 + PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
  408 + /* eieio & sync */
  409 + PPC_MEM_SYNC = 0x0000000000002000ULL,
  410 + /* PowerPC 6xx TLB management instructions */
  411 + PPC_6xx_TLB = 0x0000000000004000ULL,
  412 + /* Altivec support */
  413 + PPC_ALTIVEC = 0x0000000000008000ULL,
  414 + /* Time base mftb instruction */
  415 + PPC_MFTB = 0x0000000000010000ULL,
  416 + /* Embedded PowerPC dedicated instructions */
  417 + PPC_EMB_COMMON = 0x0000000000020000ULL,
  418 + /* PowerPC 40x exception model */
  419 + PPC_40x_EXCP = 0x0000000000040000ULL,
  420 + /* PowerPC 40x TLB management instructions */
  421 + PPC_40x_TLB = 0x0000000000080000ULL,
  422 + /* PowerPC 405 Mac instructions */
  423 + PPC_405_MAC = 0x0000000000100000ULL,
  424 + /* PowerPC 440 specific instructions */
  425 + PPC_440_SPEC = 0x0000000000200000ULL,
  426 + /* Power-to-PowerPC bridge (601) */
  427 + PPC_POWER_BR = 0x0000000000400000ULL,
  428 + /* PowerPC 602 specific */
  429 + PPC_602_SPEC = 0x0000000000800000ULL,
  430 + /* Deprecated instructions */
  431 + /* Original POWER instruction set */
  432 + PPC_POWER = 0x0000000001000000ULL,
  433 + /* POWER2 instruction set extension */
  434 + PPC_POWER2 = 0x0000000002000000ULL,
  435 + /* Power RTC support */
  436 + PPC_POWER_RTC = 0x0000000004000000ULL,
  437 + /* 64 bits PowerPC instructions */
  438 + /* 64 bits PowerPC instruction set */
  439 + PPC_64B = 0x0000000008000000ULL,
  440 + /* 64 bits hypervisor extensions */
  441 + PPC_64H = 0x0000000010000000ULL,
  442 + /* 64 bits PowerPC "bridge" features */
  443 + PPC_64_BRIDGE = 0x0000000020000000ULL,
  444 + /* BookE (embedded) PowerPC specification */
  445 + PPC_BOOKE = 0x0000000040000000ULL,
  446 + /* eieio */
  447 + PPC_MEM_EIEIO = 0x0000000080000000ULL,
  448 + /* e500 vector instructions */
  449 + PPC_E500_VECTOR = 0x0000000100000000ULL,
  450 + /* PowerPC 4xx dedicated instructions */
  451 + PPC_4xx_COMMON = 0x0000000200000000ULL,
  452 + /* PowerPC 2.03 specification extensions */
  453 + PPC_203 = 0x0000000400000000ULL,
  454 + /* PowerPC 2.03 SPE extension */
  455 + PPC_SPE = 0x0000000800000000ULL,
  456 + /* PowerPC 2.03 SPE floating-point extension */
  457 + PPC_SPEFPU = 0x0000001000000000ULL,
  458 + /* SLB management */
  459 + PPC_SLBI = 0x0000002000000000ULL,
  460 + /* PowerPC 40x ibct instructions */
  461 + PPC_40x_ICBT = 0x0000004000000000ULL,
  462 + /* PowerPC 74xx TLB management instructions */
  463 + PPC_74xx_TLB = 0x0000008000000000ULL,
  464 + /* More BookE (embedded) instructions... */
  465 + PPC_BOOKE_EXT = 0x0000010000000000ULL,
  466 + /* rfmci is not implemented in all BookE PowerPC */
  467 + PPC_RFMCI = 0x0000020000000000ULL,
  468 + /* user-mode DCR access, implemented in PowerPC 460 */
  469 + PPC_DCRUX = 0x0000040000000000ULL,
  470 +};
  471 +
  472 +/*****************************************************************************/
  473 +/* PowerPC instructions table */
368 474 #if HOST_LONG_BITS == 64
369 475 #define OPC_ALIGN 8
370 476 #else
... ... @@ -845,15 +951,15 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
845 951  
846 952 #if defined(TARGET_PPC64)
847 953 /* mulhd mulhd. */
848   -GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_INTEGER);
  954 +GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
849 955 /* mulhdu mulhdu. */
850   -GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_INTEGER);
  956 +GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
851 957 /* mulld mulld. mulldo mulldo. */
852   -GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_INTEGER);
  958 +GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
853 959 /* divd divd. divdo divdo. */
854   -GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_INTEGER);
  960 +GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
855 961 /* divdu divdu. divduo divduo. */
856   -GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_INTEGER);
  962 +GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
857 963 #endif
858 964  
859 965 /*** Integer comparison ***/
... ... @@ -1424,8 +1530,8 @@ __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1424 1530 #endif
1425 1531  
1426 1532 /*** Floating-Point arithmetic ***/
1427   -#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
1428   -GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
  1533 +#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
  1534 +GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1429 1535 { \
1430 1536 if (unlikely(!ctx->fpu_enabled)) { \
1431 1537 RET_EXCP(ctx, EXCP_NO_FP, 0); \
... ... @@ -1444,9 +1550,9 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
1444 1550 gen_op_set_Rc1(); \
1445 1551 }
1446 1552  
1447   -#define GEN_FLOAT_ACB(name, op2) \
1448   -_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
1449   -_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
  1553 +#define GEN_FLOAT_ACB(name, op2, type) \
  1554 +_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
  1555 +_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1450 1556  
1451 1557 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
1452 1558 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
... ... @@ -1492,8 +1598,8 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1492 1598 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
1493 1599 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1494 1600  
1495   -#define GEN_FLOAT_B(name, op2, op3) \
1496   -GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
  1601 +#define GEN_FLOAT_B(name, op2, op3, type) \
  1602 +GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1497 1603 { \
1498 1604 if (unlikely(!ctx->fpu_enabled)) { \
1499 1605 RET_EXCP(ctx, EXCP_NO_FP, 0); \
... ... @@ -1507,8 +1613,8 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
1507 1613 gen_op_set_Rc1(); \
1508 1614 }
1509 1615  
1510   -#define GEN_FLOAT_BS(name, op1, op2) \
1511   -GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
  1616 +#define GEN_FLOAT_BS(name, op1, op2, type) \
  1617 +GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1512 1618 { \
1513 1619 if (unlikely(!ctx->fpu_enabled)) { \
1514 1620 RET_EXCP(ctx, EXCP_NO_FP, 0); \
... ... @@ -1529,19 +1635,19 @@ GEN_FLOAT_AB(div, 0x12, 0x000007C0);
1529 1635 /* fmul - fmuls */
1530 1636 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
1531 1637  
1532   -/* fres */ /* XXX: not in 601 */
1533   -GEN_FLOAT_BS(res, 0x3B, 0x18);
  1638 +/* fres */
  1639 +GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
1534 1640  
1535   -/* frsqrte */ /* XXX: not in 601 */
1536   -GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
  1641 +/* frsqrte */
  1642 +GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
1537 1643  
1538   -/* fsel */ /* XXX: not in 601 */
1539   -_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
  1644 +/* fsel */
  1645 +_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
1540 1646 /* fsub - fsubs */
1541 1647 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
1542 1648 /* Optional: */
1543 1649 /* fsqrt */
1544   -GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
  1650 +GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1545 1651 {
1546 1652 if (unlikely(!ctx->fpu_enabled)) {
1547 1653 RET_EXCP(ctx, EXCP_NO_FP, 0);
... ... @@ -1555,7 +1661,7 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
1555 1661 gen_op_set_Rc1();
1556 1662 }
1557 1663  
1558   -GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
  1664 +GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1559 1665 {
1560 1666 if (unlikely(!ctx->fpu_enabled)) {
1561 1667 RET_EXCP(ctx, EXCP_NO_FP, 0);
... ... @@ -1572,28 +1678,28 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
1572 1678  
1573 1679 /*** Floating-Point multiply-and-add ***/
1574 1680 /* fmadd - fmadds */
1575   -GEN_FLOAT_ACB(madd, 0x1D);
  1681 +GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
1576 1682 /* fmsub - fmsubs */
1577   -GEN_FLOAT_ACB(msub, 0x1C);
  1683 +GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
1578 1684 /* fnmadd - fnmadds */
1579   -GEN_FLOAT_ACB(nmadd, 0x1F);
  1685 +GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
1580 1686 /* fnmsub - fnmsubs */
1581   -GEN_FLOAT_ACB(nmsub, 0x1E);
  1687 +GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
1582 1688  
1583 1689 /*** Floating-Point round & convert ***/
1584 1690 /* fctiw */
1585   -GEN_FLOAT_B(ctiw, 0x0E, 0x00);
  1691 +GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
1586 1692 /* fctiwz */
1587   -GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
  1693 +GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
1588 1694 /* frsp */
1589   -GEN_FLOAT_B(rsp, 0x0C, 0x00);
  1695 +GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
1590 1696 #if defined(TARGET_PPC64)
1591 1697 /* fcfid */
1592   -GEN_FLOAT_B(cfid, 0x0E, 0x1A);
  1698 +GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
1593 1699 /* fctid */
1594   -GEN_FLOAT_B(ctid, 0x0E, 0x19);
  1700 +GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
1595 1701 /* fctidz */
1596   -GEN_FLOAT_B(ctidz, 0x0F, 0x19);
  1702 +GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
1597 1703 #endif
1598 1704  
1599 1705 /*** Floating-Point compare ***/
... ... @@ -1627,7 +1733,7 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1627 1733  
1628 1734 /*** Floating-point move ***/
1629 1735 /* fabs */
1630   -GEN_FLOAT_B(abs, 0x08, 0x08);
  1736 +GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
1631 1737  
1632 1738 /* fmr - fmr. */
1633 1739 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
... ... @@ -1644,9 +1750,9 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1644 1750 }
1645 1751  
1646 1752 /* fnabs */
1647   -GEN_FLOAT_B(nabs, 0x08, 0x04);
  1753 +GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
1648 1754 /* fneg */
1649   -GEN_FLOAT_B(neg, 0x08, 0x01);
  1755 +GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
1650 1756  
1651 1757 /*** Floating-Point status & ctrl register ***/
1652 1758 /* mcrfs */
... ... @@ -2426,7 +2532,7 @@ static GenOpFunc *gen_op_stdcx[] = {
2426 2532 #endif
2427 2533  
2428 2534 /* ldarx */
2429   -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_RES)
  2535 +GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2430 2536 {
2431 2537 gen_addr_reg_index(ctx);
2432 2538 op_ldarx();
... ... @@ -2434,7 +2540,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_RES)
2434 2540 }
2435 2541  
2436 2542 /* stdcx. */
2437   -GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_RES)
  2543 +GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2438 2544 {
2439 2545 gen_addr_reg_index(ctx);
2440 2546 gen_op_load_gpr_T1(rS(ctx->opcode));
... ... @@ -2591,7 +2697,7 @@ GEN_STFS(fs, 0x14);
2591 2697  
2592 2698 /* Optional: */
2593 2699 /* stfiwx */
2594   -GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
  2700 +GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT_STFIWX)
2595 2701 {
2596 2702 if (unlikely(!ctx->fpu_enabled)) {
2597 2703 RET_EXCP(ctx, EXCP_NO_FP, 0);
... ... @@ -2886,7 +2992,7 @@ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
2886 2992 }
2887 2993  
2888 2994 #if defined(TARGET_PPC64)
2889   -GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_FLOW)
  2995 +GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
2890 2996 {
2891 2997 #if defined(CONFIG_USER_ONLY)
2892 2998 RET_PRIVOPC(ctx);
... ... @@ -3050,7 +3156,7 @@ GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3050 3156 }
3051 3157  
3052 3158 /* mftb */
3053   -GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
  3159 +GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3054 3160 {
3055 3161 gen_op_mfspr(ctx);
3056 3162 }
... ... @@ -3074,7 +3180,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3074 3180  
3075 3181 /* mtmsr */
3076 3182 #if defined(TARGET_PPC64)
3077   -GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001FF801, PPC_MISC)
  3183 +GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001FF801, PPC_64B)
3078 3184 {
3079 3185 #if defined(CONFIG_USER_ONLY)
3080 3186 RET_PRIVREG(ctx);
... ... @@ -3296,7 +3402,7 @@ GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3296 3402  
3297 3403 /* Optional: */
3298 3404 /* dcba */
3299   -GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
  3405 +GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3300 3406 {
3301 3407 }
3302 3408  
... ... @@ -3568,7 +3674,7 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3568 3674 }
3569 3675  
3570 3676 /* clcs */
3571   -GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) /* 601 ? */
  3677 +GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3572 3678 {
3573 3679 gen_op_load_gpr_T0(rA(ctx->opcode));
3574 3680 gen_op_POWER_clcs();
... ... @@ -4222,14 +4328,14 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4222 4328  
4223 4329 /* BookE specific instructions */
4224 4330 /* XXX: not implemented on 440 ? */
4225   -GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE)
  4331 +GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
4226 4332 {
4227 4333 /* XXX: TODO */
4228 4334 RET_INVAL(ctx);
4229 4335 }
4230 4336  
4231 4337 /* XXX: not implemented on 440 ? */
4232   -GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE)
  4338 +GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
4233 4339 {
4234 4340 #if defined(CONFIG_USER_ONLY)
4235 4341 RET_PRIVOPC(ctx);
... ... @@ -4331,99 +4437,98 @@ static inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3,
4331 4437 }
4332 4438 }
4333 4439  
4334   -#define GEN_MAC_HANDLER(name, opc2, opc3, is_440) \
4335   -GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, \
4336   - is_440 ? PPC_440_SPEC : PPC_405_MAC) \
  4440 +#define GEN_MAC_HANDLER(name, opc2, opc3) \
  4441 +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4337 4442 { \
4338 4443 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4339 4444 rD(ctx->opcode), Rc(ctx->opcode)); \
4340 4445 }
4341 4446  
4342 4447 /* macchw - macchw. */
4343   -GEN_MAC_HANDLER(macchw, 0x0C, 0x05, 0);
  4448 +GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4344 4449 /* macchwo - macchwo. */
4345   -GEN_MAC_HANDLER(macchwo, 0x0C, 0x15, 0);
  4450 +GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4346 4451 /* macchws - macchws. */
4347   -GEN_MAC_HANDLER(macchws, 0x0C, 0x07, 0);
  4452 +GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4348 4453 /* macchwso - macchwso. */
4349   -GEN_MAC_HANDLER(macchwso, 0x0C, 0x17, 0);
  4454 +GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4350 4455 /* macchwsu - macchwsu. */
4351   -GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06, 0);
  4456 +GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4352 4457 /* macchwsuo - macchwsuo. */
4353   -GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16, 0);
  4458 +GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4354 4459 /* macchwu - macchwu. */
4355   -GEN_MAC_HANDLER(macchwu, 0x0C, 0x04, 0);
  4460 +GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4356 4461 /* macchwuo - macchwuo. */
4357   -GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14, 0);
  4462 +GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4358 4463 /* machhw - machhw. */
4359   -GEN_MAC_HANDLER(machhw, 0x0C, 0x01, 0);
  4464 +GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4360 4465 /* machhwo - machhwo. */
4361   -GEN_MAC_HANDLER(machhwo, 0x0C, 0x11, 0);
  4466 +GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4362 4467 /* machhws - machhws. */
4363   -GEN_MAC_HANDLER(machhws, 0x0C, 0x03, 0);
  4468 +GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4364 4469 /* machhwso - machhwso. */
4365   -GEN_MAC_HANDLER(machhwso, 0x0C, 0x13, 0);
  4470 +GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4366 4471 /* machhwsu - machhwsu. */
4367   -GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02, 0);
  4472 +GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4368 4473 /* machhwsuo - machhwsuo. */
4369   -GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12, 0);
  4474 +GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4370 4475 /* machhwu - machhwu. */
4371   -GEN_MAC_HANDLER(machhwu, 0x0C, 0x00, 0);
  4476 +GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4372 4477 /* machhwuo - machhwuo. */
4373   -GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10, 0);
  4478 +GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4374 4479 /* maclhw - maclhw. */
4375   -GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D, 0);
  4480 +GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4376 4481 /* maclhwo - maclhwo. */
4377   -GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D, 0);
  4482 +GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4378 4483 /* maclhws - maclhws. */
4379   -GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F, 0);
  4484 +GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4380 4485 /* maclhwso - maclhwso. */
4381   -GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F, 0);
  4486 +GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4382 4487 /* maclhwu - maclhwu. */
4383   -GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C, 0);
  4488 +GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4384 4489 /* maclhwuo - maclhwuo. */
4385   -GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C, 0);
  4490 +GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4386 4491 /* maclhwsu - maclhwsu. */
4387   -GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E, 0);
  4492 +GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4388 4493 /* maclhwsuo - maclhwsuo. */
4389   -GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E, 0);
  4494 +GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4390 4495 /* nmacchw - nmacchw. */
4391   -GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05, 0);
  4496 +GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4392 4497 /* nmacchwo - nmacchwo. */
4393   -GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15, 0);
  4498 +GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4394 4499 /* nmacchws - nmacchws. */
4395   -GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07, 0);
  4500 +GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4396 4501 /* nmacchwso - nmacchwso. */
4397   -GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17, 0);
  4502 +GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4398 4503 /* nmachhw - nmachhw. */
4399   -GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01, 0);
  4504 +GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4400 4505 /* nmachhwo - nmachhwo. */
4401   -GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11, 0);
  4506 +GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4402 4507 /* nmachhws - nmachhws. */
4403   -GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03, 1);
  4508 +GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4404 4509 /* nmachhwso - nmachhwso. */
4405   -GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13, 1);
  4510 +GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4406 4511 /* nmaclhw - nmaclhw. */
4407   -GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D, 1);
  4512 +GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4408 4513 /* nmaclhwo - nmaclhwo. */
4409   -GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D, 1);
  4514 +GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
4410 4515 /* nmaclhws - nmaclhws. */
4411   -GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F, 1);
  4516 +GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
4412 4517 /* nmaclhwso - nmaclhwso. */
4413   -GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F, 1);
  4518 +GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
4414 4519  
4415 4520 /* mulchw - mulchw. */
4416   -GEN_MAC_HANDLER(mulchw, 0x08, 0x05, 0);
  4521 +GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
4417 4522 /* mulchwu - mulchwu. */
4418   -GEN_MAC_HANDLER(mulchwu, 0x08, 0x04, 0);
  4523 +GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
4419 4524 /* mulhhw - mulhhw. */
4420   -GEN_MAC_HANDLER(mulhhw, 0x08, 0x01, 0);
  4525 +GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
4421 4526 /* mulhhwu - mulhhwu. */
4422   -GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00, 0);
  4527 +GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
4423 4528 /* mullhw - mullhw. */
4424   -GEN_MAC_HANDLER(mullhw, 0x08, 0x0D, 0);
  4529 +GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4425 4530 /* mullhwu - mullhwu. */
4426   -GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C, 0);
  4531 +GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4427 4532  
4428 4533 /* mfdcr */
4429 4534 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
... ... @@ -4463,7 +4568,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
4463 4568  
4464 4569 /* mfdcrx */
4465 4570 /* XXX: not implemented on 440 ? */
4466   -GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE)
  4571 +GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
4467 4572 {
4468 4573 #if defined(CONFIG_USER_ONLY)
4469 4574 RET_PRIVREG(ctx);
... ... @@ -4475,12 +4580,13 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE)
4475 4580 gen_op_load_gpr_T0(rA(ctx->opcode));
4476 4581 gen_op_load_dcr();
4477 4582 gen_op_store_T0_gpr(rD(ctx->opcode));
  4583 + /* Note: Rc update flag set leads to undefined state of Rc0 */
4478 4584 #endif
4479 4585 }
4480 4586  
4481 4587 /* mtdcrx */
4482 4588 /* XXX: not implemented on 440 ? */
4483   -GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE)
  4589 +GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
4484 4590 {
4485 4591 #if defined(CONFIG_USER_ONLY)
4486 4592 RET_PRIVREG(ctx);
... ... @@ -4492,9 +4598,28 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE)
4492 4598 gen_op_load_gpr_T0(rA(ctx->opcode));
4493 4599 gen_op_load_gpr_T1(rS(ctx->opcode));
4494 4600 gen_op_store_dcr();
  4601 + /* Note: Rc update flag set leads to undefined state of Rc0 */
4495 4602 #endif
4496 4603 }
4497 4604  
  4605 +/* mfdcrux (PPC 460) : user-mode access to DCR */
  4606 +GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
  4607 +{
  4608 + gen_op_load_gpr_T0(rA(ctx->opcode));
  4609 + gen_op_load_dcr();
  4610 + gen_op_store_T0_gpr(rD(ctx->opcode));
  4611 + /* Note: Rc update flag set leads to undefined state of Rc0 */
  4612 +}
  4613 +
  4614 +/* mtdcrux (PPC 460) : user-mode access to DCR */
  4615 +GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
  4616 +{
  4617 + gen_op_load_gpr_T0(rA(ctx->opcode));
  4618 + gen_op_load_gpr_T1(rS(ctx->opcode));
  4619 + gen_op_store_dcr();
  4620 + /* Note: Rc update flag set leads to undefined state of Rc0 */
  4621 +}
  4622 +
4498 4623 /* dccci */
4499 4624 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4500 4625 {
... ... @@ -4595,7 +4720,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4595 4720  
4596 4721 /* BookE specific */
4597 4722 /* XXX: not implemented on 440 ? */
4598   -GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE)
  4723 +GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
4599 4724 {
4600 4725 #if defined(CONFIG_USER_ONLY)
4601 4726 RET_PRIVOPC(ctx);
... ... @@ -4611,7 +4736,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE)
4611 4736 }
4612 4737  
4613 4738 /* XXX: not implemented on 440 ? */
4614   -GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE)
  4739 +GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
4615 4740 {
4616 4741 #if defined(CONFIG_USER_ONLY)
4617 4742 RET_PRIVOPC(ctx);
... ... @@ -4628,7 +4753,7 @@ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE)
4628 4753  
4629 4754 /* TLB management - PowerPC 405 implementation */
4630 4755 /* tlbre */
4631   -GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_SPEC)
  4756 +GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
4632 4757 {
4633 4758 #if defined(CONFIG_USER_ONLY)
4634 4759 RET_PRIVOPC(ctx);
... ... @@ -4656,7 +4781,7 @@ GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_SPEC)
4656 4781 }
4657 4782  
4658 4783 /* tlbsx - tlbsx. */
4659   -GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_SPEC)
  4784 +GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
4660 4785 {
4661 4786 #if defined(CONFIG_USER_ONLY)
4662 4787 RET_PRIVOPC(ctx);
... ... @@ -4675,7 +4800,7 @@ GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_SPEC)
4675 4800 }
4676 4801  
4677 4802 /* tlbwe */
4678   -GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_SPEC)
  4803 +GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
4679 4804 {
4680 4805 #if defined(CONFIG_USER_ONLY)
4681 4806 RET_PRIVOPC(ctx);
... ... @@ -5701,7 +5826,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
5701 5826 for (i = 0; i < 32; i++) {
5702 5827 if ((i & (RGPL - 1)) == 0)
5703 5828 cpu_fprintf(f, "GPR%02d", i);
5704   - cpu_fprintf(f, " " REGX, env->gpr[i]);
  5829 + cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
5705 5830 if ((i & (RGPL - 1)) == (RGPL - 1))
5706 5831 cpu_fprintf(f, "\n");
5707 5832 }
... ...
target-ppc/translate_init.c
  View file @a750fc0
Changes suppressed. Click to show.
... ... @@ -32,20 +32,26 @@ struct ppc_def_t {
32 32 uint32_t pvr;
33 33 uint32_t pvr_mask;
34 34 uint64_t insns_flags;
35   - uint32_t flags;
36 35 uint64_t msr_mask;
  36 + uint8_t mmu_model;
  37 + uint8_t excp_model;
  38 + uint8_t bus_model;
  39 + uint8_t pad;
  40 + void (*init_proc)(CPUPPCState *env);
37 41 };
38 42  
39 43 /* For user-mode emulation, we don't emulate any IRQ controller */
40 44 #if defined(CONFIG_USER_ONLY)
41   -#define PPC_IRQ_INIT_FN(name) \
42   -static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43   -{ \
  45 +#define PPC_IRQ_INIT_FN(name) \
  46 +static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
  47 +{ \
44 48 }
45 49 #else
46   -#define PPC_IRQ_INIT_FN(name) \
  50 +#define PPC_IRQ_INIT_FN(name) \
47 51 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 52 #endif
  53 +
  54 +PPC_IRQ_INIT_FN(401);
49 55 PPC_IRQ_INIT_FN(405);
50 56 PPC_IRQ_INIT_FN(6xx);
51 57 PPC_IRQ_INIT_FN(970);
... ... @@ -285,7 +291,7 @@ static void spr_write_asr (void *opaque, int sprn)
285 291 RET_STOP(ctx);
286 292 }
287 293 #endif
288   -#endif /* !defined(CONFIG_USER_ONLY) */
  294 +#endif
289 295  
290 296 /* PowerPC 601 specific registers */
291 297 /* RTC */
... ... @@ -582,7 +588,7 @@ static void gen_low_BATs (CPUPPCState *env)
582 588 SPR_NOACCESS, SPR_NOACCESS,
583 589 &spr_read_dbat, &spr_write_dbatl,
584 590 0x00000000);
585   - env->nb_BATs = 4;
  591 + env->nb_BATs += 4;
586 592 }
587 593  
588 594 /* BATs 4-7 */
... ... @@ -652,7 +658,7 @@ static void gen_high_BATs (CPUPPCState *env)
652 658 SPR_NOACCESS, SPR_NOACCESS,
653 659 &spr_read_dbat_h, &spr_write_dbatl_h,
654 660 0x00000000);
655   - env->nb_BATs = 8;
  661 + env->nb_BATs += 4;
656 662 }
657 663  
658 664 /* Generic PowerPC time base */
... ... @@ -797,7 +803,7 @@ static void gen_spr_7xx (CPUPPCState *env)
797 803 &spr_read_generic, &spr_write_generic,
798 804 0x00000000);
799 805 /* XXX : not implemented */
800   - spr_register(env, SPR_SIA, "SIA",
  806 + spr_register(env, SPR_SIAR, "SIAR",
801 807 SPR_NOACCESS, SPR_NOACCESS,
802 808 &spr_read_generic, SPR_NOACCESS,
803 809 0x00000000);
... ... @@ -825,29 +831,33 @@ static void gen_spr_7xx (CPUPPCState *env)
825 831 &spr_read_ureg, SPR_NOACCESS,
826 832 &spr_read_ureg, SPR_NOACCESS,
827 833 0x00000000);
828   - spr_register(env, SPR_USIA, "USIA",
  834 + spr_register(env, SPR_USIAR, "USIAR",
829 835 &spr_read_ureg, SPR_NOACCESS,
830 836 &spr_read_ureg, SPR_NOACCESS,
831 837 0x00000000);
832   - /* Thermal management */
  838 + /* External access control */
833 839 /* XXX : not implemented */
834   - spr_register(env, SPR_THRM1, "THRM1",
  840 + spr_register(env, SPR_EAR, "EAR",
835 841 SPR_NOACCESS, SPR_NOACCESS,
836 842 &spr_read_generic, &spr_write_generic,
837 843 0x00000000);
  844 +}
  845 +
  846 +static void gen_spr_thrm (CPUPPCState *env)
  847 +{
  848 + /* Thermal management */
838 849 /* XXX : not implemented */
839   - spr_register(env, SPR_THRM2, "THRM2",
  850 + spr_register(env, SPR_THRM1, "THRM1",
840 851 SPR_NOACCESS, SPR_NOACCESS,
841 852 &spr_read_generic, &spr_write_generic,
842 853 0x00000000);
843 854 /* XXX : not implemented */
844   - spr_register(env, SPR_THRM3, "THRM3",
  855 + spr_register(env, SPR_THRM2, "THRM2",
845 856 SPR_NOACCESS, SPR_NOACCESS,
846 857 &spr_read_generic, &spr_write_generic,
847 858 0x00000000);
848   - /* External access control */
849 859 /* XXX : not implemented */
850   - spr_register(env, SPR_EAR, "EAR",
  860 + spr_register(env, SPR_THRM3, "THRM3",
851 861 SPR_NOACCESS, SPR_NOACCESS,
852 862 &spr_read_generic, &spr_write_generic,
853 863 0x00000000);
... ... @@ -904,7 +914,7 @@ static void gen_spr_604 (CPUPPCState *env)
904 914 &spr_read_generic, &spr_write_generic,
905 915 0x00000000);
906 916 /* XXX : not implemented */
907   - spr_register(env, SPR_SIA, "SIA",
  917 + spr_register(env, SPR_SIAR, "SIAR",
908 918 SPR_NOACCESS, SPR_NOACCESS,
909 919 &spr_read_generic, SPR_NOACCESS,
910 920 0x00000000);
... ... @@ -1004,7 +1014,7 @@ static void gen_spr_602 (CPUPPCState *env)
1004 1014 &spr_read_generic, &spr_write_generic,
1005 1015 0x00000000);
1006 1016 /* XXX : not implemented */
1007   - spr_register(env, SPR_ESASR, "ESASR",
  1017 + spr_register(env, SPR_ESASRR, "ESASRR",
1008 1018 SPR_NOACCESS, SPR_NOACCESS,
1009 1019 &spr_read_generic, &spr_write_generic,
1010 1020 0x00000000);
... ... @@ -1030,6 +1040,11 @@ static void gen_spr_602 (CPUPPCState *env)
1030 1040 SPR_NOACCESS, SPR_NOACCESS,
1031 1041 &spr_read_generic, &spr_write_generic,
1032 1042 0x00000000);
  1043 + /* XXX : not implemented */
  1044 + spr_register(env, SPR_IABR, "IABR",
  1045 + SPR_NOACCESS, SPR_NOACCESS,
  1046 + &spr_read_generic, &spr_write_generic,
  1047 + 0x00000000);
1033 1048 }
1034 1049  
1035 1050 /* SPR specific to PowerPC 601 implementation */
... ... @@ -1104,7 +1119,116 @@ static void gen_spr_601 (CPUPPCState *env)
1104 1119 SPR_NOACCESS, SPR_NOACCESS,
1105 1120 &spr_read_601_ubat, &spr_write_601_ubatl,
1106 1121 0x00000000);
  1122 + env->nb_BATs = 4;
  1123 +}
  1124 +
  1125 +static void gen_spr_74xx (CPUPPCState *env)
  1126 +{
  1127 + /* Processor identification */
  1128 + spr_register(env, SPR_PIR, "PIR",
  1129 + SPR_NOACCESS, SPR_NOACCESS,
  1130 + &spr_read_generic, &spr_write_pir,
  1131 + 0x00000000);
  1132 + /* XXX : not implemented */
  1133 + spr_register(env, SPR_MMCR2, "MMCR2",
  1134 + SPR_NOACCESS, SPR_NOACCESS,
  1135 + &spr_read_generic, &spr_write_generic,
  1136 + 0x00000000);
  1137 + spr_register(env, SPR_UMMCR2, "UMMCR2",
  1138 + &spr_read_ureg, SPR_NOACCESS,
  1139 + &spr_read_ureg, SPR_NOACCESS,
  1140 + 0x00000000);
  1141 + /* XXX: not implemented */
  1142 + spr_register(env, SPR_BAMR, "BAMR",
  1143 + SPR_NOACCESS, SPR_NOACCESS,
  1144 + &spr_read_generic, &spr_write_generic,
  1145 + 0x00000000);
  1146 + spr_register(env, SPR_UBAMR, "UBAMR",
  1147 + &spr_read_ureg, SPR_NOACCESS,
  1148 + &spr_read_ureg, SPR_NOACCESS,
  1149 + 0x00000000);
  1150 + spr_register(env, SPR_MSSCR0, "MSSCR0",
  1151 + SPR_NOACCESS, SPR_NOACCESS,
  1152 + &spr_read_generic, &spr_write_generic,
  1153 + 0x00000000);
  1154 + /* Hardware implementation registers */
  1155 + /* XXX : not implemented */
  1156 + spr_register(env, SPR_HID0, "HID0",
  1157 + SPR_NOACCESS, SPR_NOACCESS,
  1158 + &spr_read_generic, &spr_write_generic,
  1159 + 0x00000000);
  1160 + /* XXX : not implemented */
  1161 + spr_register(env, SPR_HID1, "HID1",
  1162 + SPR_NOACCESS, SPR_NOACCESS,
  1163 + &spr_read_generic, &spr_write_generic,
  1164 + 0x00000000);
  1165 + /* Altivec */
  1166 + spr_register(env, SPR_VRSAVE, "VRSAVE",
  1167 + &spr_read_generic, &spr_write_generic,
  1168 + &spr_read_generic, &spr_write_generic,
  1169 + 0x00000000);
  1170 +}
  1171 +
  1172 +#if defined (TODO)
  1173 +static void gen_l3_ctrl (CPUPPCState *env)
  1174 +{
  1175 + /* L3CR */
  1176 + /* XXX : not implemented */
  1177 + spr_register(env, SPR_L3CR, "L3CR",
  1178 + SPR_NOACCESS, SPR_NOACCESS,
  1179 + &spr_read_generic, &spr_write_generic,
  1180 + 0x00000000);
  1181 + /* L3ITCR0 */
  1182 + spr_register(env, SPR_L3ITCR0, "L3ITCR0",
  1183 + SPR_NOACCESS, SPR_NOACCESS,
  1184 + &spr_read_generic, &spr_write_generic,
  1185 + 0x00000000);
  1186 + /* L3ITCR1 */
  1187 + spr_register(env, SPR_L3ITCR1, "L3ITCR1",
  1188 + SPR_NOACCESS, SPR_NOACCESS,
  1189 + &spr_read_generic, &spr_write_generic,
  1190 + 0x00000000);
  1191 + /* L3ITCR2 */
  1192 + spr_register(env, SPR_L3ITCR2, "L3ITCR2",
  1193 + SPR_NOACCESS, SPR_NOACCESS,
  1194 + &spr_read_generic, &spr_write_generic,
  1195 + 0x00000000);
  1196 + /* L3ITCR3 */
  1197 + spr_register(env, SPR_L3ITCR3, "L3ITCR3",
  1198 + SPR_NOACCESS, SPR_NOACCESS,
  1199 + &spr_read_generic, &spr_write_generic,
  1200 + 0x00000000);
  1201 + /* L3OHCR */
  1202 + spr_register(env, SPR_L3OHCR, "L3OHCR",
  1203 + SPR_NOACCESS, SPR_NOACCESS,
  1204 + &spr_read_generic, &spr_write_generic,
  1205 + 0x00000000);
  1206 + /* L3PM */
  1207 + spr_register(env, SPR_L3PM, "L3PM",
  1208 + SPR_NOACCESS, SPR_NOACCESS,
  1209 + &spr_read_generic, &spr_write_generic,
  1210 + 0x00000000);
  1211 +}
  1212 +#endif /* TODO */
  1213 +
  1214 +#if defined (TODO)
  1215 +static void gen_74xx_soft_tlb (CPUPPCState *env)
  1216 +{
  1217 + /* XXX: TODO */
  1218 + spr_register(env, SPR_PTEHI, "PTEHI",
  1219 + SPR_NOACCESS, SPR_NOACCESS,
  1220 + &spr_read_generic, &spr_write_generic,
  1221 + 0x00000000);
  1222 + spr_register(env, SPR_PTELO, "PTELO",
  1223 + SPR_NOACCESS, SPR_NOACCESS,
  1224 + &spr_read_generic, &spr_write_generic,
  1225 + 0x00000000);
  1226 + spr_register(env, SPR_TLBMISS, "TLBMISS",
  1227 + SPR_NOACCESS, SPR_NOACCESS,
  1228 + &spr_read_generic, &spr_write_generic,
  1229 + 0x00000000);
1107 1230 }
  1231 +#endif /* TODO */
1108 1232  
1109 1233 /* PowerPC BookE SPR */
1110 1234 static void gen_spr_BookE (CPUPPCState *env)
... ... @@ -1132,14 +1256,6 @@ static void gen_spr_BookE (CPUPPCState *env)
1132 1256 SPR_NOACCESS, SPR_NOACCESS,
1133 1257 &spr_read_generic, &spr_write_generic,
1134 1258 0x00000000);
1135   - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1136   - SPR_NOACCESS, SPR_NOACCESS,
1137   - &spr_read_generic, &spr_write_generic,
1138   - 0x00000000);
1139   - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1140   - SPR_NOACCESS, SPR_NOACCESS,
1141   - &spr_read_generic, &spr_write_generic,
1142   - 0x00000000);
1143 1259 #endif
1144 1260 /* Debug */
1145 1261 /* XXX : not implemented */
... ... @@ -1366,6 +1482,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1366 1482 }
1367 1483  
1368 1484 /* FSL storage control registers */
  1485 +#if defined(TODO)
1369 1486 static void gen_spr_BookE_FSL (CPUPPCState *env)
1370 1487 {
1371 1488 /* TLB assist registers */
... ... @@ -1447,6 +1564,7 @@ static void gen_spr_BookE_FSL (CPUPPCState *env)
1447 1564 break;
1448 1565 }
1449 1566 }
  1567 +#endif
1450 1568  
1451 1569 /* SPR specific to PowerPC 440 implementation */
1452 1570 static void gen_spr_440 (CPUPPCState *env)
... ... @@ -1599,11 +1717,6 @@ static void gen_spr_40x (CPUPPCState *env)
1599 1717 &spr_read_generic, &spr_write_generic,
1600 1718 0x00000000);
1601 1719 /* XXX : not implemented */
1602   - spr_register(env, SPR_40x_DCWR, "DCWR",
1603   - SPR_NOACCESS, SPR_NOACCESS,
1604   - &spr_read_generic, &spr_write_generic,
1605   - 0x00000000);
1606   - /* XXX : not implemented */
1607 1720 spr_register(env, SPR_40x_ICCR, "ICCR",
1608 1721 SPR_NOACCESS, SPR_NOACCESS,
1609 1722 &spr_read_generic, &spr_write_generic,
... ... @@ -1613,11 +1726,6 @@ static void gen_spr_40x (CPUPPCState *env)
1613 1726 SPR_NOACCESS, SPR_NOACCESS,
1614 1727 &spr_read_generic, SPR_NOACCESS,
1615 1728 0x00000000);
1616   - /* Bus access control */
1617   - spr_register(env, SPR_40x_SGR, "SGR",
1618   - SPR_NOACCESS, SPR_NOACCESS,
1619   - &spr_read_generic, &spr_write_generic,
1620   - 0xFFFFFFFF);
1621 1729 /* Exception */
1622 1730 spr_register(env, SPR_40x_DEAR, "DEAR",
1623 1731 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -1834,6 +1942,19 @@ static void gen_spr_401 (CPUPPCState *env)
1834 1942 0x00000000);
1835 1943 }
1836 1944  
  1945 +static void gen_spr_401x2 (CPUPPCState *env)
  1946 +{
  1947 + gen_spr_401(env);
  1948 + spr_register(env, SPR_40x_PID, "PID",
  1949 + SPR_NOACCESS, SPR_NOACCESS,
  1950 + &spr_read_generic, &spr_write_generic,
  1951 + 0x00000000);
  1952 + spr_register(env, SPR_40x_ZPR, "ZPR",
  1953 + SPR_NOACCESS, SPR_NOACCESS,
  1954 + &spr_read_generic, &spr_write_generic,
  1955 + 0x00000000);
  1956 +}
  1957 +
1837 1958 /* SPR specific to PowerPC 403 implementation */
1838 1959 static void gen_spr_403 (CPUPPCState *env)
1839 1960 {
... ... @@ -1867,11 +1988,10 @@ static void gen_spr_403 (CPUPPCState *env)
1867 1988 SPR_NOACCESS, SPR_NOACCESS,
1868 1989 &spr_read_generic, &spr_write_generic,
1869 1990 0x00000000);
1870   - /* MMU */
1871   - spr_register(env, SPR_40x_PID, "PID",
1872   - SPR_NOACCESS, SPR_NOACCESS,
1873   - &spr_read_generic, &spr_write_generic,
1874   - 0x00000000);
  1991 +}
  1992 +
  1993 +static void gen_spr_403_real (CPUPPCState *env)
  1994 +{
1875 1995 spr_register(env, SPR_403_PBL1, "PBL1",
1876 1996 SPR_NOACCESS, SPR_NOACCESS,
1877 1997 &spr_read_403_pbr, &spr_write_403_pbr,
... ... @@ -1888,6 +2008,15 @@ static void gen_spr_403 (CPUPPCState *env)
1888 2008 SPR_NOACCESS, SPR_NOACCESS,
1889 2009 &spr_read_403_pbr, &spr_write_403_pbr,
1890 2010 0x00000000);
  2011 +}
  2012 +
  2013 +static void gen_spr_403_mmu (CPUPPCState *env)
  2014 +{
  2015 + /* MMU */
  2016 + spr_register(env, SPR_40x_PID, "PID",
  2017 + SPR_NOACCESS, SPR_NOACCESS,
  2018 + &spr_read_generic, &spr_write_generic,
  2019 + 0x00000000);
1891 2020 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 2021 SPR_NOACCESS, SPR_NOACCESS,
1893 2022 &spr_read_generic, &spr_write_generic,
... ... @@ -1895,7 +2024,6 @@ static void gen_spr_403 (CPUPPCState *env)
1895 2024 }
1896 2025  
1897 2026 /* SPR specific to PowerPC compression coprocessor extension */
1898   -#if defined (TODO)
1899 2027 static void gen_spr_compress (CPUPPCState *env)
1900 2028 {
1901 2029 spr_register(env, SPR_401_SKR, "SKR",
... ... @@ -1903,14 +2031,93 @@ static void gen_spr_compress (CPUPPCState *env)
1903 2031 &spr_read_generic, &spr_write_generic,
1904 2032 0x00000000);
1905 2033 }
  2034 +
  2035 +#if defined (TARGET_PPC64)
  2036 +#if defined (TODO)
  2037 +/* SPR specific to PowerPC 620 */
  2038 +static void gen_spr_620 (CPUPPCState *env)
  2039 +{
  2040 + spr_register(env, SPR_620_PMR0, "PMR0",
  2041 + SPR_NOACCESS, SPR_NOACCESS,
  2042 + &spr_read_generic, &spr_write_generic,
  2043 + 0x00000000);
  2044 + spr_register(env, SPR_620_PMR1, "PMR1",
  2045 + SPR_NOACCESS, SPR_NOACCESS,
  2046 + &spr_read_generic, &spr_write_generic,
  2047 + 0x00000000);
  2048 + spr_register(env, SPR_620_PMR2, "PMR2",
  2049 + SPR_NOACCESS, SPR_NOACCESS,
  2050 + &spr_read_generic, &spr_write_generic,
  2051 + 0x00000000);
  2052 + spr_register(env, SPR_620_PMR3, "PMR3",
  2053 + SPR_NOACCESS, SPR_NOACCESS,
  2054 + &spr_read_generic, &spr_write_generic,
  2055 + 0x00000000);
  2056 + spr_register(env, SPR_620_PMR4, "PMR4",
  2057 + SPR_NOACCESS, SPR_NOACCESS,
  2058 + &spr_read_generic, &spr_write_generic,
  2059 + 0x00000000);
  2060 + spr_register(env, SPR_620_PMR5, "PMR5",
  2061 + SPR_NOACCESS, SPR_NOACCESS,
  2062 + &spr_read_generic, &spr_write_generic,
  2063 + 0x00000000);
  2064 + spr_register(env, SPR_620_PMR6, "PMR6",
  2065 + SPR_NOACCESS, SPR_NOACCESS,
  2066 + &spr_read_generic, &spr_write_generic,
  2067 + 0x00000000);
  2068 + spr_register(env, SPR_620_PMR7, "PMR7",
  2069 + SPR_NOACCESS, SPR_NOACCESS,
  2070 + &spr_read_generic, &spr_write_generic,
  2071 + 0x00000000);
  2072 + spr_register(env, SPR_620_PMR8, "PMR8",
  2073 + SPR_NOACCESS, SPR_NOACCESS,
  2074 + &spr_read_generic, &spr_write_generic,
  2075 + 0x00000000);
  2076 + spr_register(env, SPR_620_PMR9, "PMR9",
  2077 + SPR_NOACCESS, SPR_NOACCESS,
  2078 + &spr_read_generic, &spr_write_generic,
  2079 + 0x00000000);
  2080 + spr_register(env, SPR_620_PMRA, "PMR10",
  2081 + SPR_NOACCESS, SPR_NOACCESS,
  2082 + &spr_read_generic, &spr_write_generic,
  2083 + 0x00000000);
  2084 + spr_register(env, SPR_620_PMRB, "PMR11",
  2085 + SPR_NOACCESS, SPR_NOACCESS,
  2086 + &spr_read_generic, &spr_write_generic,
  2087 + 0x00000000);
  2088 + spr_register(env, SPR_620_PMRC, "PMR12",
  2089 + SPR_NOACCESS, SPR_NOACCESS,
  2090 + &spr_read_generic, &spr_write_generic,
  2091 + 0x00000000);
  2092 + spr_register(env, SPR_620_PMRD, "PMR13",
  2093 + SPR_NOACCESS, SPR_NOACCESS,
  2094 + &spr_read_generic, &spr_write_generic,
  2095 + 0x00000000);
  2096 + spr_register(env, SPR_620_PMRE, "PMR14",
  2097 + SPR_NOACCESS, SPR_NOACCESS,
  2098 + &spr_read_generic, &spr_write_generic,
  2099 + 0x00000000);
  2100 + spr_register(env, SPR_620_PMRF, "PMR15",
  2101 + SPR_NOACCESS, SPR_NOACCESS,
  2102 + &spr_read_generic, &spr_write_generic,
  2103 + 0x00000000);
  2104 + spr_register(env, SPR_620_HID8, "HID8",
  2105 + SPR_NOACCESS, SPR_NOACCESS,
  2106 + &spr_read_generic, &spr_write_generic,
  2107 + 0x00000000);
  2108 + spr_register(env, SPR_620_HID9, "HID9",
  2109 + SPR_NOACCESS, SPR_NOACCESS,
  2110 + &spr_read_generic, &spr_write_generic,
  2111 + 0x00000000);
  2112 +}
1906 2113 #endif
  2114 +#endif /* defined (TARGET_PPC64) */
1907 2115  
1908 2116 // XXX: TODO
1909 2117 /*
1910 2118 * AMR => SPR 29 (Power 2.04)
1911 2119 * CTRL => SPR 136 (Power 2.04)
1912 2120 * CTRL => SPR 152 (Power 2.04)
1913   - * VRSAVE => SPR 256 (Altivec)
1914 2121 * SCOMC => SPR 276 (64 bits ?)
1915 2122 * SCOMD => SPR 277 (64 bits ?)
1916 2123 * ASR => SPR 280 (64 bits)
... ... @@ -1942,2397 +2149,3341 @@ static void gen_spr_compress (CPUPPCState *env)
1942 2149 * ... and more (thermal management, performance counters, ...)
1943 2150 */
1944 2151  
1945   -static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1946   -{
1947   - env->reserve = -1;
1948   - /* Default MMU definitions */
1949   - env->nb_BATs = -1;
1950   - env->nb_tlb = 0;
1951   - env->nb_ways = 0;
1952   - /* XXX: missing:
1953   - * 32 bits PowerPC:
1954   - * - MPC5xx(x)
1955   - * - MPC8xx(x)
1956   - * - RCPU (same as MPC5xx ?)
1957   - */
1958   - spr_register(env, SPR_PVR, "PVR",
1959   - SPR_NOACCESS, SPR_NOACCESS,
1960   - &spr_read_generic, SPR_NOACCESS,
1961   - def->pvr);
1962   - printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1963   - def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1964   - switch (def->pvr) {
1965   - /* Embedded PowerPC from IBM */
1966   - case CPU_PPC_401A1: /* 401 A1 family */
1967   - case CPU_PPC_401B2: /* 401 B2 family */
1968   -#if 0
1969   - case CPU_PPC_401B3: /* 401 B3 family */
1970   -#endif
1971   - case CPU_PPC_401C2: /* 401 C2 family */
1972   - case CPU_PPC_401D2: /* 401 D2 family */
1973   - case CPU_PPC_401E2: /* 401 E2 family */
1974   - case CPU_PPC_401F2: /* 401 F2 family */
1975   - case CPU_PPC_401G2: /* 401 G2 family */
1976   - case CPU_PPC_IOP480: /* IOP 480 family */
1977   - case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1978   - gen_spr_generic(env);
1979   - gen_spr_40x(env);
1980   - gen_spr_401_403(env);
1981   - gen_spr_401(env);
1982   -#if defined (TODO)
1983   - /* XXX: optional ? */
1984   - gen_spr_compress(env);
1985   -#endif
1986   - env->nb_BATs = 0;
1987   - env->nb_tlb = 64;
1988   - env->nb_ways = 1;
1989   - env->id_tlbs = 0;
1990   - /* XXX: TODO: allocate internal IRQ controller */
1991   - break;
1992   -
1993   - case CPU_PPC_403GA: /* 403 GA family */
1994   - case CPU_PPC_403GB: /* 403 GB family */
1995   - case CPU_PPC_403GC: /* 403 GC family */
1996   - case CPU_PPC_403GCX: /* 403 GCX family */
1997   - gen_spr_generic(env);
1998   - gen_spr_40x(env);
1999   - gen_spr_401_403(env);
2000   - gen_spr_403(env);
2001   - env->nb_BATs = 0;
2002   - env->nb_tlb = 64;
2003   - env->nb_ways = 1;
2004   - env->id_tlbs = 0;
2005   - /* XXX: TODO: allocate internal IRQ controller */
2006   - break;
2007   -
2008   - case CPU_PPC_405CR: /* 405 GP/CR family */
2009   - case CPU_PPC_405EP: /* 405 EP family */
2010   - case CPU_PPC_405GPR: /* 405 GPR family */
2011   - case CPU_PPC_405D2: /* 405 D2 family */
2012   - case CPU_PPC_405D4: /* 405 D4 family */
2013   - gen_spr_generic(env);
2014   - /* Time base */
2015   - gen_tbl(env);
2016   - gen_spr_40x(env);
2017   - gen_spr_405(env);
2018   - env->nb_BATs = 0;
2019   - env->nb_tlb = 64;
2020   - env->nb_ways = 1;
2021   - env->id_tlbs = 0;
2022   - /* Allocate hardware IRQ controller */
2023   - ppc405_irq_init(env);
2024   - break;
  2152 +/*****************************************************************************/
  2153 +/* PowerPC implementations definitions */
2025 2154  
2026   - case CPU_PPC_NPE405H: /* NPe405 H family */
2027   - case CPU_PPC_NPE405H2:
2028   - case CPU_PPC_NPE405L: /* Npe405 L family */
2029   - gen_spr_generic(env);
2030   - /* Time base */
2031   - gen_tbl(env);
2032   - gen_spr_40x(env);
2033   - gen_spr_405(env);
2034   - env->nb_BATs = 0;
2035   - env->nb_tlb = 64;
2036   - env->nb_ways = 1;
2037   - env->id_tlbs = 0;
2038   - /* Allocate hardware IRQ controller */
2039   - ppc405_irq_init(env);
2040   - break;
  2155 +/* PowerPC 40x instruction set */
  2156 +#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2041 2157  
2042   -#if defined (TODO)
2043   - case CPU_PPC_STB01000:
2044   -#endif
2045   -#if defined (TODO)
2046   - case CPU_PPC_STB01010:
2047   -#endif
2048   -#if defined (TODO)
2049   - case CPU_PPC_STB0210:
2050   -#endif
2051   - case CPU_PPC_STB03: /* STB03 family */
2052   -#if defined (TODO)
2053   - case CPU_PPC_STB043: /* STB043 family */
2054   -#endif
2055   -#if defined (TODO)
2056   - case CPU_PPC_STB045: /* STB045 family */
2057   -#endif
2058   - case CPU_PPC_STB25: /* STB25 family */
2059   -#if defined (TODO)
2060   - case CPU_PPC_STB130: /* STB130 family */
2061   -#endif
2062   - gen_spr_generic(env);
2063   - /* Time base */
2064   - gen_tbl(env);
2065   - gen_spr_40x(env);
2066   - gen_spr_405(env);
2067   - env->nb_BATs = 0;
2068   - env->nb_tlb = 64;
2069   - env->nb_ways = 1;
2070   - env->id_tlbs = 0;
2071   - /* Allocate hardware IRQ controller */
2072   - ppc405_irq_init(env);
2073   - break;
  2158 +/* PowerPC 401 */
  2159 +#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
  2160 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2161 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2162 +#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
  2163 +#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
  2164 +#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
  2165 +#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2074 2166  
2075   - case CPU_PPC_440EP: /* 440 EP family */
2076   - case CPU_PPC_440GP: /* 440 GP family */
2077   - case CPU_PPC_440GX: /* 440 GX family */
2078   - case CPU_PPC_440GXc: /* 440 GXc family */
2079   - case CPU_PPC_440GXf: /* 440 GXf family */
2080   - case CPU_PPC_440SP: /* 440 SP family */
2081   - case CPU_PPC_440SP2:
2082   - case CPU_PPC_440SPE: /* 440 SPE family */
2083   - gen_spr_generic(env);
2084   - /* Time base */
2085   - gen_tbl(env);
2086   - gen_spr_BookE(env);
2087   - gen_spr_440(env);
2088   - env->nb_BATs = 0;
2089   - env->nb_tlb = 64;
2090   - env->nb_ways = 1;
2091   - env->id_tlbs = 0;
2092   - /* XXX: TODO: allocate internal IRQ controller */
2093   - break;
  2167 +static void init_proc_401 (CPUPPCState *env)
  2168 +{
  2169 + gen_spr_40x(env);
  2170 + gen_spr_401_403(env);
  2171 + gen_spr_401(env);
  2172 + /* Bus access control */
  2173 + spr_register(env, SPR_40x_SGR, "SGR",
  2174 + SPR_NOACCESS, SPR_NOACCESS,
  2175 + &spr_read_generic, &spr_write_generic,
  2176 + 0xFFFFFFFF);
  2177 + /* XXX : not implemented */
  2178 + spr_register(env, SPR_40x_DCWR, "DCWR",
  2179 + SPR_NOACCESS, SPR_NOACCESS,
  2180 + &spr_read_generic, &spr_write_generic,
  2181 + 0x00000000);
  2182 + /* XXX: TODO: allocate internal IRQ controller */
  2183 +}
2094 2184  
2095   - /* Embedded PowerPC from Freescale */
2096   -#if defined (TODO)
2097   - case CPU_PPC_5xx:
2098   - break;
2099   -#endif
2100   -#if defined (TODO)
2101   - case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
2102   - break;
2103   -#endif
2104   -#if defined (TODO)
2105   - case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
2106   - case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
2107   - break;
2108   -#endif
2109   -#if defined (TODO)
2110   - case CPU_PPC_827x: /* MPC 827x / 828x */
2111   - break;
2112   -#endif
2113   -
2114   - /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2115   - case CPU_PPC_e500v110:
2116   - case CPU_PPC_e500v120:
2117   - case CPU_PPC_e500v210:
2118   - case CPU_PPC_e500v220:
2119   - gen_spr_generic(env);
2120   - /* Time base */
2121   - gen_tbl(env);
2122   - gen_spr_BookE(env);
2123   - gen_spr_BookE_FSL(env);
2124   - env->nb_BATs = 0;
2125   - env->nb_tlb = 64;
2126   - env->nb_ways = 1;
2127   - env->id_tlbs = 0;
2128   - /* XXX: TODO: allocate internal IRQ controller */
2129   - break;
2130   -
2131   -#if defined (TODO)
2132   - case CPU_PPC_e600:
2133   - break;
2134   -#endif
2135   -
2136   - /* 32 bits PowerPC */
2137   - case CPU_PPC_601: /* PowerPC 601 */
2138   - gen_spr_generic(env);
2139   - gen_spr_ne_601(env);
2140   - gen_spr_601(env);
2141   - /* Hardware implementation registers */
2142   - /* XXX : not implemented */
2143   - spr_register(env, SPR_HID0, "HID0",
2144   - SPR_NOACCESS, SPR_NOACCESS,
2145   - &spr_read_generic, &spr_write_generic,
2146   - 0x00000000);
2147   - /* XXX : not implemented */
2148   - spr_register(env, SPR_HID1, "HID1",
2149   - SPR_NOACCESS, SPR_NOACCESS,
2150   - &spr_read_generic, &spr_write_generic,
2151   - 0x00000000);
2152   - /* XXX : not implemented */
2153   - spr_register(env, SPR_601_HID2, "HID2",
2154   - SPR_NOACCESS, SPR_NOACCESS,
2155   - &spr_read_generic, &spr_write_generic,
2156   - 0x00000000);
2157   - /* XXX : not implemented */
2158   - spr_register(env, SPR_601_HID5, "HID5",
2159   - SPR_NOACCESS, SPR_NOACCESS,
2160   - &spr_read_generic, &spr_write_generic,
2161   - 0x00000000);
2162   - /* XXX : not implemented */
2163   -#if 0 /* ? */
2164   - spr_register(env, SPR_601_HID15, "HID15",
2165   - SPR_NOACCESS, SPR_NOACCESS,
2166   - &spr_read_generic, &spr_write_generic,
2167   - 0x00000000);
2168   -#endif
2169   - env->nb_tlb = 64;
2170   - env->nb_ways = 2;
2171   - env->id_tlbs = 0;
2172   - env->id_tlbs = 0;
2173   - /* XXX: TODO: allocate internal IRQ controller */
2174   - break;
2175   -
2176   - case CPU_PPC_602: /* PowerPC 602 */
2177   - gen_spr_generic(env);
2178   - gen_spr_ne_601(env);
2179   - /* Memory management */
2180   - gen_low_BATs(env);
2181   - /* Time base */
2182   - gen_tbl(env);
2183   - gen_6xx_7xx_soft_tlb(env, 64, 2);
2184   - gen_spr_602(env);
2185   - /* hardware implementation registers */
2186   - /* XXX : not implemented */
2187   - spr_register(env, SPR_HID0, "HID0",
2188   - SPR_NOACCESS, SPR_NOACCESS,
2189   - &spr_read_generic, &spr_write_generic,
2190   - 0x00000000);
2191   - /* XXX : not implemented */
2192   - spr_register(env, SPR_HID1, "HID1",
2193   - SPR_NOACCESS, SPR_NOACCESS,
2194   - &spr_read_generic, &spr_write_generic,
2195   - 0x00000000);
2196   - /* Allocate hardware IRQ controller */
2197   - ppc6xx_irq_init(env);
2198   - break;
2199   -
2200   - case CPU_PPC_603: /* PowerPC 603 */
2201   - case CPU_PPC_603E: /* PowerPC 603e */
2202   - case CPU_PPC_603E7v:
2203   - case CPU_PPC_603E7v2:
2204   - case CPU_PPC_603P: /* PowerPC 603p */
2205   - case CPU_PPC_603R: /* PowerPC 603r */
2206   - gen_spr_generic(env);
2207   - gen_spr_ne_601(env);
2208   - /* Memory management */
2209   - gen_low_BATs(env);
2210   - /* Time base */
2211   - gen_tbl(env);
2212   - gen_6xx_7xx_soft_tlb(env, 64, 2);
2213   - gen_spr_603(env);
2214   - /* hardware implementation registers */
2215   - /* XXX : not implemented */
2216   - spr_register(env, SPR_HID0, "HID0",
2217   - SPR_NOACCESS, SPR_NOACCESS,
2218   - &spr_read_generic, &spr_write_generic,
2219   - 0x00000000);
2220   - /* XXX : not implemented */
2221   - spr_register(env, SPR_HID1, "HID1",
2222   - SPR_NOACCESS, SPR_NOACCESS,
2223   - &spr_read_generic, &spr_write_generic,
2224   - 0x00000000);
2225   - /* Allocate hardware IRQ controller */
2226   - ppc6xx_irq_init(env);
2227   - break;
2228   -
2229   - case CPU_PPC_G2: /* PowerPC G2 family */
2230   - case CPU_PPC_G2H4:
2231   - case CPU_PPC_G2gp:
2232   - case CPU_PPC_G2ls:
2233   - case CPU_PPC_G2LE: /* PowerPC G2LE family */
2234   - case CPU_PPC_G2LEgp:
2235   - case CPU_PPC_G2LEls:
2236   - gen_spr_generic(env);
2237   - gen_spr_ne_601(env);
2238   - /* Memory management */
2239   - gen_low_BATs(env);
2240   - /* Time base */
2241   - gen_tbl(env);
2242   - /* Memory management */
2243   - gen_high_BATs(env);
2244   - gen_6xx_7xx_soft_tlb(env, 64, 2);
2245   - gen_spr_G2_755(env);
2246   - gen_spr_G2(env);
2247   - /* Hardware implementation register */
2248   - /* XXX : not implemented */
2249   - spr_register(env, SPR_HID0, "HID0",
2250   - SPR_NOACCESS, SPR_NOACCESS,
2251   - &spr_read_generic, &spr_write_generic,
2252   - 0x00000000);
2253   - /* XXX : not implemented */
2254   - spr_register(env, SPR_HID1, "HID1",
2255   - SPR_NOACCESS, SPR_NOACCESS,
2256   - &spr_read_generic, &spr_write_generic,
2257   - 0x00000000);
2258   - /* XXX : not implemented */
2259   - spr_register(env, SPR_HID2, "HID2",
2260   - SPR_NOACCESS, SPR_NOACCESS,
2261   - &spr_read_generic, &spr_write_generic,
2262   - 0x00000000);
2263   - /* Allocate hardware IRQ controller */
2264   - ppc6xx_irq_init(env);
2265   - break;
2266   -
2267   - case CPU_PPC_604: /* PowerPC 604 */
2268   - case CPU_PPC_604E: /* PowerPC 604e */
2269   - case CPU_PPC_604R: /* PowerPC 604r */
2270   - gen_spr_generic(env);
2271   - gen_spr_ne_601(env);
2272   - /* Memory management */
2273   - gen_low_BATs(env);
2274   - /* Time base */
2275   - gen_tbl(env);
2276   - gen_spr_604(env);
2277   - /* Hardware implementation registers */
2278   - /* XXX : not implemented */
2279   - spr_register(env, SPR_HID0, "HID0",
2280   - SPR_NOACCESS, SPR_NOACCESS,
2281   - &spr_read_generic, &spr_write_generic,
2282   - 0x00000000);
2283   - /* XXX : not implemented */
2284   - spr_register(env, SPR_HID1, "HID1",
2285   - SPR_NOACCESS, SPR_NOACCESS,
2286   - &spr_read_generic, &spr_write_generic,
2287   - 0x00000000);
2288   - /* Allocate hardware IRQ controller */
2289   - ppc6xx_irq_init(env);
2290   - break;
2291   -
2292   - case CPU_PPC_74x: /* PowerPC 740 / 750 */
2293   - case CPU_PPC_740E:
2294   - case CPU_PPC_750E:
2295   - case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2296   - case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2297   - case CPU_PPC_750CXE22:
2298   - case CPU_PPC_750CXE23:
2299   - case CPU_PPC_750CXE24:
2300   - case CPU_PPC_750CXE24b:
2301   - case CPU_PPC_750CXE31:
2302   - case CPU_PPC_750CXE31b:
2303   - case CPU_PPC_750CXR:
2304   - gen_spr_generic(env);
2305   - gen_spr_ne_601(env);
2306   - /* Memory management */
2307   - gen_low_BATs(env);
2308   - /* Time base */
2309   - gen_tbl(env);
2310   - gen_spr_7xx(env);
2311   - /* Hardware implementation registers */
2312   - /* XXX : not implemented */
2313   - spr_register(env, SPR_HID0, "HID0",
2314   - SPR_NOACCESS, SPR_NOACCESS,
2315   - &spr_read_generic, &spr_write_generic,
2316   - 0x00000000);
2317   - /* XXX : not implemented */
2318   - spr_register(env, SPR_HID1, "HID1",
2319   - SPR_NOACCESS, SPR_NOACCESS,
2320   - &spr_read_generic, &spr_write_generic,
2321   - 0x00000000);
2322   - /* Allocate hardware IRQ controller */
2323   - ppc6xx_irq_init(env);
2324   - break;
2325   -
2326   - case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2327   - case CPU_PPC_750FX20:
2328   - case CPU_PPC_750FX21:
2329   - case CPU_PPC_750FX22:
2330   - case CPU_PPC_750FX23:
2331   - case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2332   - case CPU_PPC_750GX11:
2333   - case CPU_PPC_750GX12:
2334   - gen_spr_generic(env);
2335   - gen_spr_ne_601(env);
2336   - /* Memory management */
2337   - gen_low_BATs(env);
2338   - /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2339   - gen_high_BATs(env);
2340   - /* Time base */
2341   - gen_tbl(env);
2342   - gen_spr_7xx(env);
2343   - /* Hardware implementation registers */
2344   - /* XXX : not implemented */
2345   - spr_register(env, SPR_HID0, "HID0",
2346   - SPR_NOACCESS, SPR_NOACCESS,
2347   - &spr_read_generic, &spr_write_generic,
2348   - 0x00000000);
2349   - /* XXX : not implemented */
2350   - spr_register(env, SPR_HID1, "HID1",
2351   - SPR_NOACCESS, SPR_NOACCESS,
2352   - &spr_read_generic, &spr_write_generic,
2353   - 0x00000000);
2354   - /* XXX : not implemented */
2355   - spr_register(env, SPR_750_HID2, "HID2",
2356   - SPR_NOACCESS, SPR_NOACCESS,
2357   - &spr_read_generic, &spr_write_generic,
2358   - 0x00000000);
2359   - /* Allocate hardware IRQ controller */
2360   - ppc6xx_irq_init(env);
2361   - break;
2362   -
2363   - case CPU_PPC_755_10: /* PowerPC 755 */
2364   - case CPU_PPC_755_11:
2365   - case CPU_PPC_755_20:
2366   - case CPU_PPC_755D:
2367   - case CPU_PPC_755E:
2368   - gen_spr_generic(env);
2369   - gen_spr_ne_601(env);
2370   - /* Memory management */
2371   - gen_low_BATs(env);
2372   - /* Time base */
2373   - gen_tbl(env);
2374   - /* Memory management */
2375   - gen_high_BATs(env);
2376   - gen_6xx_7xx_soft_tlb(env, 64, 2);
2377   - gen_spr_G2_755(env);
2378   - /* L2 cache control */
2379   - /* XXX : not implemented */
2380   - spr_register(env, SPR_ICTC, "ICTC",
2381   - SPR_NOACCESS, SPR_NOACCESS,
2382   - &spr_read_generic, &spr_write_generic,
2383   - 0x00000000);
2384   - /* XXX : not implemented */
2385   - spr_register(env, SPR_L2PM, "L2PM",
2386   - SPR_NOACCESS, SPR_NOACCESS,
2387   - &spr_read_generic, &spr_write_generic,
2388   - 0x00000000);
2389   - /* Hardware implementation registers */
2390   - /* XXX : not implemented */
2391   - spr_register(env, SPR_HID0, "HID0",
2392   - SPR_NOACCESS, SPR_NOACCESS,
2393   - &spr_read_generic, &spr_write_generic,
2394   - 0x00000000);
2395   - /* XXX : not implemented */
2396   - spr_register(env, SPR_HID1, "HID1",
2397   - SPR_NOACCESS, SPR_NOACCESS,
2398   - &spr_read_generic, &spr_write_generic,
2399   - 0x00000000);
2400   - /* XXX : not implemented */
2401   - spr_register(env, SPR_HID2, "HID2",
2402   - SPR_NOACCESS, SPR_NOACCESS,
2403   - &spr_read_generic, &spr_write_generic,
2404   - 0x00000000);
2405   - /* Allocate hardware IRQ controller */
2406   - ppc6xx_irq_init(env);
2407   - break;
2408   -
2409   -#if defined (TODO)
2410   - /* G4 family */
2411   - case CPU_PPC_7400: /* PowerPC 7400 */
2412   - case CPU_PPC_7410C: /* PowerPC 7410 */
2413   - case CPU_PPC_7410D:
2414   - case CPU_PPC_7410E:
2415   - case CPU_PPC_7441: /* PowerPC 7441 */
2416   - case CPU_PPC_7445: /* PowerPC 7445 */
2417   - case CPU_PPC_7447: /* PowerPC 7447 */
2418   - case CPU_PPC_7447A: /* PowerPC 7447A */
2419   - case CPU_PPC_7448: /* PowerPC 7448 */
2420   - case CPU_PPC_7450: /* PowerPC 7450 */
2421   - case CPU_PPC_7450b:
2422   - case CPU_PPC_7451: /* PowerPC 7451 */
2423   - case CPU_PPC_7451G:
2424   - case CPU_PPC_7455: /* PowerPC 7455 */
2425   - case CPU_PPC_7455F:
2426   - case CPU_PPC_7455G:
2427   - case CPU_PPC_7457: /* PowerPC 7457 */
2428   - case CPU_PPC_7457C:
2429   - case CPU_PPC_7457A: /* PowerPC 7457A */
2430   - break;
2431   -#endif
2432   -
2433   - /* 64 bits PowerPC */
2434   -#if defined (TARGET_PPC64)
2435   -#if defined (TODO)
2436   - case CPU_PPC_620: /* PowerPC 620 */
2437   - case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2438   - case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2439   - case CPU_PPC_POWER4: /* Power 4 */
2440   - case CPU_PPC_POWER4P: /* Power 4+ */
2441   - case CPU_PPC_POWER5: /* Power 5 */
2442   - case CPU_PPC_POWER5P: /* Power 5+ */
2443   -#endif
2444   - break;
2445   -
2446   - case CPU_PPC_970: /* PowerPC 970 */
2447   - case CPU_PPC_970FX10: /* PowerPC 970 FX */
2448   - case CPU_PPC_970FX20:
2449   - case CPU_PPC_970FX21:
2450   - case CPU_PPC_970FX30:
2451   - case CPU_PPC_970FX31:
2452   - case CPU_PPC_970MP10: /* PowerPC 970 MP */
2453   - case CPU_PPC_970MP11:
2454   - gen_spr_generic(env);
2455   - gen_spr_ne_601(env);
2456   - /* XXX: not correct */
2457   - gen_low_BATs(env);
2458   - /* Time base */
2459   - gen_tbl(env);
2460   - gen_spr_7xx(env);
2461   - /* Hardware implementation registers */
2462   - /* XXX : not implemented */
2463   - spr_register(env, SPR_HID0, "HID0",
2464   - SPR_NOACCESS, SPR_NOACCESS,
2465   - &spr_read_generic, &spr_write_generic,
2466   - 0x00000000);
2467   - /* XXX : not implemented */
2468   - spr_register(env, SPR_HID1, "HID1",
2469   - SPR_NOACCESS, SPR_NOACCESS,
2470   - &spr_read_generic, &spr_write_generic,
2471   - 0x00000000);
2472   - /* XXX : not implemented */
2473   - spr_register(env, SPR_750_HID2, "HID2",
2474   - SPR_NOACCESS, SPR_NOACCESS,
2475   - &spr_read_generic, &spr_write_generic,
2476   - 0x00000000);
2477   - /* Allocate hardware IRQ controller */
2478   - ppc970_irq_init(env);
2479   - break;
2480   -
2481   -#if defined (TODO)
2482   - case CPU_PPC_CELL10: /* Cell family */
2483   - case CPU_PPC_CELL20:
2484   - case CPU_PPC_CELL30:
2485   - case CPU_PPC_CELL31:
2486   -#endif
2487   - break;
2488   -
2489   -#if defined (TODO)
2490   - case CPU_PPC_RS64: /* Apache (RS64/A35) */
2491   - case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2492   - case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2493   - case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
2494   -#endif
2495   - break;
2496   -#endif /* defined (TARGET_PPC64) */
2497   -
2498   -#if defined (TODO)
2499   - /* POWER */
2500   - case CPU_POWER: /* POWER */
2501   - case CPU_POWER2: /* POWER2 */
2502   - break;
2503   -#endif
2504   -
2505   - default:
2506   - gen_spr_generic(env);
2507   - /* XXX: TODO: allocate internal IRQ controller */
2508   - break;
2509   - }
2510   - if (env->nb_BATs == -1)
2511   - env->nb_BATs = 4;
2512   - /* Allocate TLBs buffer when needed */
2513   - if (env->nb_tlb != 0) {
2514   - int nb_tlb = env->nb_tlb;
2515   - if (env->id_tlbs != 0)
2516   - nb_tlb *= 2;
2517   - env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2518   - /* Pre-compute some useful values */
2519   - env->tlb_per_way = env->nb_tlb / env->nb_ways;
2520   - }
  2185 +/* PowerPC 401x2 */
  2186 +#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
  2187 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2188 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2189 + PPC_CACHE_DCBA | PPC_MFTB | \
  2190 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2191 +#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
  2192 +#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
  2193 +#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
  2194 +#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
  2195 +
  2196 +static void init_proc_401x2 (CPUPPCState *env)
  2197 +{
  2198 + gen_spr_40x(env);
  2199 + gen_spr_401_403(env);
  2200 + gen_spr_401x2(env);
  2201 + gen_spr_compress(env);
  2202 + /* Bus access control */
  2203 + spr_register(env, SPR_40x_SGR, "SGR",
  2204 + SPR_NOACCESS, SPR_NOACCESS,
  2205 + &spr_read_generic, &spr_write_generic,
  2206 + 0xFFFFFFFF);
  2207 + /* XXX : not implemented */
  2208 + spr_register(env, SPR_40x_DCWR, "DCWR",
  2209 + SPR_NOACCESS, SPR_NOACCESS,
  2210 + &spr_read_generic, &spr_write_generic,
  2211 + 0x00000000);
  2212 + /* Memory management */
  2213 + env->nb_tlb = 64;
  2214 + env->nb_ways = 1;
  2215 + env->id_tlbs = 0;
  2216 + /* XXX: TODO: allocate internal IRQ controller */
2521 2217 }
2522 2218  
2523   -#if defined(PPC_DUMP_CPU)
2524   -static void dump_sprs (CPUPPCState *env)
  2219 +/* PowerPC 401x3 */
  2220 +#if defined(TODO)
  2221 +#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
  2222 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2223 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2224 + PPC_CACHE_DCBA | PPC_MFTB | \
  2225 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2226 +#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
  2227 +#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
  2228 +#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
  2229 +#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
  2230 +
  2231 +static void init_proc_401x2 (CPUPPCState *env)
2525 2232 {
2526   - ppc_spr_t *spr;
2527   - uint32_t pvr = env->spr[SPR_PVR];
2528   - uint32_t sr, sw, ur, uw;
2529   - int i, j, n;
2530   -
2531   - printf("* SPRs for PVR=%08x\n", pvr);
2532   - for (i = 0; i < 32; i++) {
2533   - for (j = 0; j < 32; j++) {
2534   - n = (i << 5) | j;
2535   - spr = &env->spr_cb[n];
2536   -#if !defined(CONFIG_USER_ONLY)
2537   - sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2538   - sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2539   -#else
2540   - sw = 0;
2541   - sr = 0;
2542   -#endif
2543   - uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2544   - ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2545   - if (sw || sr || uw || ur) {
2546   - printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
2547   - (i << 5) | j, (i << 5) | j, spr->name,
2548   - sw ? 'w' : '-', sr ? 'r' : '-',
2549   - uw ? 'w' : '-', ur ? 'r' : '-');
2550   - }
2551   - }
2552   - }
2553   - fflush(stdout);
2554   - fflush(stderr);
2555 2233 }
2556   -#endif
2557   -
2558   -/*****************************************************************************/
2559   -#include <stdlib.h>
2560   -#include <string.h>
2561   -
2562   -int fflush (FILE *stream);
2563   -
2564   -/* Opcode types */
2565   -enum {
2566   - PPC_DIRECT = 0, /* Opcode routine */
2567   - PPC_INDIRECT = 1, /* Indirect opcode table */
2568   -};
2569   -
2570   -static inline int is_indirect_opcode (void *handler)
  2234 +#endif /* TODO */
  2235 +
  2236 +/* IOP480 */
  2237 +#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
  2238 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2239 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2240 + PPC_CACHE_DCBA | \
  2241 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2242 +#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
  2243 +#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
  2244 +#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
  2245 +#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
  2246 +
  2247 +static void init_proc_IOP480 (CPUPPCState *env)
2571 2248 {
2572   - return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
  2249 + gen_spr_40x(env);
  2250 + gen_spr_401_403(env);
  2251 + gen_spr_401x2(env);
  2252 + gen_spr_compress(env);
  2253 + /* Bus access control */
  2254 + spr_register(env, SPR_40x_SGR, "SGR",
  2255 + SPR_NOACCESS, SPR_NOACCESS,
  2256 + &spr_read_generic, &spr_write_generic,
  2257 + 0xFFFFFFFF);
  2258 + /* XXX : not implemented */
  2259 + spr_register(env, SPR_40x_DCWR, "DCWR",
  2260 + SPR_NOACCESS, SPR_NOACCESS,
  2261 + &spr_read_generic, &spr_write_generic,
  2262 + 0x00000000);
  2263 + /* Memory management */
  2264 + env->nb_tlb = 64;
  2265 + env->nb_ways = 1;
  2266 + env->id_tlbs = 0;
  2267 + /* XXX: TODO: allocate internal IRQ controller */
2573 2268 }
2574 2269  
2575   -static inline opc_handler_t **ind_table(void *handler)
  2270 +/* PowerPC 403 */
  2271 +#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
  2272 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2273 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2274 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2275 +#define POWERPC_MSRM_403 (0x000000000007D00DULL)
  2276 +#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
  2277 +#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
  2278 +#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
  2279 +
  2280 +static void init_proc_403 (CPUPPCState *env)
2576 2281 {
2577   - return (opc_handler_t **)((unsigned long)handler & ~3);
  2282 + gen_spr_40x(env);
  2283 + gen_spr_401_403(env);
  2284 + gen_spr_403(env);
  2285 + gen_spr_403_real(env);
  2286 + /* XXX: TODO: allocate internal IRQ controller */
2578 2287 }
2579 2288  
2580   -/* Instruction table creation */
2581   -/* Opcodes tables creation */
2582   -static void fill_new_table (opc_handler_t **table, int len)
  2289 +/* PowerPC 403 GCX */
  2290 +#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
  2291 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2292 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2293 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2294 +#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
  2295 +#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
  2296 +#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
  2297 +#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
  2298 +
  2299 +static void init_proc_403GCX (CPUPPCState *env)
2583 2300 {
2584   - int i;
2585   -
2586   - for (i = 0; i < len; i++)
2587   - table[i] = &invalid_handler;
  2301 + gen_spr_40x(env);
  2302 + gen_spr_401_403(env);
  2303 + gen_spr_403(env);
  2304 + gen_spr_403_real(env);
  2305 + gen_spr_403_mmu(env);
  2306 + /* Bus access control */
  2307 + spr_register(env, SPR_40x_SGR, "SGR",
  2308 + SPR_NOACCESS, SPR_NOACCESS,
  2309 + &spr_read_generic, &spr_write_generic,
  2310 + 0xFFFFFFFF);
  2311 + /* XXX : not implemented */
  2312 + spr_register(env, SPR_40x_DCWR, "DCWR",
  2313 + SPR_NOACCESS, SPR_NOACCESS,
  2314 + &spr_read_generic, &spr_write_generic,
  2315 + 0x00000000);
  2316 + /* Memory management */
  2317 + env->nb_tlb = 64;
  2318 + env->nb_ways = 1;
  2319 + env->id_tlbs = 0;
  2320 + /* XXX: TODO: allocate internal IRQ controller */
2588 2321 }
2589 2322  
2590   -static int create_new_table (opc_handler_t **table, unsigned char idx)
  2323 +/* PowerPC 405 */
  2324 +#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
  2325 + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
  2326 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  2327 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
  2328 + PPC_405_MAC)
  2329 +#define POWERPC_MSRM_405 (0x000000000006E630ULL)
  2330 +#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
  2331 +#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
  2332 +#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
  2333 +
  2334 +static void init_proc_405 (CPUPPCState *env)
2591 2335 {
2592   - opc_handler_t **tmp;
2593   -
2594   - tmp = malloc(0x20 * sizeof(opc_handler_t));
2595   - if (tmp == NULL)
2596   - return -1;
2597   - fill_new_table(tmp, 0x20);
2598   - table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2599   -
2600   - return 0;
  2336 + /* Time base */
  2337 + gen_tbl(env);
  2338 + gen_spr_40x(env);
  2339 + gen_spr_405(env);
  2340 + /* Bus access control */
  2341 + spr_register(env, SPR_40x_SGR, "SGR",
  2342 + SPR_NOACCESS, SPR_NOACCESS,
  2343 + &spr_read_generic, &spr_write_generic,
  2344 + 0xFFFFFFFF);
  2345 + /* XXX : not implemented */
  2346 + spr_register(env, SPR_40x_DCWR, "DCWR",
  2347 + SPR_NOACCESS, SPR_NOACCESS,
  2348 + &spr_read_generic, &spr_write_generic,
  2349 + 0x00000000);
  2350 + /* Memory management */
  2351 + env->nb_tlb = 64;
  2352 + env->nb_ways = 1;
  2353 + env->id_tlbs = 0;
  2354 + /* Allocate hardware IRQ controller */
  2355 + ppc405_irq_init(env);
2601 2356 }
2602 2357  
2603   -static int insert_in_table (opc_handler_t **table, unsigned char idx,
2604   - opc_handler_t *handler)
  2358 +/* PowerPC 440 EP */
  2359 +#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
  2360 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2361 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  2362 + PPC_440_SPEC | PPC_RFMCI)
  2363 +#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
  2364 +#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
  2365 +#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
  2366 +#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
  2367 +
  2368 +static void init_proc_440EP (CPUPPCState *env)
2605 2369 {
2606   - if (table[idx] != &invalid_handler)
2607   - return -1;
2608   - table[idx] = handler;
2609   -
2610   - return 0;
  2370 + /* Time base */
  2371 + gen_tbl(env);
  2372 + gen_spr_BookE(env);
  2373 + gen_spr_440(env);
  2374 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  2375 + SPR_NOACCESS, SPR_NOACCESS,
  2376 + &spr_read_generic, &spr_write_generic,
  2377 + 0x00000000);
  2378 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  2379 + SPR_NOACCESS, SPR_NOACCESS,
  2380 + &spr_read_generic, &spr_write_generic,
  2381 + 0x00000000);
  2382 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  2383 + SPR_NOACCESS, SPR_NOACCESS,
  2384 + &spr_read_generic, &spr_write_generic,
  2385 + 0x00000000);
  2386 + spr_register(env, SPR_440_CCR1, "CCR1",
  2387 + SPR_NOACCESS, SPR_NOACCESS,
  2388 + &spr_read_generic, &spr_write_generic,
  2389 + 0x00000000);
  2390 + /* Memory management */
  2391 + env->nb_tlb = 64;
  2392 + env->nb_ways = 1;
  2393 + env->id_tlbs = 0;
  2394 + /* XXX: TODO: allocate internal IRQ controller */
2611 2395 }
2612 2396  
2613   -static int register_direct_insn (opc_handler_t **ppc_opcodes,
2614   - unsigned char idx, opc_handler_t *handler)
  2397 +/* PowerPC 440 GP */
  2398 +#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
  2399 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2400 + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
  2401 + PPC_405_MAC | PPC_440_SPEC)
  2402 +#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
  2403 +#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
  2404 +#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
  2405 +#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
  2406 +
  2407 +static void init_proc_440GP (CPUPPCState *env)
2615 2408 {
2616   - if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2617   - printf("*** ERROR: opcode %02x already assigned in main "
2618   - "opcode table\n", idx);
2619   - return -1;
2620   - }
2621   -
2622   - return 0;
  2409 + /* Time base */
  2410 + gen_tbl(env);
  2411 + gen_spr_BookE(env);
  2412 + gen_spr_440(env);
  2413 + /* Memory management */
  2414 + env->nb_tlb = 64;
  2415 + env->nb_ways = 1;
  2416 + env->id_tlbs = 0;
  2417 + /* XXX: TODO: allocate internal IRQ controller */
2623 2418 }
2624 2419  
2625   -static int register_ind_in_table (opc_handler_t **table,
2626   - unsigned char idx1, unsigned char idx2,
2627   - opc_handler_t *handler)
  2420 +/* PowerPC 440x4 */
  2421 +#if defined(TODO)
  2422 +#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
  2423 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2424 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  2425 + PPC_440_SPEC)
  2426 +#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
  2427 +#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
  2428 +#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
  2429 +#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
  2430 +
  2431 +static void init_proc_440x4 (CPUPPCState *env)
2628 2432 {
2629   - if (table[idx1] == &invalid_handler) {
2630   - if (create_new_table(table, idx1) < 0) {
2631   - printf("*** ERROR: unable to create indirect table "
2632   - "idx=%02x\n", idx1);
2633   - return -1;
2634   - }
2635   - } else {
2636   - if (!is_indirect_opcode(table[idx1])) {
2637   - printf("*** ERROR: idx %02x already assigned to a direct "
2638   - "opcode\n", idx1);
2639   - return -1;
2640   - }
2641   - }
2642   - if (handler != NULL &&
2643   - insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2644   - printf("*** ERROR: opcode %02x already assigned in "
2645   - "opcode table %02x\n", idx2, idx1);
2646   - return -1;
2647   - }
2648   -
2649   - return 0;
  2433 + /* Time base */
  2434 + gen_tbl(env);
  2435 + gen_spr_BookE(env);
  2436 + gen_spr_440(env);
  2437 + /* Memory management */
  2438 + env->nb_tlb = 64;
  2439 + env->nb_ways = 1;
  2440 + env->id_tlbs = 0;
  2441 + /* XXX: TODO: allocate internal IRQ controller */
2650 2442 }
2651   -
2652   -static int register_ind_insn (opc_handler_t **ppc_opcodes,
2653   - unsigned char idx1, unsigned char idx2,
2654   - opc_handler_t *handler)
  2443 +#endif /* TODO */
  2444 +
  2445 +/* PowerPC 440x5 */
  2446 +#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
  2447 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2448 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  2449 + PPC_440_SPEC | PPC_RFMCI)
  2450 +#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
  2451 +#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
  2452 +#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
  2453 +#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
  2454 +
  2455 +static void init_proc_440x5 (CPUPPCState *env)
2655 2456 {
2656   - int ret;
2657   -
2658   - ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2659   -
2660   - return ret;
  2457 + /* Time base */
  2458 + gen_tbl(env);
  2459 + gen_spr_BookE(env);
  2460 + gen_spr_440(env);
  2461 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  2462 + SPR_NOACCESS, SPR_NOACCESS,
  2463 + &spr_read_generic, &spr_write_generic,
  2464 + 0x00000000);
  2465 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  2466 + SPR_NOACCESS, SPR_NOACCESS,
  2467 + &spr_read_generic, &spr_write_generic,
  2468 + 0x00000000);
  2469 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  2470 + SPR_NOACCESS, SPR_NOACCESS,
  2471 + &spr_read_generic, &spr_write_generic,
  2472 + 0x00000000);
  2473 + spr_register(env, SPR_440_CCR1, "CCR1",
  2474 + SPR_NOACCESS, SPR_NOACCESS,
  2475 + &spr_read_generic, &spr_write_generic,
  2476 + 0x00000000);
  2477 + /* Memory management */
  2478 + env->nb_tlb = 64;
  2479 + env->nb_ways = 1;
  2480 + env->id_tlbs = 0;
  2481 + /* XXX: TODO: allocate internal IRQ controller */
2661 2482 }
2662 2483  
2663   -static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2664   - unsigned char idx1, unsigned char idx2,
2665   - unsigned char idx3, opc_handler_t *handler)
  2484 +/* PowerPC 460 (guessed) */
  2485 +#if defined(TODO)
  2486 +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
  2487 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2488 + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
  2489 + PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
  2490 +#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
  2491 +#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
  2492 +#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
  2493 +#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
  2494 +
  2495 +static void init_proc_460 (CPUPPCState *env)
2666 2496 {
2667   - if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2668   - printf("*** ERROR: unable to join indirect table idx "
2669   - "[%02x-%02x]\n", idx1, idx2);
2670   - return -1;
2671   - }
2672   - if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2673   - handler) < 0) {
2674   - printf("*** ERROR: unable to insert opcode "
2675   - "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2676   - return -1;
2677   - }
2678   -
2679   - return 0;
2680 2497 }
2681   -
2682   -static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
  2498 +#endif /* TODO */
  2499 +
  2500 +/* PowerPC 460F (guessed) */
  2501 +#if defined(TODO)
  2502 +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
  2503 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  2504 + PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
  2505 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
  2506 + PPC_FLOAT_STFIWX | \
  2507 + PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
  2508 + PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
  2509 +#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
  2510 +#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
  2511 +#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
  2512 +#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
  2513 +
  2514 +static void init_proc_460 (CPUPPCState *env)
2683 2515 {
2684   - if (insn->opc2 != 0xFF) {
2685   - if (insn->opc3 != 0xFF) {
2686   - if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2687   - insn->opc3, &insn->handler) < 0)
2688   - return -1;
2689   - } else {
2690   - if (register_ind_insn(ppc_opcodes, insn->opc1,
2691   - insn->opc2, &insn->handler) < 0)
2692   - return -1;
2693   - }
2694   - } else {
2695   - if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2696   - return -1;
2697   - }
2698   -
2699   - return 0;
  2516 + /* Time base */
  2517 + gen_tbl(env);
  2518 + gen_spr_BookE(env);
  2519 + gen_spr_440(env);
  2520 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  2521 + SPR_NOACCESS, SPR_NOACCESS,
  2522 + &spr_read_generic, &spr_write_generic,
  2523 + 0x00000000);
  2524 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  2525 + SPR_NOACCESS, SPR_NOACCESS,
  2526 + &spr_read_generic, &spr_write_generic,
  2527 + 0x00000000);
  2528 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  2529 + SPR_NOACCESS, SPR_NOACCESS,
  2530 + &spr_read_generic, &spr_write_generic,
  2531 + 0x00000000);
  2532 + spr_register(env, SPR_440_CCR1, "CCR1",
  2533 + SPR_NOACCESS, SPR_NOACCESS,
  2534 + &spr_read_generic, &spr_write_generic,
  2535 + 0x00000000);
  2536 + spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
  2537 + &spr_read_generic, &spr_write_generic,
  2538 + &spr_read_generic, &spr_write_generic,
  2539 + 0x00000000);
  2540 + /* Memory management */
  2541 + env->nb_tlb = 64;
  2542 + env->nb_ways = 1;
  2543 + env->id_tlbs = 0;
  2544 + /* XXX: TODO: allocate internal IRQ controller */
2700 2545 }
2701   -
2702   -static int test_opcode_table (opc_handler_t **table, int len)
  2546 +#endif /* TODO */
  2547 +
  2548 +/* Generic BookE PowerPC */
  2549 +#if defined(TODO)
  2550 +#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
  2551 + PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
  2552 + PPC_CACHE_DCBA | \
  2553 + PPC_FLOAT | PPC_FLOAT_FSQRT | \
  2554 + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
  2555 + PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
  2556 + PPC_BOOKE)
  2557 +#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
  2558 +#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
  2559 +#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
  2560 +#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
  2561 +
  2562 +static void init_proc_BookE (CPUPPCState *env)
2703 2563 {
2704   - int i, count, tmp;
2705   -
2706   - for (i = 0, count = 0; i < len; i++) {
2707   - /* Consistency fixup */
2708   - if (table[i] == NULL)
2709   - table[i] = &invalid_handler;
2710   - if (table[i] != &invalid_handler) {
2711   - if (is_indirect_opcode(table[i])) {
2712   - tmp = test_opcode_table(ind_table(table[i]), 0x20);
2713   - if (tmp == 0) {
2714   - free(table[i]);
2715   - table[i] = &invalid_handler;
2716   - } else {
2717   - count++;
2718   - }
2719   - } else {
2720   - count++;
2721   - }
2722   - }
2723   - }
2724   -
2725   - return count;
2726 2564 }
2727   -
2728   -static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
  2565 +#endif /* TODO */
  2566 +
  2567 +/* e200 core */
  2568 +#if defined(TODO)
  2569 +#endif /* TODO */
  2570 +
  2571 +/* e300 core */
  2572 +#if defined(TODO)
  2573 +#endif /* TODO */
  2574 +
  2575 +/* e500 core */
  2576 +#if defined(TODO)
  2577 +#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
  2578 + PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
  2579 + PPC_CACHE_DCBA | \
  2580 + PPC_BOOKE | PPC_E500_VECTOR)
  2581 +#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
  2582 +#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
  2583 +#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
  2584 +
  2585 +static void init_proc_e500 (CPUPPCState *env)
2729 2586 {
2730   - if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2731   - printf("*** WARNING: no opcode defined !\n");
  2587 + /* Time base */
  2588 + gen_tbl(env);
  2589 + gen_spr_BookE(env);
  2590 + /* Memory management */
  2591 + gen_spr_BookE_FSL(env);
  2592 + env->nb_tlb = 64;
  2593 + env->nb_ways = 1;
  2594 + env->id_tlbs = 0;
  2595 + /* XXX: TODO: allocate internal IRQ controller */
2732 2596 }
2733   -
2734   -/*****************************************************************************/
2735   -static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
  2597 +#endif /* TODO */
  2598 +
  2599 +/* e600 core */
  2600 +#if defined(TODO)
  2601 +#endif /* TODO */
  2602 +
  2603 +/* Non-embedded PowerPC */
  2604 +/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
  2605 +#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
  2606 + PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
  2607 +/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
  2608 +#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
  2609 + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
  2610 + PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
  2611 + PPC_MEM_TLBSYNC | PPC_MFTB)
  2612 +
  2613 +/* POWER : same as 601, without mfmsr, mfsr */
  2614 +#if defined(TODO)
  2615 +#define POWERPC_INSNS_POWER (XXX_TODO)
  2616 +/* POWER RSC (from RAD6000) */
  2617 +#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
  2618 +#endif /* TODO */
  2619 +
  2620 +/* PowerPC 601 */
  2621 +#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
  2622 +#define POWERPC_MSRM_601 (0x000000000000FE70ULL)
  2623 +//#define POWERPC_MMU_601 (POWERPC_MMU_601)
  2624 +//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
  2625 +#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
  2626 +
  2627 +static void init_proc_601 (CPUPPCState *env)
2736 2628 {
2737   - opcode_t *opc, *start, *end;
2738   -
2739   - fill_new_table(env->opcodes, 0x40);
2740   -#if defined(PPC_DUMP_CPU)
2741   - printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2742   - " %08x\n",
2743   - def->pvr, def->name, def->insns_flags, def->flags);
2744   -#endif
2745   - if (&opc_start < &opc_end) {
2746   - start = &opc_start;
2747   - end = &opc_end;
2748   - } else {
2749   - start = &opc_end;
2750   - end = &opc_start;
2751   - }
2752   - for (opc = start + 1; opc != end; opc++) {
2753   - if ((opc->handler.type & def->insns_flags) != 0) {
2754   - if (register_insn(env->opcodes, opc) < 0) {
2755   - printf("*** ERROR initializing PowerPC instruction "
2756   - "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2757   - opc->opc3);
2758   - return -1;
2759   - }
2760   -#if defined(PPC_DUMP_CPU)
2761   - if (opc1 != 0x00) {
2762   - if (opc->opc3 == 0xFF) {
2763   - if (opc->opc2 == 0xFF) {
2764   - printf("INSN: %02x -- -- (%02d ----) : %s\n",
2765   - opc->opc1, opc->opc1, opc->oname);
2766   - } else {
2767   - printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
2768   - opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2769   - opc->oname);
2770   - }
2771   - } else {
2772   - printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
2773   - opc->opc1, opc->opc2, opc->opc3,
2774   - opc->opc1, (opc->opc3 << 5) | opc->opc2,
2775   - opc->oname);
2776   - }
2777   - }
2778   -#endif
2779   - }
2780   - }
2781   - fix_opcode_tables(env->opcodes);
2782   - fflush(stdout);
2783   - fflush(stderr);
2784   -
2785   - return 0;
  2629 + gen_spr_ne_601(env);
  2630 + gen_spr_601(env);
  2631 + /* Hardware implementation registers */
  2632 + /* XXX : not implemented */
  2633 + spr_register(env, SPR_HID0, "HID0",
  2634 + SPR_NOACCESS, SPR_NOACCESS,
  2635 + &spr_read_generic, &spr_write_generic,
  2636 + 0x00000000);
  2637 + /* XXX : not implemented */
  2638 + spr_register(env, SPR_HID1, "HID1",
  2639 + SPR_NOACCESS, SPR_NOACCESS,
  2640 + &spr_read_generic, &spr_write_generic,
  2641 + 0x00000000);
  2642 + /* XXX : not implemented */
  2643 + spr_register(env, SPR_601_HID2, "HID2",
  2644 + SPR_NOACCESS, SPR_NOACCESS,
  2645 + &spr_read_generic, &spr_write_generic,
  2646 + 0x00000000);
  2647 + /* XXX : not implemented */
  2648 + spr_register(env, SPR_601_HID5, "HID5",
  2649 + SPR_NOACCESS, SPR_NOACCESS,
  2650 + &spr_read_generic, &spr_write_generic,
  2651 + 0x00000000);
  2652 + /* XXX : not implemented */
  2653 + spr_register(env, SPR_601_HID15, "HID15",
  2654 + SPR_NOACCESS, SPR_NOACCESS,
  2655 + &spr_read_generic, &spr_write_generic,
  2656 + 0x00000000);
  2657 + /* Memory management */
  2658 + env->nb_tlb = 64;
  2659 + env->nb_ways = 2;
  2660 + env->id_tlbs = 0;
  2661 + env->id_tlbs = 0;
  2662 + /* XXX: TODO: allocate internal IRQ controller */
2786 2663 }
2787 2664  
2788   -int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
  2665 +/* PowerPC 602 */
  2666 +#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
  2667 + PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
  2668 + PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
  2669 + PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
  2670 +#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
  2671 +#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
  2672 +//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
  2673 +#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
  2674 +
  2675 +static void init_proc_602 (CPUPPCState *env)
2789 2676 {
2790   - env->msr_mask = def->msr_mask;
2791   - env->flags = def->flags;
2792   - if (create_ppc_opcodes(env, def) < 0)
2793   - return -1;
2794   - init_ppc_proc(env, def);
2795   -#if defined(PPC_DUMP_CPU)
2796   - dump_sprs(env);
2797   - if (env->tlb != NULL) {
2798   - printf("%d %s TLB in %d ways\n", env->nb_tlb,
2799   - env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2800   - }
2801   -#endif
  2677 + gen_spr_ne_601(env);
  2678 + gen_spr_602(env);
  2679 + /* Time base */
  2680 + gen_tbl(env);
  2681 + /* hardware implementation registers */
  2682 + /* XXX : not implemented */
  2683 + spr_register(env, SPR_HID0, "HID0",
  2684 + SPR_NOACCESS, SPR_NOACCESS,
  2685 + &spr_read_generic, &spr_write_generic,
  2686 + 0x00000000);
  2687 + /* XXX : not implemented */
  2688 + spr_register(env, SPR_HID1, "HID1",
  2689 + SPR_NOACCESS, SPR_NOACCESS,
  2690 + &spr_read_generic, &spr_write_generic,
  2691 + 0x00000000);
  2692 + /* Memory management */
  2693 + gen_low_BATs(env);
  2694 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2695 + /* Allocate hardware IRQ controller */
  2696 + ppc6xx_irq_init(env);
  2697 +}
2802 2698  
2803   - return 0;
  2699 +/* PowerPC 603 */
  2700 +#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  2701 +#define POWERPC_MSRM_603 (0x000000000001FF73ULL)
  2702 +#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
  2703 +//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
  2704 +#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
  2705 +
  2706 +static void init_proc_603 (CPUPPCState *env)
  2707 +{
  2708 + gen_spr_ne_601(env);
  2709 + gen_spr_603(env);
  2710 + /* Time base */
  2711 + gen_tbl(env);
  2712 + /* hardware implementation registers */
  2713 + /* XXX : not implemented */
  2714 + spr_register(env, SPR_HID0, "HID0",
  2715 + SPR_NOACCESS, SPR_NOACCESS,
  2716 + &spr_read_generic, &spr_write_generic,
  2717 + 0x00000000);
  2718 + /* XXX : not implemented */
  2719 + spr_register(env, SPR_HID1, "HID1",
  2720 + SPR_NOACCESS, SPR_NOACCESS,
  2721 + &spr_read_generic, &spr_write_generic,
  2722 + 0x00000000);
  2723 + /* Memory management */
  2724 + gen_low_BATs(env);
  2725 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2726 + /* Allocate hardware IRQ controller */
  2727 + ppc6xx_irq_init(env);
2804 2728 }
2805 2729  
  2730 +/* PowerPC 603e */
  2731 +#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  2732 +#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
  2733 +#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
  2734 +//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
  2735 +#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
  2736 +
  2737 +static void init_proc_603E (CPUPPCState *env)
  2738 +{
  2739 + gen_spr_ne_601(env);
  2740 + gen_spr_603(env);
  2741 + /* Time base */
  2742 + gen_tbl(env);
  2743 + /* hardware implementation registers */
  2744 + /* XXX : not implemented */
  2745 + spr_register(env, SPR_HID0, "HID0",
  2746 + SPR_NOACCESS, SPR_NOACCESS,
  2747 + &spr_read_generic, &spr_write_generic,
  2748 + 0x00000000);
  2749 + /* XXX : not implemented */
  2750 + spr_register(env, SPR_HID1, "HID1",
  2751 + SPR_NOACCESS, SPR_NOACCESS,
  2752 + &spr_read_generic, &spr_write_generic,
  2753 + 0x00000000);
  2754 + /* XXX : not implemented */
  2755 + spr_register(env, SPR_IABR, "IABR",
  2756 + SPR_NOACCESS, SPR_NOACCESS,
  2757 + &spr_read_generic, &spr_write_generic,
  2758 + 0x00000000);
  2759 + /* Memory management */
  2760 + gen_low_BATs(env);
  2761 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2762 + /* Allocate hardware IRQ controller */
  2763 + ppc6xx_irq_init(env);
  2764 +}
  2765 +
  2766 +/* PowerPC G2 */
  2767 +#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  2768 +#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
  2769 +#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
  2770 +//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
  2771 +#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
  2772 +
  2773 +static void init_proc_G2 (CPUPPCState *env)
  2774 +{
  2775 + gen_spr_ne_601(env);
  2776 + gen_spr_G2_755(env);
  2777 + gen_spr_G2(env);
  2778 + /* Time base */
  2779 + gen_tbl(env);
  2780 + /* Hardware implementation register */
  2781 + /* XXX : not implemented */
  2782 + spr_register(env, SPR_HID0, "HID0",
  2783 + SPR_NOACCESS, SPR_NOACCESS,
  2784 + &spr_read_generic, &spr_write_generic,
  2785 + 0x00000000);
  2786 + /* XXX : not implemented */
  2787 + spr_register(env, SPR_HID1, "HID1",
  2788 + SPR_NOACCESS, SPR_NOACCESS,
  2789 + &spr_read_generic, &spr_write_generic,
  2790 + 0x00000000);
  2791 + /* XXX : not implemented */
  2792 + spr_register(env, SPR_HID2, "HID2",
  2793 + SPR_NOACCESS, SPR_NOACCESS,
  2794 + &spr_read_generic, &spr_write_generic,
  2795 + 0x00000000);
  2796 + /* Memory management */
  2797 + gen_low_BATs(env);
  2798 + gen_high_BATs(env);
  2799 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2800 + /* Allocate hardware IRQ controller */
  2801 + ppc6xx_irq_init(env);
  2802 +}
  2803 +
  2804 +/* PowerPC G2LE */
  2805 +#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  2806 +#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
  2807 +#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
  2808 +#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
  2809 +#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
  2810 +
  2811 +static void init_proc_G2LE (CPUPPCState *env)
  2812 +{
  2813 + gen_spr_ne_601(env);
  2814 + gen_spr_G2_755(env);
  2815 + gen_spr_G2(env);
  2816 + /* Time base */
  2817 + gen_tbl(env);
  2818 + /* Hardware implementation register */
  2819 + /* XXX : not implemented */
  2820 + spr_register(env, SPR_HID0, "HID0",
  2821 + SPR_NOACCESS, SPR_NOACCESS,
  2822 + &spr_read_generic, &spr_write_generic,
  2823 + 0x00000000);
  2824 + /* XXX : not implemented */
  2825 + spr_register(env, SPR_HID1, "HID1",
  2826 + SPR_NOACCESS, SPR_NOACCESS,
  2827 + &spr_read_generic, &spr_write_generic,
  2828 + 0x00000000);
  2829 + /* XXX : not implemented */
  2830 + spr_register(env, SPR_HID2, "HID2",
  2831 + SPR_NOACCESS, SPR_NOACCESS,
  2832 + &spr_read_generic, &spr_write_generic,
  2833 + 0x00000000);
  2834 + /* Memory management */
  2835 + gen_low_BATs(env);
  2836 + gen_high_BATs(env);
  2837 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2838 + /* Allocate hardware IRQ controller */
  2839 + ppc6xx_irq_init(env);
  2840 +}
  2841 +
  2842 +/* PowerPC 604 */
  2843 +#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
  2844 +#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
  2845 +#define POWERPC_MMU_604 (POWERPC_MMU_32B)
  2846 +//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
  2847 +#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
  2848 +
  2849 +static void init_proc_604 (CPUPPCState *env)
  2850 +{
  2851 + gen_spr_ne_601(env);
  2852 + gen_spr_604(env);
  2853 + /* Time base */
  2854 + gen_tbl(env);
  2855 + /* Hardware implementation registers */
  2856 + /* XXX : not implemented */
  2857 + spr_register(env, SPR_HID0, "HID0",
  2858 + SPR_NOACCESS, SPR_NOACCESS,
  2859 + &spr_read_generic, &spr_write_generic,
  2860 + 0x00000000);
  2861 + /* XXX : not implemented */
  2862 + spr_register(env, SPR_HID1, "HID1",
  2863 + SPR_NOACCESS, SPR_NOACCESS,
  2864 + &spr_read_generic, &spr_write_generic,
  2865 + 0x00000000);
  2866 + /* Memory management */
  2867 + gen_low_BATs(env);
  2868 + /* Allocate hardware IRQ controller */
  2869 + ppc6xx_irq_init(env);
  2870 +}
  2871 +
  2872 +/* PowerPC 740/750 (aka G3) */
  2873 +#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
  2874 +#define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
  2875 +#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
  2876 +//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
  2877 +#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
  2878 +
  2879 +static void init_proc_7x0 (CPUPPCState *env)
  2880 +{
  2881 + gen_spr_ne_601(env);
  2882 + gen_spr_7xx(env);
  2883 + /* Time base */
  2884 + gen_tbl(env);
  2885 + /* Thermal management */
  2886 + gen_spr_thrm(env);
  2887 + /* Hardware implementation registers */
  2888 + /* XXX : not implemented */
  2889 + spr_register(env, SPR_HID0, "HID0",
  2890 + SPR_NOACCESS, SPR_NOACCESS,
  2891 + &spr_read_generic, &spr_write_generic,
  2892 + 0x00000000);
  2893 + /* XXX : not implemented */
  2894 + spr_register(env, SPR_HID1, "HID1",
  2895 + SPR_NOACCESS, SPR_NOACCESS,
  2896 + &spr_read_generic, &spr_write_generic,
  2897 + 0x00000000);
  2898 + /* Memory management */
  2899 + gen_low_BATs(env);
  2900 + /* Allocate hardware IRQ controller */
  2901 + ppc6xx_irq_init(env);
  2902 +}
  2903 +
  2904 +/* PowerPC 750FX/GX */
  2905 +#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
  2906 +#define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
  2907 +#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
  2908 +#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
  2909 +#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
  2910 +
  2911 +static void init_proc_750fx (CPUPPCState *env)
  2912 +{
  2913 + gen_spr_ne_601(env);
  2914 + gen_spr_7xx(env);
  2915 + /* Time base */
  2916 + gen_tbl(env);
  2917 + /* Thermal management */
  2918 + gen_spr_thrm(env);
  2919 + /* Hardware implementation registers */
  2920 + /* XXX : not implemented */
  2921 + spr_register(env, SPR_HID0, "HID0",
  2922 + SPR_NOACCESS, SPR_NOACCESS,
  2923 + &spr_read_generic, &spr_write_generic,
  2924 + 0x00000000);
  2925 + /* XXX : not implemented */
  2926 + spr_register(env, SPR_HID1, "HID1",
  2927 + SPR_NOACCESS, SPR_NOACCESS,
  2928 + &spr_read_generic, &spr_write_generic,
  2929 + 0x00000000);
  2930 + /* XXX : not implemented */
  2931 + spr_register(env, SPR_750_HID2, "HID2",
  2932 + SPR_NOACCESS, SPR_NOACCESS,
  2933 + &spr_read_generic, &spr_write_generic,
  2934 + 0x00000000);
  2935 + /* Memory management */
  2936 + gen_low_BATs(env);
  2937 + /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
  2938 + gen_high_BATs(env);
  2939 + /* Allocate hardware IRQ controller */
  2940 + ppc6xx_irq_init(env);
  2941 +}
  2942 +
  2943 +/* PowerPC 745/755 */
  2944 +#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
  2945 +#define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
  2946 +#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
  2947 +//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
  2948 +#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
  2949 +
  2950 +static void init_proc_7x5 (CPUPPCState *env)
  2951 +{
  2952 + gen_spr_ne_601(env);
  2953 + gen_spr_G2_755(env);
  2954 + /* Time base */
  2955 + gen_tbl(env);
  2956 + /* L2 cache control */
  2957 + /* XXX : not implemented */
  2958 + spr_register(env, SPR_ICTC, "ICTC",
  2959 + SPR_NOACCESS, SPR_NOACCESS,
  2960 + &spr_read_generic, &spr_write_generic,
  2961 + 0x00000000);
  2962 + /* XXX : not implemented */
  2963 + spr_register(env, SPR_L2PMCR, "L2PMCR",
  2964 + SPR_NOACCESS, SPR_NOACCESS,
  2965 + &spr_read_generic, &spr_write_generic,
  2966 + 0x00000000);
  2967 + /* Hardware implementation registers */
  2968 + /* XXX : not implemented */
  2969 + spr_register(env, SPR_HID0, "HID0",
  2970 + SPR_NOACCESS, SPR_NOACCESS,
  2971 + &spr_read_generic, &spr_write_generic,
  2972 + 0x00000000);
  2973 + /* XXX : not implemented */
  2974 + spr_register(env, SPR_HID1, "HID1",
  2975 + SPR_NOACCESS, SPR_NOACCESS,
  2976 + &spr_read_generic, &spr_write_generic,
  2977 + 0x00000000);
  2978 + /* XXX : not implemented */
  2979 + spr_register(env, SPR_HID2, "HID2",
  2980 + SPR_NOACCESS, SPR_NOACCESS,
  2981 + &spr_read_generic, &spr_write_generic,
  2982 + 0x00000000);
  2983 + /* Memory management */
  2984 + gen_low_BATs(env);
  2985 + gen_high_BATs(env);
  2986 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  2987 + /* Allocate hardware IRQ controller */
  2988 + ppc6xx_irq_init(env);
  2989 +}
  2990 +
  2991 +/* PowerPC 7400 (aka G4) */
  2992 +#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  2993 + PPC_EXTERN | PPC_MEM_TLBIA | \
  2994 + PPC_ALTIVEC)
  2995 +#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
  2996 +#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
  2997 +#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
  2998 +#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
  2999 +
  3000 +static void init_proc_7400 (CPUPPCState *env)
  3001 +{
  3002 + gen_spr_ne_601(env);
  3003 + gen_spr_7xx(env);
  3004 + /* Time base */
  3005 + gen_tbl(env);
  3006 + /* 74xx specific SPR */
  3007 + gen_spr_74xx(env);
  3008 + /* Thermal management */
  3009 + gen_spr_thrm(env);
  3010 + /* Memory management */
  3011 + gen_low_BATs(env);
  3012 + /* Allocate hardware IRQ controller */
  3013 + ppc6xx_irq_init(env);
  3014 +}
  3015 +
  3016 +/* PowerPC 7410 (aka G4) */
  3017 +#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  3018 + PPC_EXTERN | PPC_MEM_TLBIA | \
  3019 + PPC_ALTIVEC)
  3020 +#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
  3021 +#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
  3022 +#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
  3023 +#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
  3024 +
  3025 +static void init_proc_7410 (CPUPPCState *env)
  3026 +{
  3027 + gen_spr_ne_601(env);
  3028 + gen_spr_7xx(env);
  3029 + /* Time base */
  3030 + gen_tbl(env);
  3031 + /* 74xx specific SPR */
  3032 + gen_spr_74xx(env);
  3033 + /* Thermal management */
  3034 + gen_spr_thrm(env);
  3035 + /* L2PMCR */
  3036 + /* XXX : not implemented */
  3037 + spr_register(env, SPR_L2PMCR, "L2PMCR",
  3038 + SPR_NOACCESS, SPR_NOACCESS,
  3039 + &spr_read_generic, &spr_write_generic,
  3040 + 0x00000000);
  3041 + /* LDSTDB */
  3042 + /* XXX : not implemented */
  3043 + spr_register(env, SPR_LDSTDB, "LDSTDB",
  3044 + SPR_NOACCESS, SPR_NOACCESS,
  3045 + &spr_read_generic, &spr_write_generic,
  3046 + 0x00000000);
  3047 + /* Memory management */
  3048 + gen_low_BATs(env);
  3049 + /* Allocate hardware IRQ controller */
  3050 + ppc6xx_irq_init(env);
  3051 +}
  3052 +
  3053 +/* PowerPC 7440 (aka G4) */
  3054 +#if defined (TODO)
  3055 +#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  3056 + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
  3057 + PPC_ALTIVEC)
  3058 +#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
  3059 +#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
  3060 +#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
  3061 +#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
  3062 +
  3063 +static void init_proc_7440 (CPUPPCState *env)
  3064 +{
  3065 + gen_spr_ne_601(env);
  3066 + gen_spr_7xx(env);
  3067 + /* Time base */
  3068 + gen_tbl(env);
  3069 + /* 74xx specific SPR */
  3070 + gen_spr_74xx(env);
  3071 + /* LDSTCR */
  3072 + /* XXX : not implemented */
  3073 + spr_register(env, SPR_LDSTCR, "LDSTCR",
  3074 + SPR_NOACCESS, SPR_NOACCESS,
  3075 + &spr_read_generic, &spr_write_generic,
  3076 + 0x00000000);
  3077 + /* ICTRL */
  3078 + /* XXX : not implemented */
  3079 + spr_register(env, SPR_ICTRL, "ICTRL",
  3080 + SPR_NOACCESS, SPR_NOACCESS,
  3081 + &spr_read_generic, &spr_write_generic,
  3082 + 0x00000000);
  3083 + /* MSSSR0 */
  3084 + spr_register(env, SPR_MSSSR0, "MSSSR0",
  3085 + SPR_NOACCESS, SPR_NOACCESS,
  3086 + &spr_read_generic, &spr_write_generic,
  3087 + 0x00000000);
  3088 + /* PMC */
  3089 + /* XXX : not implemented */
  3090 + spr_register(env, SPR_PMC5, "PMC5",
  3091 + SPR_NOACCESS, SPR_NOACCESS,
  3092 + &spr_read_generic, &spr_write_generic,
  3093 + 0x00000000);
  3094 + spr_register(env, SPR_UPMC5, "UPMC5",
  3095 + &spr_read_ureg, SPR_NOACCESS,
  3096 + &spr_read_ureg, SPR_NOACCESS,
  3097 + 0x00000000);
  3098 + spr_register(env, SPR_PMC6, "PMC6",
  3099 + SPR_NOACCESS, SPR_NOACCESS,
  3100 + &spr_read_generic, &spr_write_generic,
  3101 + 0x00000000);
  3102 + spr_register(env, SPR_UPMC6, "UPMC6",
  3103 + &spr_read_ureg, SPR_NOACCESS,
  3104 + &spr_read_ureg, SPR_NOACCESS,
  3105 + 0x00000000);
  3106 + /* Memory management */
  3107 + gen_low_BATs(env);
  3108 + gen_74xx_soft_tlb(env);
  3109 + /* Allocate hardware IRQ controller */
  3110 + ppc6xx_irq_init(env);
  3111 +}
  3112 +#endif /* TODO */
  3113 +
  3114 +/* PowerPC 7450 (aka G4) */
  3115 +#if defined (TODO)
  3116 +#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  3117 + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
  3118 + PPC_ALTIVEC)
  3119 +#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
  3120 +#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
  3121 +#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
  3122 +#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
  3123 +
  3124 +static void init_proc_7450 (CPUPPCState *env)
  3125 +{
  3126 + gen_spr_ne_601(env);
  3127 + gen_spr_7xx(env);
  3128 + /* Time base */
  3129 + gen_tbl(env);
  3130 + /* 74xx specific SPR */
  3131 + gen_spr_74xx(env);
  3132 + /* Level 3 cache control */
  3133 + gen_l3_ctrl(env);
  3134 + /* LDSTCR */
  3135 + /* XXX : not implemented */
  3136 + spr_register(env, SPR_LDSTCR, "LDSTCR",
  3137 + SPR_NOACCESS, SPR_NOACCESS,
  3138 + &spr_read_generic, &spr_write_generic,
  3139 + 0x00000000);
  3140 + /* ICTRL */
  3141 + /* XXX : not implemented */
  3142 + spr_register(env, SPR_ICTRL, "ICTRL",
  3143 + SPR_NOACCESS, SPR_NOACCESS,
  3144 + &spr_read_generic, &spr_write_generic,
  3145 + 0x00000000);
  3146 + /* MSSSR0 */
  3147 + spr_register(env, SPR_MSSSR0, "MSSSR0",
  3148 + SPR_NOACCESS, SPR_NOACCESS,
  3149 + &spr_read_generic, &spr_write_generic,
  3150 + 0x00000000);
  3151 + /* PMC */
  3152 + /* XXX : not implemented */
  3153 + spr_register(env, SPR_PMC5, "PMC5",
  3154 + SPR_NOACCESS, SPR_NOACCESS,
  3155 + &spr_read_generic, &spr_write_generic,
  3156 + 0x00000000);
  3157 + spr_register(env, SPR_UPMC5, "UPMC5",
  3158 + &spr_read_ureg, SPR_NOACCESS,
  3159 + &spr_read_ureg, SPR_NOACCESS,
  3160 + 0x00000000);
  3161 + spr_register(env, SPR_PMC6, "PMC6",
  3162 + SPR_NOACCESS, SPR_NOACCESS,
  3163 + &spr_read_generic, &spr_write_generic,
  3164 + 0x00000000);
  3165 + spr_register(env, SPR_UPMC6, "UPMC6",
  3166 + &spr_read_ureg, SPR_NOACCESS,
  3167 + &spr_read_ureg, SPR_NOACCESS,
  3168 + 0x00000000);
  3169 + /* Memory management */
  3170 + gen_low_BATs(env);
  3171 + gen_74xx_soft_tlb(env);
  3172 + /* Allocate hardware IRQ controller */
  3173 + ppc6xx_irq_init(env);
  3174 +}
  3175 +#endif /* TODO */
  3176 +
  3177 +/* PowerPC 7445 (aka G4) */
  3178 +#if defined (TODO)
  3179 +#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  3180 + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
  3181 + PPC_ALTIVEC)
  3182 +#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
  3183 +#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
  3184 +#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
  3185 +#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
  3186 +
  3187 +static void init_proc_7445 (CPUPPCState *env)
  3188 +{
  3189 + gen_spr_ne_601(env);
  3190 + gen_spr_7xx(env);
  3191 + /* Time base */
  3192 + gen_tbl(env);
  3193 + /* 74xx specific SPR */
  3194 + gen_spr_74xx(env);
  3195 + /* LDSTCR */
  3196 + /* XXX : not implemented */
  3197 + spr_register(env, SPR_LDSTCR, "LDSTCR",
  3198 + SPR_NOACCESS, SPR_NOACCESS,
  3199 + &spr_read_generic, &spr_write_generic,
  3200 + 0x00000000);
  3201 + /* ICTRL */
  3202 + /* XXX : not implemented */
  3203 + spr_register(env, SPR_ICTRL, "ICTRL",
  3204 + SPR_NOACCESS, SPR_NOACCESS,
  3205 + &spr_read_generic, &spr_write_generic,
  3206 + 0x00000000);
  3207 + /* MSSSR0 */
  3208 + spr_register(env, SPR_MSSSR0, "MSSSR0",
  3209 + SPR_NOACCESS, SPR_NOACCESS,
  3210 + &spr_read_generic, &spr_write_generic,
  3211 + 0x00000000);
  3212 + /* PMC */
  3213 + /* XXX : not implemented */
  3214 + spr_register(env, SPR_PMC5, "PMC5",
  3215 + SPR_NOACCESS, SPR_NOACCESS,
  3216 + &spr_read_generic, &spr_write_generic,
  3217 + 0x00000000);
  3218 + spr_register(env, SPR_UPMC5, "UPMC5",
  3219 + &spr_read_ureg, SPR_NOACCESS,
  3220 + &spr_read_ureg, SPR_NOACCESS,
  3221 + 0x00000000);
  3222 + spr_register(env, SPR_PMC6, "PMC6",
  3223 + SPR_NOACCESS, SPR_NOACCESS,
  3224 + &spr_read_generic, &spr_write_generic,
  3225 + 0x00000000);
  3226 + spr_register(env, SPR_UPMC6, "UPMC6",
  3227 + &spr_read_ureg, SPR_NOACCESS,
  3228 + &spr_read_ureg, SPR_NOACCESS,
  3229 + 0x00000000);
  3230 + /* SPRGs */
  3231 + spr_register(env, SPR_SPRG4, "SPRG4",
  3232 + SPR_NOACCESS, SPR_NOACCESS,
  3233 + &spr_read_generic, &spr_write_generic,
  3234 + 0x00000000);
  3235 + spr_register(env, SPR_USPRG4, "USPRG4",
  3236 + &spr_read_ureg, SPR_NOACCESS,
  3237 + &spr_read_ureg, SPR_NOACCESS,
  3238 + 0x00000000);
  3239 + spr_register(env, SPR_SPRG5, "SPRG5",
  3240 + SPR_NOACCESS, SPR_NOACCESS,
  3241 + &spr_read_generic, &spr_write_generic,
  3242 + 0x00000000);
  3243 + spr_register(env, SPR_USPRG5, "USPRG5",
  3244 + &spr_read_ureg, SPR_NOACCESS,
  3245 + &spr_read_ureg, SPR_NOACCESS,
  3246 + 0x00000000);
  3247 + spr_register(env, SPR_SPRG6, "SPRG6",
  3248 + SPR_NOACCESS, SPR_NOACCESS,
  3249 + &spr_read_generic, &spr_write_generic,
  3250 + 0x00000000);
  3251 + spr_register(env, SPR_USPRG6, "USPRG6",
  3252 + &spr_read_ureg, SPR_NOACCESS,
  3253 + &spr_read_ureg, SPR_NOACCESS,
  3254 + 0x00000000);
  3255 + spr_register(env, SPR_SPRG7, "SPRG7",
  3256 + SPR_NOACCESS, SPR_NOACCESS,
  3257 + &spr_read_generic, &spr_write_generic,
  3258 + 0x00000000);
  3259 + spr_register(env, SPR_USPRG7, "USPRG7",
  3260 + &spr_read_ureg, SPR_NOACCESS,
  3261 + &spr_read_ureg, SPR_NOACCESS,
  3262 + 0x00000000);
  3263 + /* Memory management */
  3264 + gen_low_BATs(env);
  3265 + gen_high_BATs(env);
  3266 + gen_74xx_soft_tlb(env);
  3267 + /* Allocate hardware IRQ controller */
  3268 + ppc6xx_irq_init(env);
  3269 +}
  3270 +#endif /* TODO */
  3271 +
  3272 +/* PowerPC 7455 (aka G4) */
  3273 +#if defined (TODO)
  3274 +#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
  3275 + PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
  3276 + PPC_ALTIVEC)
  3277 +#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
  3278 +#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
  3279 +#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
  3280 +#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
  3281 +
  3282 +static void init_proc_7455 (CPUPPCState *env)
  3283 +{
  3284 + gen_spr_ne_601(env);
  3285 + gen_spr_7xx(env);
  3286 + /* Time base */
  3287 + gen_tbl(env);
  3288 + /* 74xx specific SPR */
  3289 + gen_spr_74xx(env);
  3290 + /* Level 3 cache control */
  3291 + gen_l3_ctrl(env);
  3292 + /* LDSTCR */
  3293 + /* XXX : not implemented */
  3294 + spr_register(env, SPR_LDSTCR, "LDSTCR",
  3295 + SPR_NOACCESS, SPR_NOACCESS,
  3296 + &spr_read_generic, &spr_write_generic,
  3297 + 0x00000000);
  3298 + /* ICTRL */
  3299 + /* XXX : not implemented */
  3300 + spr_register(env, SPR_ICTRL, "ICTRL",
  3301 + SPR_NOACCESS, SPR_NOACCESS,
  3302 + &spr_read_generic, &spr_write_generic,
  3303 + 0x00000000);
  3304 + /* MSSSR0 */
  3305 + spr_register(env, SPR_MSSSR0, "MSSSR0",
  3306 + SPR_NOACCESS, SPR_NOACCESS,
  3307 + &spr_read_generic, &spr_write_generic,
  3308 + 0x00000000);
  3309 + /* PMC */
  3310 + /* XXX : not implemented */
  3311 + spr_register(env, SPR_PMC5, "PMC5",
  3312 + SPR_NOACCESS, SPR_NOACCESS,
  3313 + &spr_read_generic, &spr_write_generic,
  3314 + 0x00000000);
  3315 + spr_register(env, SPR_UPMC5, "UPMC5",
  3316 + &spr_read_ureg, SPR_NOACCESS,
  3317 + &spr_read_ureg, SPR_NOACCESS,
  3318 + 0x00000000);
  3319 + spr_register(env, SPR_PMC6, "PMC6",
  3320 + SPR_NOACCESS, SPR_NOACCESS,
  3321 + &spr_read_generic, &spr_write_generic,
  3322 + 0x00000000);
  3323 + spr_register(env, SPR_UPMC6, "UPMC6",
  3324 + &spr_read_ureg, SPR_NOACCESS,
  3325 + &spr_read_ureg, SPR_NOACCESS,
  3326 + 0x00000000);
  3327 + /* SPRGs */
  3328 + spr_register(env, SPR_SPRG4, "SPRG4",
  3329 + SPR_NOACCESS, SPR_NOACCESS,
  3330 + &spr_read_generic, &spr_write_generic,
  3331 + 0x00000000);
  3332 + spr_register(env, SPR_USPRG4, "USPRG4",
  3333 + &spr_read_ureg, SPR_NOACCESS,
  3334 + &spr_read_ureg, SPR_NOACCESS,
  3335 + 0x00000000);
  3336 + spr_register(env, SPR_SPRG5, "SPRG5",
  3337 + SPR_NOACCESS, SPR_NOACCESS,
  3338 + &spr_read_generic, &spr_write_generic,
  3339 + 0x00000000);
  3340 + spr_register(env, SPR_USPRG5, "USPRG5",
  3341 + &spr_read_ureg, SPR_NOACCESS,
  3342 + &spr_read_ureg, SPR_NOACCESS,
  3343 + 0x00000000);
  3344 + spr_register(env, SPR_SPRG6, "SPRG6",
  3345 + SPR_NOACCESS, SPR_NOACCESS,
  3346 + &spr_read_generic, &spr_write_generic,
  3347 + 0x00000000);
  3348 + spr_register(env, SPR_USPRG6, "USPRG6",
  3349 + &spr_read_ureg, SPR_NOACCESS,
  3350 + &spr_read_ureg, SPR_NOACCESS,
  3351 + 0x00000000);
  3352 + spr_register(env, SPR_SPRG7, "SPRG7",
  3353 + SPR_NOACCESS, SPR_NOACCESS,
  3354 + &spr_read_generic, &spr_write_generic,
  3355 + 0x00000000);
  3356 + spr_register(env, SPR_USPRG7, "USPRG7",
  3357 + &spr_read_ureg, SPR_NOACCESS,
  3358 + &spr_read_ureg, SPR_NOACCESS,
  3359 + 0x00000000);
  3360 + /* Memory management */
  3361 + gen_low_BATs(env);
  3362 + gen_high_BATs(env);
  3363 + gen_74xx_soft_tlb(env);
  3364 + /* Allocate hardware IRQ controller */
  3365 + ppc6xx_irq_init(env);
  3366 +}
  3367 +#endif /* TODO */
  3368 +
  3369 +#if defined (TARGET_PPC64)
  3370 +/* PowerPC 970 */
  3371 +#if defined (TODO)
  3372 +#define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  3373 + PPC_64B | PPC_ALTIVEC | \
  3374 + PPC_64_BRIDGE | PPC_SLBI)
  3375 +#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
  3376 +#define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
  3377 +//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
  3378 +#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
  3379 +
  3380 +static void init_proc_970 (CPUPPCState *env)
  3381 +{
  3382 + gen_spr_ne_601(env);
  3383 + gen_spr_7xx(env);
  3384 + /* Time base */
  3385 + gen_tbl(env);
  3386 + /* Hardware implementation registers */
  3387 + /* XXX : not implemented */
  3388 + spr_register(env, SPR_HID0, "HID0",
  3389 + SPR_NOACCESS, SPR_NOACCESS,
  3390 + &spr_read_generic, &spr_write_generic,
  3391 + 0x00000000);
  3392 + /* XXX : not implemented */
  3393 + spr_register(env, SPR_HID1, "HID1",
  3394 + SPR_NOACCESS, SPR_NOACCESS,
  3395 + &spr_read_generic, &spr_write_generic,
  3396 + 0x00000000);
  3397 + /* XXX : not implemented */
  3398 + spr_register(env, SPR_750_HID2, "HID2",
  3399 + SPR_NOACCESS, SPR_NOACCESS,
  3400 + &spr_read_generic, &spr_write_generic,
  3401 + 0x00000000);
  3402 + /* Memory management */
  3403 + /* XXX: not correct */
  3404 + gen_low_BATs(env);
  3405 +#if 0 // TODO
  3406 + env->slb_nr = 32;
  3407 +#endif
  3408 + /* Allocate hardware IRQ controller */
  3409 + ppc970_irq_init(env);
  3410 +}
  3411 +#endif /* TODO */
  3412 +
  3413 +/* PowerPC 970FX (aka G5) */
  3414 +#if defined (TODO)
  3415 +#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  3416 + PPC_64B | PPC_ALTIVEC | \
  3417 + PPC_64_BRIDGE | PPC_SLBI)
  3418 +#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
  3419 +#define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
  3420 +#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
  3421 +#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
  3422 +
  3423 +static void init_proc_970FX (CPUPPCState *env)
  3424 +{
  3425 + gen_spr_ne_601(env);
  3426 + gen_spr_7xx(env);
  3427 + /* Time base */
  3428 + gen_tbl(env);
  3429 + /* Hardware implementation registers */
  3430 + /* XXX : not implemented */
  3431 + spr_register(env, SPR_HID0, "HID0",
  3432 + SPR_NOACCESS, SPR_NOACCESS,
  3433 + &spr_read_generic, &spr_write_generic,
  3434 + 0x00000000);
  3435 + /* XXX : not implemented */
  3436 + spr_register(env, SPR_HID1, "HID1",
  3437 + SPR_NOACCESS, SPR_NOACCESS,
  3438 + &spr_read_generic, &spr_write_generic,
  3439 + 0x00000000);
  3440 + /* XXX : not implemented */
  3441 + spr_register(env, SPR_750_HID2, "HID2",
  3442 + SPR_NOACCESS, SPR_NOACCESS,
  3443 + &spr_read_generic, &spr_write_generic,
  3444 + 0x00000000);
  3445 + /* Memory management */
  3446 + /* XXX: not correct */
  3447 + gen_low_BATs(env);
  3448 +#if 0 // TODO
  3449 + env->slb_nr = 32;
  3450 +#endif
  3451 + /* Allocate hardware IRQ controller */
  3452 + ppc970_irq_init(env);
  3453 +}
  3454 +#endif /* TODO */
  3455 +
  3456 +/* PowerPC 970 GX */
  3457 +#if defined (TODO)
  3458 +#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  3459 + PPC_64B | PPC_ALTIVEC | \
  3460 + PPC_64_BRIDGE | PPC_SLBI)
  3461 +#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
  3462 +#define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
  3463 +#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
  3464 +#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
  3465 +
  3466 +static void init_proc_970GX (CPUPPCState *env)
  3467 +{
  3468 + gen_spr_ne_601(env);
  3469 + gen_spr_7xx(env);
  3470 + /* Time base */
  3471 + gen_tbl(env);
  3472 + /* Hardware implementation registers */
  3473 + /* XXX : not implemented */
  3474 + spr_register(env, SPR_HID0, "HID0",
  3475 + SPR_NOACCESS, SPR_NOACCESS,
  3476 + &spr_read_generic, &spr_write_generic,
  3477 + 0x00000000);
  3478 + /* XXX : not implemented */
  3479 + spr_register(env, SPR_HID1, "HID1",
  3480 + SPR_NOACCESS, SPR_NOACCESS,
  3481 + &spr_read_generic, &spr_write_generic,
  3482 + 0x00000000);
  3483 + /* XXX : not implemented */
  3484 + spr_register(env, SPR_750_HID2, "HID2",
  3485 + SPR_NOACCESS, SPR_NOACCESS,
  3486 + &spr_read_generic, &spr_write_generic,
  3487 + 0x00000000);
  3488 + /* Memory management */
  3489 + /* XXX: not correct */
  3490 + gen_low_BATs(env);
  3491 +#if 0 // TODO
  3492 + env->slb_nr = 32;
  3493 +#endif
  3494 + /* Allocate hardware IRQ controller */
  3495 + ppc970_irq_init(env);
  3496 +}
  3497 +#endif /* TODO */
  3498 +
  3499 +/* PowerPC 620 */
  3500 +#if defined (TODO)
  3501 +#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
  3502 + PPC_64B | PPC_SLBI)
  3503 +#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
  3504 +#define POWERPC_MMU_620 (POWERPC_MMU_64B)
  3505 +#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
  3506 +#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
  3507 +
  3508 +static void init_proc_620 (CPUPPCState *env)
  3509 +{
  3510 + gen_spr_ne_601(env);
  3511 + gen_spr_620(env);
  3512 + /* Time base */
  3513 + gen_tbl(env);
  3514 + /* Hardware implementation registers */
  3515 + /* XXX : not implemented */
  3516 + spr_register(env, SPR_HID0, "HID0",
  3517 + SPR_NOACCESS, SPR_NOACCESS,
  3518 + &spr_read_generic, &spr_write_generic,
  3519 + 0x00000000);
  3520 + /* Memory management */
  3521 + gen_low_BATs(env);
  3522 + gen_high_BATs(env);
  3523 + /* XXX: TODO: initialize internal interrupt controller */
  3524 +}
  3525 +#endif /* TODO */
  3526 +#endif /* defined (TARGET_PPC64) */
  3527 +
  3528 +/* Default 32 bits PowerPC target will be 604 */
  3529 +#define CPU_POWERPC_PPC32 CPU_POWERPC_604
  3530 +#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
  3531 +#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
  3532 +#define POWERPC_MMU_PPC32 POWERPC_MMU_604
  3533 +#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
  3534 +#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
  3535 +#define init_proc_PPC32 init_proc_604
  3536 +
  3537 +/* Default 64 bits PowerPC target will be 970 FX */
  3538 +#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
  3539 +#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
  3540 +#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
  3541 +#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
  3542 +#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
  3543 +#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
  3544 +#define init_proc_PPC64 init_proc_970FX
  3545 +
  3546 +/* Default PowerPC target will be PowerPC 32 */
  3547 +#if defined (TARGET_PPC64) && 0 // XXX: TODO
  3548 +#define CPU_POWERPC_PPC CPU_POWERPC_PPC64
  3549 +#define POWERPC_INSNS_PPC POWERPC_INSNS_PPC64
  3550 +#define POWERPC_MSRM_PPC POWERPC_MSRM_PPC64
  3551 +#define POWERPC_MMU_PPC POWERPC_MMU_PPC64
  3552 +#define POWERPC_EXCP_PPC POWERPC_EXCP_PPC64
  3553 +#define POWERPC_INPUT_PPC POWERPC_INPUT_PPC64
  3554 +#define init_proc_PPC init_proc_PPC64
  3555 +#else
  3556 +#define CPU_POWERPC_PPC CPU_POWERPC_PPC32
  3557 +#define POWERPC_INSNS_PPC POWERPC_INSNS_PPC32
  3558 +#define POWERPC_MSRM_PPC POWERPC_MSRM_PPC32
  3559 +#define POWERPC_MMU_PPC POWERPC_MMU_PPC32
  3560 +#define POWERPC_EXCP_PPC POWERPC_EXCP_PPC32
  3561 +#define POWERPC_INPUT_PPC POWERPC_INPUT_PPC32
  3562 +#define init_proc_PPC init_proc_PPC32
  3563 +#endif
  3564 +
  3565 +/*****************************************************************************/
  3566 +/* PVR definitions for most known PowerPC */
  3567 +enum {
  3568 + /* PowerPC 401 family */
  3569 + /* Generic PowerPC 401 */
  3570 +#define CPU_POWERPC_401 CPU_POWERPC_401G2
  3571 + /* PowerPC 401 cores */
  3572 + CPU_POWERPC_401A1 = 0x00210000,
  3573 + CPU_POWERPC_401B2 = 0x00220000,
  3574 +#if 0
  3575 + CPU_POWERPC_401B3 = xxx,
  3576 +#endif
  3577 + CPU_POWERPC_401C2 = 0x00230000,
  3578 + CPU_POWERPC_401D2 = 0x00240000,
  3579 + CPU_POWERPC_401E2 = 0x00250000,
  3580 + CPU_POWERPC_401F2 = 0x00260000,
  3581 + CPU_POWERPC_401G2 = 0x00270000,
  3582 + /* PowerPC 401 microcontrolers */
  3583 +#if 0
  3584 + CPU_POWERPC_401GF = xxx,
  3585 +#endif
  3586 +#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
  3587 + /* IBM Processor for Network Resources */
  3588 + CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
  3589 +#if 0
  3590 + CPU_POWERPC_XIPCHIP = xxx,
  3591 +#endif
  3592 + /* PowerPC 403 family */
  3593 + /* Generic PowerPC 403 */
  3594 +#define CPU_POWERPC_403 CPU_POWERPC_403GC
  3595 + /* PowerPC 403 microcontrollers */
  3596 + CPU_POWERPC_403GA = 0x00200011,
  3597 + CPU_POWERPC_403GB = 0x00200100,
  3598 + CPU_POWERPC_403GC = 0x00200200,
  3599 + CPU_POWERPC_403GCX = 0x00201400,
  3600 +#if 0
  3601 + CPU_POWERPC_403GP = xxx,
  3602 +#endif
  3603 + /* PowerPC 405 family */
  3604 + /* Generic PowerPC 405 */
  3605 +#define CPU_POWERPC_405 CPU_POWERPC_405D4
  3606 + /* PowerPC 405 cores */
  3607 +#if 0
  3608 + CPU_POWERPC_405A3 = xxx,
  3609 +#endif
  3610 +#if 0
  3611 + CPU_POWERPC_405A4 = xxx,
  3612 +#endif
  3613 +#if 0
  3614 + CPU_POWERPC_405B3 = xxx,
  3615 +#endif
  3616 +#if 0
  3617 + CPU_POWERPC_405B4 = xxx,
  3618 +#endif
  3619 +#if 0
  3620 + CPU_POWERPC_405C3 = xxx,
  3621 +#endif
  3622 +#if 0
  3623 + CPU_POWERPC_405C4 = xxx,
  3624 +#endif
  3625 + CPU_POWERPC_405D2 = 0x20010000,
  3626 +#if 0
  3627 + CPU_POWERPC_405D3 = xxx,
  3628 +#endif
  3629 + CPU_POWERPC_405D4 = 0x41810000,
  3630 +#if 0
  3631 + CPU_POWERPC_405D5 = xxx,
  3632 +#endif
  3633 +#if 0
  3634 + CPU_POWERPC_405E4 = xxx,
  3635 +#endif
  3636 +#if 0
  3637 + CPU_POWERPC_405F4 = xxx,
  3638 +#endif
  3639 +#if 0
  3640 + CPU_POWERPC_405F5 = xxx,
  3641 +#endif
  3642 +#if 0
  3643 + CPU_POWERPC_405F6 = xxx,
  3644 +#endif
  3645 + /* PowerPC 405 microcontrolers */
  3646 + /* XXX: missing 0x200108a0 */
  3647 +#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
  3648 + CPU_POWERPC_405CRa = 0x40110041,
  3649 + CPU_POWERPC_405CRb = 0x401100C5,
  3650 + CPU_POWERPC_405CRc = 0x40110145,
  3651 + CPU_POWERPC_405EP = 0x51210950,
  3652 +#if 0
  3653 + CPU_POWERPC_405EXr = xxx,
  3654 +#endif
  3655 + CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
  3656 +#if 0
  3657 + CPU_POWERPC_405FX = xxx,
  3658 +#endif
  3659 +#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
  3660 + CPU_POWERPC_405GPa = 0x40110000,
  3661 + CPU_POWERPC_405GPb = 0x40110040,
  3662 + CPU_POWERPC_405GPc = 0x40110082,
  3663 + CPU_POWERPC_405GPd = 0x401100C4,
  3664 +#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
  3665 + CPU_POWERPC_405GPR = 0x50910951,
  3666 +#if 0
  3667 + CPU_POWERPC_405H = xxx,
  3668 +#endif
  3669 +#if 0
  3670 + CPU_POWERPC_405L = xxx,
  3671 +#endif
  3672 + CPU_POWERPC_405LP = 0x41F10000,
  3673 +#if 0
  3674 + CPU_POWERPC_405PM = xxx,
  3675 +#endif
  3676 +#if 0
  3677 + CPU_POWERPC_405PS = xxx,
  3678 +#endif
  3679 +#if 0
  3680 + CPU_POWERPC_405S = xxx,
  3681 +#endif
  3682 + /* IBM network processors */
  3683 + CPU_POWERPC_NPE405H = 0x414100C0,
  3684 + CPU_POWERPC_NPE405H2 = 0x41410140,
  3685 + CPU_POWERPC_NPE405L = 0x416100C0,
  3686 + CPU_POWERPC_NPE4GS3 = 0x40B10000,
  3687 +#if 0
  3688 + CPU_POWERPC_NPCxx1 = xxx,
  3689 +#endif
  3690 +#if 0
  3691 + CPU_POWERPC_NPR161 = xxx,
  3692 +#endif
  3693 +#if 0
  3694 + CPU_POWERPC_LC77700 = xxx,
  3695 +#endif
  3696 + /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
  3697 +#if 0
  3698 + CPU_POWERPC_STB01000 = xxx,
  3699 +#endif
  3700 +#if 0
  3701 + CPU_POWERPC_STB01010 = xxx,
  3702 +#endif
  3703 +#if 0
  3704 + CPU_POWERPC_STB0210 = xxx, /* 401B3 */
  3705 +#endif
  3706 + CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
  3707 +#if 0
  3708 + CPU_POWERPC_STB043 = xxx,
  3709 +#endif
  3710 +#if 0
  3711 + CPU_POWERPC_STB045 = xxx,
  3712 +#endif
  3713 + CPU_POWERPC_STB04 = 0x41810000,
  3714 + CPU_POWERPC_STB25 = 0x51510950,
  3715 +#if 0
  3716 + CPU_POWERPC_STB130 = xxx,
  3717 +#endif
  3718 + /* Xilinx cores */
  3719 + CPU_POWERPC_X2VP4 = 0x20010820,
  3720 +#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
  3721 + CPU_POWERPC_X2VP20 = 0x20010860,
  3722 +#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
  3723 +#if 0
  3724 + CPU_POWERPC_ZL10310 = xxx,
  3725 +#endif
  3726 +#if 0
  3727 + CPU_POWERPC_ZL10311 = xxx,
  3728 +#endif
  3729 +#if 0
  3730 + CPU_POWERPC_ZL10320 = xxx,
  3731 +#endif
  3732 +#if 0
  3733 + CPU_POWERPC_ZL10321 = xxx,
  3734 +#endif
  3735 + /* PowerPC 440 family */
  3736 + /* Generic PowerPC 440 */
  3737 +#define CPU_POWERPC_440 CPU_POWERPC_440GXf
  3738 + /* PowerPC 440 cores */
  3739 +#if 0
  3740 + CPU_POWERPC_440A4 = xxx,
  3741 +#endif
  3742 +#if 0
  3743 + CPU_POWERPC_440A5 = xxx,
  3744 +#endif
  3745 +#if 0
  3746 + CPU_POWERPC_440B4 = xxx,
  3747 +#endif
  3748 +#if 0
  3749 + CPU_POWERPC_440F5 = xxx,
  3750 +#endif
  3751 +#if 0
  3752 + CPU_POWERPC_440G5 = xxx,
  3753 +#endif
  3754 +#if 0
  3755 + CPU_POWERPC_440H4 = xxx,
  3756 +#endif
  3757 +#if 0
  3758 + CPU_POWERPC_440H6 = xxx,
  3759 +#endif
  3760 + /* PowerPC 440 microcontrolers */
  3761 +#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
  3762 + CPU_POWERPC_440EPa = 0x42221850,
  3763 + CPU_POWERPC_440EPb = 0x422218D3,
  3764 +#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
  3765 + CPU_POWERPC_440GPb = 0x40120440,
  3766 + CPU_POWERPC_440GPc = 0x40120481,
  3767 +#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
  3768 +#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
  3769 + CPU_POWERPC_440GRX = 0x200008D0,
  3770 +#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
  3771 +#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
  3772 + CPU_POWERPC_440GXa = 0x51B21850,
  3773 + CPU_POWERPC_440GXb = 0x51B21851,
  3774 + CPU_POWERPC_440GXc = 0x51B21892,
  3775 + CPU_POWERPC_440GXf = 0x51B21894,
  3776 +#if 0
  3777 + CPU_POWERPC_440S = xxx,
  3778 +#endif
  3779 + CPU_POWERPC_440SP = 0x53221850,
  3780 + CPU_POWERPC_440SP2 = 0x53221891,
  3781 + CPU_POWERPC_440SPE = 0x53421890,
  3782 + /* PowerPC 460 family */
  3783 +#if 0
  3784 + /* Generic PowerPC 464 */
  3785 +#define CPU_POWERPC_464 CPU_POWERPC_464H90
  3786 +#endif
  3787 + /* PowerPC 464 microcontrolers */
  3788 +#if 0
  3789 + CPU_POWERPC_464H90 = xxx,
  3790 +#endif
  3791 +#if 0
  3792 + CPU_POWERPC_464H90FP = xxx,
  3793 +#endif
  3794 + /* Freescale embedded PowerPC cores */
  3795 + /* e200 family */
  3796 +#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
  3797 +#if 0
  3798 + CPU_POWERPC_e200z0 = xxx,
  3799 +#endif
  3800 +#if 0
  3801 + CPU_POWERPC_e200z3 = xxx,
  3802 +#endif
  3803 + CPU_POWERPC_e200z5 = 0x81000000,
  3804 + CPU_POWERPC_e200z6 = 0x81120000,
  3805 + /* e300 family */
  3806 +#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
  3807 + CPU_POWERPC_e300c1 = 0x00830000,
  3808 + CPU_POWERPC_e300c2 = 0x00840000,
  3809 + CPU_POWERPC_e300c3 = 0x00850000,
  3810 + /* e500 family */
  3811 +#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
  3812 + CPU_POWERPC_e500_v11 = 0x80200010,
  3813 + CPU_POWERPC_e500_v12 = 0x80200020,
  3814 + CPU_POWERPC_e500_v21 = 0x80210010,
  3815 + CPU_POWERPC_e500_v22 = 0x80210020,
  3816 +#if 0
  3817 + CPU_POWERPC_e500mc = xxx,
  3818 +#endif
  3819 + /* e600 family */
  3820 + CPU_POWERPC_e600 = 0x80040010,
  3821 + /* PowerPC MPC 5xx cores */
  3822 + CPU_POWERPC_5xx = 0x00020020,
  3823 + /* PowerPC MPC 8xx cores (aka PowerQUICC) */
  3824 + CPU_POWERPC_8xx = 0x00500000,
  3825 + /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
  3826 + CPU_POWERPC_82xx_HIP3 = 0x00810101,
  3827 + CPU_POWERPC_82xx_HIP4 = 0x80811014,
  3828 + CPU_POWERPC_827x = 0x80822013,
  3829 + /* PowerPC 6xx cores */
  3830 + CPU_POWERPC_601 = 0x00010001,
  3831 + CPU_POWERPC_601a = 0x00010002,
  3832 + CPU_POWERPC_602 = 0x00050100,
  3833 + CPU_POWERPC_603 = 0x00030100,
  3834 +#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
  3835 + CPU_POWERPC_603E_v11 = 0x00060101,
  3836 + CPU_POWERPC_603E_v12 = 0x00060102,
  3837 + CPU_POWERPC_603E_v13 = 0x00060103,
  3838 + CPU_POWERPC_603E_v14 = 0x00060104,
  3839 + CPU_POWERPC_603E_v22 = 0x00060202,
  3840 + CPU_POWERPC_603E_v3 = 0x00060300,
  3841 + CPU_POWERPC_603E_v4 = 0x00060400,
  3842 + CPU_POWERPC_603E_v41 = 0x00060401,
  3843 + CPU_POWERPC_603E7t = 0x00071201,
  3844 + CPU_POWERPC_603E7v = 0x00070100,
  3845 + CPU_POWERPC_603E7v1 = 0x00070101,
  3846 + CPU_POWERPC_603E7v2 = 0x00070201,
  3847 + CPU_POWERPC_603E7 = 0x00070200,
  3848 + CPU_POWERPC_603P = 0x00070000,
  3849 +#define CPU_POWERPC_603R CPU_POWERPC_603E7t
  3850 + CPU_POWERPC_G2 = 0x00810011,
  3851 +#if 0 // Linux pretends the MSB is zero...
  3852 + CPU_POWERPC_G2H4 = 0x80811010,
  3853 + CPU_POWERPC_G2gp = 0x80821010,
  3854 + CPU_POWERPC_G2ls = 0x90810010,
  3855 + CPU_POWERPC_G2LE = 0x80820010,
  3856 + CPU_POWERPC_G2LEgp = 0x80822010,
  3857 + CPU_POWERPC_G2LEls = 0xA0822010,
  3858 +#else
  3859 + CPU_POWERPC_G2H4 = 0x00811010,
  3860 + CPU_POWERPC_G2gp = 0x00821010,
  3861 + CPU_POWERPC_G2ls = 0x10810010,
  3862 + CPU_POWERPC_G2LE = 0x00820010,
  3863 + CPU_POWERPC_G2LEgp = 0x00822010,
  3864 + CPU_POWERPC_G2LEls = 0x20822010,
  3865 +#endif
  3866 + CPU_POWERPC_604 = 0x00040103,
  3867 +#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
  3868 + CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
  3869 + CPU_POWERPC_604E_v22 = 0x00090202,
  3870 + CPU_POWERPC_604E_v24 = 0x00090204,
  3871 + CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
  3872 +#if 0
  3873 + CPU_POWERPC_604EV = xxx,
  3874 +#endif
  3875 + /* PowerPC 740/750 cores (aka G3) */
  3876 + /* XXX: missing 0x00084202 */
  3877 +#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
  3878 + CPU_POWERPC_7x0_v20 = 0x00080200,
  3879 + CPU_POWERPC_7x0_v21 = 0x00080201,
  3880 + CPU_POWERPC_7x0_v22 = 0x00080202,
  3881 + CPU_POWERPC_7x0_v30 = 0x00080300,
  3882 + CPU_POWERPC_7x0_v31 = 0x00080301,
  3883 + CPU_POWERPC_740E = 0x00080100,
  3884 + CPU_POWERPC_7x0P = 0x10080000,
  3885 + /* XXX: missing 0x00087010 (CL ?) */
  3886 + CPU_POWERPC_750CL = 0x00087200,
  3887 +#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
  3888 + CPU_POWERPC_750CX_v21 = 0x00082201,
  3889 + CPU_POWERPC_750CX_v22 = 0x00082202,
  3890 +#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
  3891 + CPU_POWERPC_750CXE_v21 = 0x00082211,
  3892 + CPU_POWERPC_750CXE_v22 = 0x00082212,
  3893 + CPU_POWERPC_750CXE_v23 = 0x00082213,
  3894 + CPU_POWERPC_750CXE_v24 = 0x00082214,
  3895 + CPU_POWERPC_750CXE_v24b = 0x00083214,
  3896 + CPU_POWERPC_750CXE_v31 = 0x00083211,
  3897 + CPU_POWERPC_750CXE_v31b = 0x00083311,
  3898 + CPU_POWERPC_750CXR = 0x00083410,
  3899 + CPU_POWERPC_750E = 0x00080200,
  3900 + CPU_POWERPC_750FL = 0x700A0203,
  3901 +#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
  3902 + CPU_POWERPC_750FX_v10 = 0x70000100,
  3903 + CPU_POWERPC_750FX_v20 = 0x70000200,
  3904 + CPU_POWERPC_750FX_v21 = 0x70000201,
  3905 + CPU_POWERPC_750FX_v22 = 0x70000202,
  3906 + CPU_POWERPC_750FX_v23 = 0x70000203,
  3907 + CPU_POWERPC_750GL = 0x70020102,
  3908 +#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
  3909 + CPU_POWERPC_750GX_v10 = 0x70020100,
  3910 + CPU_POWERPC_750GX_v11 = 0x70020101,
  3911 + CPU_POWERPC_750GX_v12 = 0x70020102,
  3912 +#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
  3913 + CPU_POWERPC_750L_v22 = 0x00088202,
  3914 + CPU_POWERPC_750L_v30 = 0x00088300,
  3915 + CPU_POWERPC_750L_v32 = 0x00088302,
  3916 + /* PowerPC 745/755 cores */
  3917 +#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
  3918 + CPU_POWERPC_7x5_v10 = 0x00083100,
  3919 + CPU_POWERPC_7x5_v11 = 0x00083101,
  3920 + CPU_POWERPC_7x5_v20 = 0x00083200,
  3921 + CPU_POWERPC_7x5_v21 = 0x00083201,
  3922 + CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
  3923 + CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
  3924 + CPU_POWERPC_7x5_v24 = 0x00083204,
  3925 + CPU_POWERPC_7x5_v25 = 0x00083205,
  3926 + CPU_POWERPC_7x5_v26 = 0x00083206,
  3927 + CPU_POWERPC_7x5_v27 = 0x00083207,
  3928 + CPU_POWERPC_7x5_v28 = 0x00083208,
  3929 +#if 0
  3930 + CPU_POWERPC_7x5P = xxx,
  3931 +#endif
  3932 + /* PowerPC 74xx cores (aka G4) */
  3933 + /* XXX: missing 0x000C1101 */
  3934 +#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
  3935 + CPU_POWERPC_7400_v10 = 0x000C0100,
  3936 + CPU_POWERPC_7400_v11 = 0x000C0101,
  3937 + CPU_POWERPC_7400_v20 = 0x000C0200,
  3938 + CPU_POWERPC_7400_v22 = 0x000C0202,
  3939 + CPU_POWERPC_7400_v26 = 0x000C0206,
  3940 + CPU_POWERPC_7400_v27 = 0x000C0207,
  3941 + CPU_POWERPC_7400_v28 = 0x000C0208,
  3942 + CPU_POWERPC_7400_v29 = 0x000C0209,
  3943 +#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
  3944 + CPU_POWERPC_7410_v10 = 0x800C1100,
  3945 + CPU_POWERPC_7410_v11 = 0x800C1101,
  3946 + CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
  3947 + CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
  3948 + CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
  3949 +#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
  3950 + CPU_POWERPC_7448_v10 = 0x80040100,
  3951 + CPU_POWERPC_7448_v11 = 0x80040101,
  3952 + CPU_POWERPC_7448_v20 = 0x80040200,
  3953 + CPU_POWERPC_7448_v21 = 0x80040201,
  3954 +#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
  3955 + CPU_POWERPC_7450_v10 = 0x80000100,
  3956 + CPU_POWERPC_7450_v11 = 0x80000101,
  3957 + CPU_POWERPC_7450_v12 = 0x80000102,
  3958 + CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
  3959 + CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
  3960 + CPU_POWERPC_74x1 = 0x80000203,
  3961 + CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
  3962 + /* XXX: missing 0x80010200 */
  3963 +#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
  3964 + CPU_POWERPC_74x5_v10 = 0x80010100,
  3965 + CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
  3966 + CPU_POWERPC_74x5_v32 = 0x80010302,
  3967 + CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
  3968 + CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
  3969 +#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
  3970 + CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
  3971 + CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
  3972 + CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
  3973 + /* 64 bits PowerPC */
  3974 + CPU_POWERPC_620 = 0x00140000,
  3975 + CPU_POWERPC_630 = 0x00400000,
  3976 + CPU_POWERPC_631 = 0x00410104,
  3977 + CPU_POWERPC_POWER4 = 0x00350000,
  3978 + CPU_POWERPC_POWER4P = 0x00380000,
  3979 + CPU_POWERPC_POWER5 = 0x003A0203,
  3980 +#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
  3981 + CPU_POWERPC_POWER5P = 0x003B0000,
  3982 +#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
  3983 + CPU_POWERPC_POWER6 = 0x003E0000,
  3984 + CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
  3985 + CPU_POWERPC_POWER6A = 0x0F000002,
  3986 + CPU_POWERPC_970 = 0x00390202,
  3987 +#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
  3988 + CPU_POWERPC_970FX_v10 = 0x00391100,
  3989 + CPU_POWERPC_970FX_v20 = 0x003C0200,
  3990 + CPU_POWERPC_970FX_v21 = 0x003C0201,
  3991 + CPU_POWERPC_970FX_v30 = 0x003C0300,
  3992 + CPU_POWERPC_970FX_v31 = 0x003C0301,
  3993 + CPU_POWERPC_970GX = 0x00450000,
  3994 +#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
  3995 + CPU_POWERPC_970MP_v10 = 0x00440100,
  3996 + CPU_POWERPC_970MP_v11 = 0x00440101,
  3997 +#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
  3998 + CPU_POWERPC_CELL_v10 = 0x00700100,
  3999 + CPU_POWERPC_CELL_v20 = 0x00700400,
  4000 + CPU_POWERPC_CELL_v30 = 0x00700500,
  4001 + CPU_POWERPC_CELL_v31 = 0x00700501,
  4002 +#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
  4003 + CPU_POWERPC_RS64 = 0x00330000,
  4004 + CPU_POWERPC_RS64II = 0x00340000,
  4005 + CPU_POWERPC_RS64III = 0x00360000,
  4006 + CPU_POWERPC_RS64IV = 0x00370000,
  4007 + /* Original POWER */
  4008 + /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
  4009 + * POWER2 (RIOS2) & RSC2 (P2SC) here
  4010 + */
  4011 +#if 0
  4012 + CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
  4013 +#endif
  4014 +#if 0
  4015 + CPU_POWER2 = xxx, /* 0x40000 ? */
  4016 +#endif
  4017 + /* PA Semi core */
  4018 + CPU_POWERPC_PA6T = 0x00900000,
  4019 +};
  4020 +
  4021 +/* System version register (used on MPC 8xxx) */
  4022 +enum {
  4023 + PPC_SVR_8540 = 0x80300000,
  4024 + PPC_SVR_8541E = 0x807A0010,
  4025 + PPC_SVR_8543v10 = 0x80320010,
  4026 + PPC_SVR_8543v11 = 0x80320011,
  4027 + PPC_SVR_8543v20 = 0x80320020,
  4028 + PPC_SVR_8543Ev10 = 0x803A0010,
  4029 + PPC_SVR_8543Ev11 = 0x803A0011,
  4030 + PPC_SVR_8543Ev20 = 0x803A0020,
  4031 + PPC_SVR_8545 = 0x80310220,
  4032 + PPC_SVR_8545E = 0x80390220,
  4033 + PPC_SVR_8547E = 0x80390120,
  4034 + PPC_SCR_8548v10 = 0x80310010,
  4035 + PPC_SCR_8548v11 = 0x80310011,
  4036 + PPC_SCR_8548v20 = 0x80310020,
  4037 + PPC_SVR_8548Ev10 = 0x80390010,
  4038 + PPC_SVR_8548Ev11 = 0x80390011,
  4039 + PPC_SVR_8548Ev20 = 0x80390020,
  4040 + PPC_SVR_8555E = 0x80790010,
  4041 + PPC_SVR_8560v10 = 0x80700010,
  4042 + PPC_SVR_8560v20 = 0x80700020,
  4043 +};
  4044 +
2806 4045 /*****************************************************************************/
2807   -/* PowerPC CPU definitions */
  4046 +/* PowerPC CPU definitions */
  4047 +#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
  4048 + { \
  4049 + .name = _name, \
  4050 + .pvr = _pvr, \
  4051 + .pvr_mask = _pvr_mask, \
  4052 + .insns_flags = glue(POWERPC_INSNS_,_type), \
  4053 + .msr_mask = glue(POWERPC_MSRM_,_type), \
  4054 + .mmu_model = glue(POWERPC_MMU_,_type), \
  4055 + .excp_model = glue(POWERPC_EXCP_,_type), \
  4056 + .bus_model = glue(POWERPC_INPUT_,_type), \
  4057 + .init_proc = &glue(init_proc_,_type), \
  4058 + }
  4059 +
2808 4060 static ppc_def_t ppc_defs[] = {
2809   - /* Embedded PowerPC */
  4061 + /* Embedded PowerPC */
  4062 + /* PowerPC 401 family */
2810 4063 /* Generic PowerPC 401 */
2811   - {
2812   - .name = "401",
2813   - .pvr = CPU_PPC_401,
2814   - .pvr_mask = 0xFFFFFFFF,
2815   - .insns_flags = PPC_INSNS_401,
2816   - .flags = PPC_FLAGS_401,
2817   - .msr_mask = 0x000FD201,
2818   - },
  4064 + POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
  4065 + /* PowerPC 401 cores */
2819 4066 /* PowerPC 401A1 */
2820   - {
2821   - .name = "401a1",
2822   - .pvr = CPU_PPC_401A1,
2823   - .pvr_mask = 0xFFFFFFFF,
2824   - .insns_flags = PPC_INSNS_401,
2825   - .flags = PPC_FLAGS_401,
2826   - .msr_mask = 0x000FD201,
2827   - },
2828   - /* PowerPC 401B2 */
2829   - {
2830   - .name = "401b2",
2831   - .pvr = CPU_PPC_401B2,
2832   - .pvr_mask = 0xFFFFFFFF,
2833   - .insns_flags = PPC_INSNS_401,
2834   - .flags = PPC_FLAGS_401,
2835   - .msr_mask = 0x000FD201,
2836   - },
  4067 + POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
  4068 + /* PowerPC 401B2 */
  4069 + POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
2837 4070 #if defined (TODO)
2838   - /* PowerPC 401B3 */
2839   - {
2840   - .name = "401b3",
2841   - .pvr = CPU_PPC_401B3,
2842   - .pvr_mask = 0xFFFFFFFF,
2843   - .insns_flags = PPC_INSNS_401,
2844   - .flags = PPC_FLAGS_401,
2845   - .msr_mask = 0x000FD201,
2846   - },
2847   -#endif
2848   - /* PowerPC 401C2 */
2849   - {
2850   - .name = "401c2",
2851   - .pvr = CPU_PPC_401C2,
2852   - .pvr_mask = 0xFFFFFFFF,
2853   - .insns_flags = PPC_INSNS_401,
2854   - .flags = PPC_FLAGS_401,
2855   - .msr_mask = 0x000FD201,
2856   - },
2857   - /* PowerPC 401D2 */
2858   - {
2859   - .name = "401d2",
2860   - .pvr = CPU_PPC_401D2,
2861   - .pvr_mask = 0xFFFFFFFF,
2862   - .insns_flags = PPC_INSNS_401,
2863   - .flags = PPC_FLAGS_401,
2864   - .msr_mask = 0x000FD201,
2865   - },
2866   - /* PowerPC 401E2 */
2867   - {
2868   - .name = "401e2",
2869   - .pvr = CPU_PPC_401E2,
2870   - .pvr_mask = 0xFFFFFFFF,
2871   - .insns_flags = PPC_INSNS_401,
2872   - .flags = PPC_FLAGS_401,
2873   - .msr_mask = 0x000FD201,
2874   - },
2875   - /* PowerPC 401F2 */
2876   - {
2877   - .name = "401f2",
2878   - .pvr = CPU_PPC_401F2,
2879   - .pvr_mask = 0xFFFFFFFF,
2880   - .insns_flags = PPC_INSNS_401,
2881   - .flags = PPC_FLAGS_401,
2882   - .msr_mask = 0x000FD201,
2883   - },
2884   - /* PowerPC 401G2 */
2885   - {
2886   - .name = "401g2",
2887   - .pvr = CPU_PPC_401G2,
2888   - .pvr_mask = 0xFFFFFFFF,
2889   - .insns_flags = PPC_INSNS_401,
2890   - .flags = PPC_FLAGS_401,
2891   - .msr_mask = 0x000FD201,
2892   - },
  4071 + /* PowerPC 401B3 */
  4072 + POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
  4073 +#endif
  4074 + /* PowerPC 401C2 */
  4075 + POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
  4076 + /* PowerPC 401D2 */
  4077 + POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
  4078 + /* PowerPC 401E2 */
  4079 + POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
  4080 + /* PowerPC 401F2 */
  4081 + POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
  4082 + /* PowerPC 401G2 */
  4083 + /* XXX: to be checked */
  4084 + POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
  4085 + /* PowerPC 401 microcontrolers */
2893 4086 #if defined (TODO)
2894   - /* PowerPC 401G2 */
2895   - {
2896   - .name = "401gf",
2897   - .pvr = CPU_PPC_401GF,
2898   - .pvr_mask = 0xFFFFFFFF,
2899   - .insns_flags = PPC_INSNS_401,
2900   - .flags = PPC_FLAGS_401,
2901   - .msr_mask = 0x000FD201,
2902   - },
  4087 + /* PowerPC 401GF */
  4088 + POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
2903 4089 #endif
  4090 + /* IOP480 (401 microcontroler) */
  4091 + POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
  4092 + /* IBM Processor for Network Resources */
  4093 + POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
2904 4094 #if defined (TODO)
2905   - /* IOP480 (401 microcontroler) */
2906   - {
2907   - .name = "iop480",
2908   - .pvr = CPU_PPC_IOP480,
2909   - .pvr_mask = 0xFFFFFFFF,
2910   - .insns_flags = PPC_INSNS_401,
2911   - .flags = PPC_FLAGS_401,
2912   - .msr_mask = 0x000FD201,
2913   - },
  4095 + POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
2914 4096 #endif
  4097 + /* PowerPC 403 family */
  4098 + /* Generic PowerPC 403 */
  4099 + POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
  4100 + /* PowerPC 403 microcontrolers */
  4101 + /* PowerPC 403 GA */
  4102 + POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
  4103 + /* PowerPC 403 GB */
  4104 + POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
  4105 + /* PowerPC 403 GC */
  4106 + POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
  4107 + /* PowerPC 403 GCX */
  4108 + POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
2915 4109 #if defined (TODO)
2916   - /* IBM Processor for Network Resources */
2917   - {
2918   - .name = "Cobra",
2919   - .pvr = CPU_PPC_COBRA,
2920   - .pvr_mask = 0xFFFFFFFF,
2921   - .insns_flags = PPC_INSNS_401,
2922   - .flags = PPC_FLAGS_401,
2923   - .msr_mask = 0x000FD201,
2924   - },
  4110 + /* PowerPC 403 GP */
  4111 + POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
2925 4112 #endif
2926   - /* Generic PowerPC 403 */
2927   - {
2928   - .name = "403",
2929   - .pvr = CPU_PPC_403,
2930   - .pvr_mask = 0xFFFFFFFF,
2931   - .insns_flags = PPC_INSNS_403,
2932   - .flags = PPC_FLAGS_403,
2933   - .msr_mask = 0x000000000007D23DULL,
2934   - },
2935   - /* PowerPC 403 GA */
2936   - {
2937   - .name = "403ga",
2938   - .pvr = CPU_PPC_403GA,
2939   - .pvr_mask = 0xFFFFFFFF,
2940   - .insns_flags = PPC_INSNS_403,
2941   - .flags = PPC_FLAGS_403,
2942   - .msr_mask = 0x000000000007D23DULL,
2943   - },
2944   - /* PowerPC 403 GB */
2945   - {
2946   - .name = "403gb",
2947   - .pvr = CPU_PPC_403GB,
2948   - .pvr_mask = 0xFFFFFFFF,
2949   - .insns_flags = PPC_INSNS_403,
2950   - .flags = PPC_FLAGS_403,
2951   - .msr_mask = 0x000000000007D23DULL,
2952   - },
2953   - /* PowerPC 403 GC */
2954   - {
2955   - .name = "403gc",
2956   - .pvr = CPU_PPC_403GC,
2957   - .pvr_mask = 0xFFFFFFFF,
2958   - .insns_flags = PPC_INSNS_403,
2959   - .flags = PPC_FLAGS_403,
2960   - .msr_mask = 0x000000000007D23DULL,
2961   - },
2962   - /* PowerPC 403 GCX */
2963   - {
2964   - .name = "403gcx",
2965   - .pvr = CPU_PPC_403GCX,
2966   - .pvr_mask = 0xFFFFFFFF,
2967   - .insns_flags = PPC_INSNS_403,
2968   - .flags = PPC_FLAGS_403,
2969   - .msr_mask = 0x000000000007D23DULL,
2970   - },
  4113 + /* PowerPC 405 family */
  4114 + /* Generic PowerPC 405 */
  4115 + POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
  4116 + /* PowerPC 405 cores */
2971 4117 #if defined (TODO)
2972   - /* PowerPC 403 GP */
2973   - {
2974   - .name = "403gp",
2975   - .pvr = CPU_PPC_403GP,
2976   - .pvr_mask = 0xFFFFFFFF,
2977   - .insns_flags = PPC_INSNS_403,
2978   - .flags = PPC_FLAGS_403,
2979   - .msr_mask = 0x000000000007D23DULL,
2980   - },
  4118 + /* PowerPC 405 A3 */
  4119 + POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
2981 4120 #endif
2982   - /* Generic PowerPC 405 */
2983   - {
2984   - .name = "405",
2985   - .pvr = CPU_PPC_405,
2986   - .pvr_mask = 0xFFFFFFFF,
2987   - .insns_flags = PPC_INSNS_405,
2988   - .flags = PPC_FLAGS_405,
2989   - .msr_mask = 0x00000000020EFF30ULL,
2990   - },
2991 4121 #if defined (TODO)
2992   - /* PowerPC 405 A3 */
2993   - {
2994   - .name = "405a3",
2995   - .pvr = CPU_PPC_405A3,
2996   - .pvr_mask = 0xFFFFFFFF,
2997   - .insns_flags = PPC_INSNS_405,
2998   - .flags = PPC_FLAGS_405,
2999   - .msr_mask = 0x00000000020EFF30ULL,
3000   - },
  4122 + /* PowerPC 405 A4 */
  4123 + POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
3001 4124 #endif
3002 4125 #if defined (TODO)
3003   - /* PowerPC 405 A4 */
3004   - {
3005   - .name = "405a4",
3006   - .pvr = CPU_PPC_405A4,
3007   - .pvr_mask = 0xFFFFFFFF,
3008   - .insns_flags = PPC_INSNS_405,
3009   - .flags = PPC_FLAGS_405,
3010   - .msr_mask = 0x00000000020EFF30ULL,
3011   - },
  4126 + /* PowerPC 405 B3 */
  4127 + POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
3012 4128 #endif
3013 4129 #if defined (TODO)
3014   - /* PowerPC 405 B3 */
3015   - {
3016   - .name = "405b3",
3017   - .pvr = CPU_PPC_405B3,
3018   - .pvr_mask = 0xFFFFFFFF,
3019   - .insns_flags = PPC_INSNS_405,
3020   - .flags = PPC_FLAGS_405,
3021   - .msr_mask = 0x00000000020EFF30ULL,
3022   - },
3023   -#endif
3024   - /* PowerPC 405 D2 */
3025   - {
3026   - .name = "405d2",
3027   - .pvr = CPU_PPC_405D2,
3028   - .pvr_mask = 0xFFFFFFFF,
3029   - .insns_flags = PPC_INSNS_405,
3030   - .flags = PPC_FLAGS_405,
3031   - .msr_mask = 0x00000000020EFF30ULL,
3032   - },
3033   - /* PowerPC 405 D4 */
3034   - {
3035   - .name = "405d4",
3036   - .pvr = CPU_PPC_405D4,
3037   - .pvr_mask = 0xFFFFFFFF,
3038   - .insns_flags = PPC_INSNS_405,
3039   - .flags = PPC_FLAGS_405,
3040   - .msr_mask = 0x00000000020EFF30ULL,
3041   - },
3042   - /* PowerPC 405 CR */
3043   - {
3044   - .name = "405cr",
3045   - .pvr = CPU_PPC_405CR,
3046   - .pvr_mask = 0xFFFFFFFF,
3047   - .insns_flags = PPC_INSNS_405,
3048   - .flags = PPC_FLAGS_405,
3049   - .msr_mask = 0x00000000020EFF30ULL,
3050   - },
3051   - /* PowerPC 405 GP */
3052   - {
3053   - .name = "405gp",
3054   - .pvr = CPU_PPC_405GP,
3055   - .pvr_mask = 0xFFFFFFFF,
3056   - .insns_flags = PPC_INSNS_405,
3057   - .flags = PPC_FLAGS_405,
3058   - .msr_mask = 0x00000000020EFF30ULL,
3059   - },
3060   - /* PowerPC 405 EP */
3061   - {
3062   - .name = "405ep",
3063   - .pvr = CPU_PPC_405EP,
3064   - .pvr_mask = 0xFFFFFFFF,
3065   - .insns_flags = PPC_INSNS_405,
3066   - .flags = PPC_FLAGS_405,
3067   - .msr_mask = 0x00000000000ED630ULL,
3068   - },
  4130 + /* PowerPC 405 B4 */
  4131 + POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
  4132 +#endif
  4133 +#if defined (TODO)
  4134 + /* PowerPC 405 C3 */
  4135 + POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
  4136 +#endif
  4137 +#if defined (TODO)
  4138 + /* PowerPC 405 C4 */
  4139 + POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
  4140 +#endif
  4141 + /* PowerPC 405 D2 */
  4142 + POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
  4143 +#if defined (TODO)
  4144 + /* PowerPC 405 D3 */
  4145 + POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
  4146 +#endif
  4147 + /* PowerPC 405 D4 */
  4148 + POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
  4149 +#if defined (TODO)
  4150 + /* PowerPC 405 D5 */
  4151 + POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
  4152 +#endif
  4153 +#if defined (TODO)
  4154 + /* PowerPC 405 E4 */
  4155 + POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
  4156 +#endif
  4157 +#if defined (TODO)
  4158 + /* PowerPC 405 F4 */
  4159 + POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
  4160 +#endif
  4161 +#if defined (TODO)
  4162 + /* PowerPC 405 F5 */
  4163 + POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
  4164 +#endif
  4165 +#if defined (TODO)
  4166 + /* PowerPC 405 F6 */
  4167 + POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
  4168 +#endif
  4169 + /* PowerPC 405 microcontrolers */
  4170 + /* PowerPC 405 CR */
  4171 + POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
  4172 + /* PowerPC 405 CRa */
  4173 + POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
  4174 + /* PowerPC 405 CRb */
  4175 + POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
  4176 + /* PowerPC 405 CRc */
  4177 + POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
  4178 + /* PowerPC 405 EP */
  4179 + POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
  4180 +#if defined(TODO)
  4181 + /* PowerPC 405 EXr */
  4182 + POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
  4183 +#endif
  4184 + /* PowerPC 405 EZ */
  4185 + POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
  4186 +#if defined(TODO)
  4187 + /* PowerPC 405 FX */
  4188 + POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
  4189 +#endif
  4190 + /* PowerPC 405 GP */
  4191 + POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
  4192 + /* PowerPC 405 GPa */
  4193 + POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
  4194 + /* PowerPC 405 GPb */
  4195 + POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
  4196 + /* PowerPC 405 GPc */
  4197 + POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
  4198 + /* PowerPC 405 GPd */
  4199 + POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
  4200 + /* PowerPC 405 GPe */
  4201 + POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
  4202 + /* PowerPC 405 GPR */
  4203 + POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
  4204 +#if defined(TODO)
  4205 + /* PowerPC 405 H */
  4206 + POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
  4207 +#endif
  4208 +#if defined(TODO)
  4209 + /* PowerPC 405 L */
  4210 + POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
  4211 +#endif
  4212 + /* PowerPC 405 LP */
  4213 + POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
  4214 +#if defined(TODO)
  4215 + /* PowerPC 405 PM */
  4216 + POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
  4217 +#endif
  4218 +#if defined(TODO)
  4219 + /* PowerPC 405 PS */
  4220 + POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
  4221 +#endif
  4222 +#if defined(TODO)
  4223 + /* PowerPC 405 S */
  4224 + POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
  4225 +#endif
  4226 + /* Npe405 H */
  4227 + POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
  4228 + /* Npe405 H2 */
  4229 + POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
  4230 + /* Npe405 L */
  4231 + POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
  4232 + /* Npe4GS3 */
  4233 + POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
  4234 +#if defined (TODO)
  4235 + POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
  4236 +#endif
  4237 +#if defined (TODO)
  4238 + POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
  4239 +#endif
  4240 +#if defined (TODO)
  4241 + /* PowerPC LC77700 (Sanyo) */
  4242 + POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
  4243 +#endif
  4244 + /* PowerPC 401/403/405 based set-top-box microcontrolers */
  4245 +#if defined (TODO)
  4246 + /* STB010000 */
  4247 + POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
  4248 +#endif
  4249 +#if defined (TODO)
  4250 + /* STB01010 */
  4251 + POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
  4252 +#endif
  4253 +#if defined (TODO)
  4254 + /* STB0210 */
  4255 + POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
  4256 +#endif
  4257 + /* STB03xx */
  4258 + POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
  4259 +#if defined (TODO)
  4260 + /* STB043x */
  4261 + POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
  4262 +#endif
  4263 +#if defined (TODO)
  4264 + /* STB045x */
  4265 + POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
  4266 +#endif
  4267 + /* STB04xx */
  4268 + POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
  4269 + /* STB25xx */
  4270 + POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
  4271 +#if defined (TODO)
  4272 + /* STB130 */
  4273 + POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
  4274 +#endif
  4275 + /* Xilinx PowerPC 405 cores */
  4276 + POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
  4277 + POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
  4278 + POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
  4279 + POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
  4280 +#if defined (TODO)
  4281 + /* Zarlink ZL10310 */
  4282 + POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
  4283 +#endif
  4284 +#if defined (TODO)
  4285 + /* Zarlink ZL10311 */
  4286 + POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
  4287 +#endif
  4288 +#if defined (TODO)
  4289 + /* Zarlink ZL10320 */
  4290 + POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
  4291 +#endif
  4292 +#if defined (TODO)
  4293 + /* Zarlink ZL10321 */
  4294 + POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
  4295 +#endif
  4296 + /* PowerPC 440 family */
  4297 + /* Generic PowerPC 440 */
  4298 + POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
  4299 + /* PowerPC 440 cores */
  4300 +#if defined (TODO)
  4301 + /* PowerPC 440 A4 */
  4302 + POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
  4303 +#endif
  4304 +#if defined (TODO)
  4305 + /* PowerPC 440 A5 */
  4306 + POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
  4307 +#endif
  4308 +#if defined (TODO)
  4309 + /* PowerPC 440 B4 */
  4310 + POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
  4311 +#endif
  4312 +#if defined (TODO)
  4313 + /* PowerPC 440 G4 */
  4314 + POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
  4315 +#endif
  4316 +#if defined (TODO)
  4317 + /* PowerPC 440 F5 */
  4318 + POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
  4319 +#endif
  4320 +#if defined (TODO)
  4321 + /* PowerPC 440 G5 */
  4322 + POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
  4323 +#endif
  4324 +#if defined (TODO)
  4325 + /* PowerPC 440H4 */
  4326 + POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
  4327 +#endif
  4328 +#if defined (TODO)
  4329 + /* PowerPC 440H6 */
  4330 + POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
  4331 +#endif
  4332 + /* PowerPC 440 microcontrolers */
  4333 + /* PowerPC 440 EP */
  4334 + POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
  4335 + /* PowerPC 440 EPa */
  4336 + POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
  4337 + /* PowerPC 440 EPb */
  4338 + POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
  4339 + /* PowerPC 440 EPX */
  4340 + POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
  4341 + /* PowerPC 440 GP */
  4342 + POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
  4343 + /* PowerPC 440 GPb */
  4344 + POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
  4345 + /* PowerPC 440 GPc */
  4346 + POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
  4347 + /* PowerPC 440 GR */
  4348 + POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
  4349 + /* PowerPC 440 GRa */
  4350 + POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
  4351 + /* PowerPC 440 GRX */
  4352 + POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
  4353 + /* PowerPC 440 GX */
  4354 + POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
  4355 + /* PowerPC 440 GXa */
  4356 + POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
  4357 + /* PowerPC 440 GXb */
  4358 + POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
  4359 + /* PowerPC 440 GXc */
  4360 + POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
  4361 + /* PowerPC 440 GXf */
  4362 + POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
  4363 +#if defined(TODO)
  4364 + /* PowerPC 440 S */
  4365 + POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
  4366 +#endif
  4367 + /* PowerPC 440 SP */
  4368 + POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
  4369 + /* PowerPC 440 SP2 */
  4370 + POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
  4371 + /* PowerPC 440 SPE */
  4372 + POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
  4373 + /* PowerPC 460 family */
  4374 +#if defined (TODO)
  4375 + /* Generic PowerPC 464 */
  4376 + POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
  4377 +#endif
  4378 + /* PowerPC 464 microcontrolers */
  4379 +#if defined (TODO)
  4380 + /* PowerPC 464H90 */
  4381 + POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
  4382 +#endif
  4383 +#if defined (TODO)
  4384 + /* PowerPC 464H90F */
  4385 + POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
  4386 +#endif
  4387 + /* Freescale embedded PowerPC cores */
  4388 + /* e200 family */
  4389 +#if defined (TODO)
  4390 + /* Generic PowerPC e200 core */
  4391 + POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
  4392 +#endif
  4393 +#if defined (TODO)
  4394 + /* PowerPC e200z5 core */
  4395 + POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
  4396 +#endif
  4397 +#if defined (TODO)
  4398 + /* PowerPC e200z6 core */
  4399 + POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
  4400 +#endif
  4401 + /* e300 family */
  4402 +#if defined (TODO)
  4403 + /* Generic PowerPC e300 core */
  4404 + POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
  4405 +#endif
  4406 +#if defined (TODO)
  4407 + /* PowerPC e300c1 core */
  4408 + POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
  4409 +#endif
  4410 +#if defined (TODO)
  4411 + /* PowerPC e300c2 core */
  4412 + POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
  4413 +#endif
  4414 +#if defined (TODO)
  4415 + /* PowerPC e300c3 core */
  4416 + POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
  4417 +#endif
  4418 + /* e500 family */
  4419 +#if defined (TODO)
  4420 + /* PowerPC e500 core */
  4421 + POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
  4422 +#endif
  4423 +#if defined (TODO)
  4424 + /* PowerPC e500 v1.1 core */
  4425 + POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
  4426 +#endif
  4427 +#if defined (TODO)
  4428 + /* PowerPC e500 v1.2 core */
  4429 + POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
  4430 +#endif
  4431 +#if defined (TODO)
  4432 + /* PowerPC e500 v2.1 core */
  4433 + POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
  4434 +#endif
  4435 +#if defined (TODO)
  4436 + /* PowerPC e500 v2.2 core */
  4437 + POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
  4438 +#endif
  4439 + /* e600 family */
  4440 +#if defined (TODO)
  4441 + /* PowerPC e600 core */
  4442 + POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
  4443 +#endif
  4444 + /* PowerPC MPC 5xx cores */
  4445 +#if defined (TODO)
  4446 + /* PowerPC MPC 5xx */
  4447 + POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
  4448 +#endif
  4449 + /* PowerPC MPC 8xx cores */
  4450 +#if defined (TODO)
  4451 + /* PowerPC MPC 8xx */
  4452 + POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
  4453 +#endif
  4454 + /* PowerPC MPC 8xxx cores */
  4455 +#if defined (TODO)
  4456 + /* PowerPC MPC 82xx HIP3 */
  4457 + POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
  4458 +#endif
  4459 +#if defined (TODO)
  4460 + /* PowerPC MPC 82xx HIP4 */
  4461 + POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
  4462 +#endif
  4463 +#if defined (TODO)
  4464 + /* PowerPC MPC 827x */
  4465 + POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
  4466 +#endif
  4467 +
  4468 + /* 32 bits "classic" PowerPC */
  4469 + /* PowerPC 6xx family */
  4470 + /* PowerPC 601 */
  4471 + POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
  4472 + /* PowerPC 601v2 */
  4473 + POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
  4474 + /* PowerPC 602 */
  4475 + POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
  4476 + /* PowerPC 603 */
  4477 + POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
  4478 + /* Code name for PowerPC 603 */
  4479 + POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
  4480 + /* PowerPC 603e */
  4481 + POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
  4482 + /* Code name for PowerPC 603e */
  4483 + POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
  4484 + /* PowerPC 603e v1.1 */
  4485 + POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
  4486 + /* PowerPC 603e v1.2 */
  4487 + POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
  4488 + /* PowerPC 603e v1.3 */
  4489 + POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
  4490 + /* PowerPC 603e v1.4 */
  4491 + POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
  4492 + /* PowerPC 603e v2.2 */
  4493 + POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
  4494 + /* PowerPC 603e v3 */
  4495 + POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
  4496 + /* PowerPC 603e v4 */
  4497 + POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
  4498 + /* PowerPC 603e v4.1 */
  4499 + POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
  4500 + /* PowerPC 603e */
  4501 + POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
  4502 + /* PowerPC 603e7t */
  4503 + POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
  4504 + /* PowerPC 603e7v */
  4505 + POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
  4506 + /* Code name for PowerPC 603ev */
  4507 + POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
  4508 + /* PowerPC 603e7v1 */
  4509 + POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
  4510 + /* PowerPC 603e7v2 */
  4511 + POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
  4512 + /* PowerPC 603p */
  4513 + /* to be checked */
  4514 + POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
  4515 + /* PowerPC 603r */
  4516 + POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
  4517 + /* Code name for PowerPC 603r */
  4518 + POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
  4519 + /* PowerPC G2 core */
  4520 + POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
  4521 + /* PowerPC G2 H4 */
  4522 + POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
  4523 + /* PowerPC G2 GP */
  4524 + POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
  4525 + /* PowerPC G2 LS */
  4526 + POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
  4527 + /* PowerPC G2LE */
  4528 + /* Same as G2, with little-endian mode support */
  4529 + POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
  4530 + /* PowerPC G2LE GP */
  4531 + POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
  4532 + /* PowerPC G2LE LS */
  4533 + POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
  4534 + /* PowerPC 604 */
  4535 + POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
  4536 + /* PowerPC 604e */
  4537 + POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
  4538 + /* PowerPC 604e v1.0 */
  4539 + POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
  4540 + /* PowerPC 604e v2.2 */
  4541 + POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
  4542 + /* PowerPC 604e v2.4 */
  4543 + POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
  4544 + /* PowerPC 604r */
  4545 + POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
  4546 +#if defined(TODO)
  4547 + /* PowerPC 604ev */
  4548 + POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
  4549 +#endif
  4550 + /* PowerPC 7xx family */
  4551 + /* Generic PowerPC 740 (G3) */
  4552 + POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
  4553 + /* Generic PowerPC 750 (G3) */
  4554 + POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
  4555 + /* Code name for generic PowerPC 740/750 (G3) */
  4556 + POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
  4557 + /* PowerPC 740/750 is also known as G3 */
  4558 + POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
  4559 + /* PowerPC 740 v2.0 (G3) */
  4560 + POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
  4561 + /* PowerPC 750 v2.0 (G3) */
  4562 + POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
  4563 + /* PowerPC 740 v2.1 (G3) */
  4564 + POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
  4565 + /* PowerPC 750 v2.1 (G3) */
  4566 + POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
  4567 + /* PowerPC 740 v2.2 (G3) */
  4568 + POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
  4569 + /* PowerPC 750 v2.2 (G3) */
  4570 + POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
  4571 + /* PowerPC 740 v3.0 (G3) */
  4572 + POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
  4573 + /* PowerPC 750 v3.0 (G3) */
  4574 + POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
  4575 + /* PowerPC 740 v3.1 (G3) */
  4576 + POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
  4577 + /* PowerPC 750 v3.1 (G3) */
  4578 + POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
  4579 + /* PowerPC 740E (G3) */
  4580 + POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
  4581 + /* PowerPC 740P (G3) */
  4582 + POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
  4583 + /* PowerPC 750P (G3) */
  4584 + POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
  4585 + /* Code name for PowerPC 740P/750P (G3) */
  4586 + POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
  4587 + /* PowerPC 750CL (G3 embedded) */
  4588 + POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
  4589 + /* PowerPC 750CX (G3 embedded) */
  4590 + POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
  4591 + /* PowerPC 750CX v2.1 (G3 embedded) */
  4592 + POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
  4593 + /* PowerPC 750CX v2.2 (G3 embedded) */
  4594 + POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
  4595 + /* PowerPC 750CXe (G3 embedded) */
  4596 + POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
  4597 + /* PowerPC 750CXe v2.1 (G3 embedded) */
  4598 + POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
  4599 + /* PowerPC 750CXe v2.2 (G3 embedded) */
  4600 + POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
  4601 + /* PowerPC 750CXe v2.3 (G3 embedded) */
  4602 + POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
  4603 + /* PowerPC 750CXe v2.4 (G3 embedded) */
  4604 + POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
  4605 + /* PowerPC 750CXe v2.4b (G3 embedded) */
  4606 + POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
  4607 + /* PowerPC 750CXe v3.1 (G3 embedded) */
  4608 + POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
  4609 + /* PowerPC 750CXe v3.1b (G3 embedded) */
  4610 + POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
  4611 + /* PowerPC 750CXr (G3 embedded) */
  4612 + POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
  4613 + /* PowerPC 750E (G3) */
  4614 + POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
  4615 + /* PowerPC 750FL (G3 embedded) */
  4616 + POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 7x0),
  4617 + /* PowerPC 750FX (G3 embedded) */
  4618 + POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
  4619 + /* PowerPC 750FX v1.0 (G3 embedded) */
  4620 + POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
  4621 + /* PowerPC 750FX v2.0 (G3 embedded) */
  4622 + POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
  4623 + /* PowerPC 750FX v2.1 (G3 embedded) */
  4624 + POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
  4625 + /* PowerPC 750FX v2.2 (G3 embedded) */
  4626 + POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
  4627 + /* PowerPC 750FX v2.3 (G3 embedded) */
  4628 + POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
  4629 + /* PowerPC 750GL (G3 embedded) */
  4630 + POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 7x0),
  4631 + /* PowerPC 750GX (G3 embedded) */
  4632 + POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
  4633 + /* PowerPC 750GX v1.0 (G3 embedded) */
  4634 + POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
  4635 + /* PowerPC 750GX v1.1 (G3 embedded) */
  4636 + POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
  4637 + /* PowerPC 750GX v1.2 (G3 embedded) */
  4638 + POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
  4639 + /* PowerPC 750L (G3 embedded) */
  4640 + POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
  4641 + /* Code name for PowerPC 750L (G3 embedded) */
  4642 + POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
  4643 + /* PowerPC 750L v2.2 (G3 embedded) */
  4644 + POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
  4645 + /* PowerPC 750L v3.0 (G3 embedded) */
  4646 + POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
  4647 + /* PowerPC 750L v3.2 (G3 embedded) */
  4648 + POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
  4649 + /* Generic PowerPC 745 */
  4650 + POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
  4651 + /* Generic PowerPC 755 */
  4652 + POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
  4653 + /* Code name for PowerPC 745/755 */
  4654 + POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
  4655 + /* PowerPC 745 v1.0 */
  4656 + POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
  4657 + /* PowerPC 755 v1.0 */
  4658 + POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
  4659 + /* PowerPC 745 v1.1 */
  4660 + POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
  4661 + /* PowerPC 755 v1.1 */
  4662 + POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
  4663 + /* PowerPC 745 v2.0 */
  4664 + POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
  4665 + /* PowerPC 755 v2.0 */
  4666 + POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
  4667 + /* PowerPC 745 v2.1 */
  4668 + POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
  4669 + /* PowerPC 755 v2.1 */
  4670 + POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
  4671 + /* PowerPC 745 v2.2 */
  4672 + POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
  4673 + /* PowerPC 755 v2.2 */
  4674 + POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
  4675 + /* PowerPC 745 v2.3 */
  4676 + POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
  4677 + /* PowerPC 755 v2.3 */
  4678 + POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
  4679 + /* PowerPC 745 v2.4 */
  4680 + POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
  4681 + /* PowerPC 755 v2.4 */
  4682 + POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
  4683 + /* PowerPC 745 v2.5 */
  4684 + POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
  4685 + /* PowerPC 755 v2.5 */
  4686 + POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
  4687 + /* PowerPC 745 v2.6 */
  4688 + POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
  4689 + /* PowerPC 755 v2.6 */
  4690 + POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
  4691 + /* PowerPC 745 v2.7 */
  4692 + POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
  4693 + /* PowerPC 755 v2.7 */
  4694 + POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
  4695 + /* PowerPC 745 v2.8 */
  4696 + POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
  4697 + /* PowerPC 755 v2.8 */
  4698 + POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
  4699 +#if defined (TODO)
  4700 + /* PowerPC 745P (G3) */
  4701 + POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
  4702 + /* PowerPC 755P (G3) */
  4703 + POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
  4704 +#endif
  4705 + /* PowerPC 74xx family */
  4706 + /* PowerPC 7400 (G4) */
  4707 + POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
  4708 + /* Code name for PowerPC 7400 */
  4709 + POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
  4710 + /* PowerPC 74xx is also well known as G4 */
  4711 + POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
  4712 + /* PowerPC 7400 v1.0 (G4) */
  4713 + POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
  4714 + /* PowerPC 7400 v1.1 (G4) */
  4715 + POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
  4716 + /* PowerPC 7400 v2.0 (G4) */
  4717 + POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
  4718 + /* PowerPC 7400 v2.2 (G4) */
  4719 + POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
  4720 + /* PowerPC 7400 v2.6 (G4) */
  4721 + POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
  4722 + /* PowerPC 7400 v2.7 (G4) */
  4723 + POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
  4724 + /* PowerPC 7400 v2.8 (G4) */
  4725 + POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
  4726 + /* PowerPC 7400 v2.9 (G4) */
  4727 + POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
  4728 + /* PowerPC 7410 (G4) */
  4729 + POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
  4730 + /* Code name for PowerPC 7410 */
  4731 + POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
  4732 + /* PowerPC 7410 v1.0 (G4) */
  4733 + POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
  4734 + /* PowerPC 7410 v1.1 (G4) */
  4735 + POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
  4736 + /* PowerPC 7410 v1.2 (G4) */
  4737 + POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
  4738 + /* PowerPC 7410 v1.3 (G4) */
  4739 + POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
  4740 + /* PowerPC 7410 v1.4 (G4) */
  4741 + POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
  4742 + /* PowerPC 7448 (G4) */
  4743 + POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
  4744 + /* PowerPC 7448 v1.0 (G4) */
  4745 + POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
  4746 + /* PowerPC 7448 v1.1 (G4) */
  4747 + POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
  4748 + /* PowerPC 7448 v2.0 (G4) */
  4749 + POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
  4750 + /* PowerPC 7448 v2.1 (G4) */
  4751 + POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
  4752 +#if defined (TODO)
  4753 + /* PowerPC 7450 (G4) */
  4754 + POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
  4755 + /* Code name for PowerPC 7450 */
  4756 + POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
  4757 +#endif
  4758 +#if defined (TODO)
  4759 + /* PowerPC 7450 v1.0 (G4) */
  4760 + POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
  4761 +#endif
  4762 +#if defined (TODO)
  4763 + /* PowerPC 7450 v1.1 (G4) */
  4764 + POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
  4765 +#endif
  4766 +#if defined (TODO)
  4767 + /* PowerPC 7450 v1.2 (G4) */
  4768 + POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
  4769 +#endif
  4770 +#if defined (TODO)
  4771 + /* PowerPC 7450 v2.0 (G4) */
  4772 + POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
  4773 +#endif
  4774 +#if defined (TODO)
  4775 + /* PowerPC 7450 v2.1 (G4) */
  4776 + POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
  4777 +#endif
  4778 +#if defined (TODO)
  4779 + /* PowerPC 7441 (G4) */
  4780 + POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
  4781 + /* PowerPC 7451 (G4) */
  4782 + POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
  4783 +#endif
3069 4784 #if defined (TODO)
3070   - /* PowerPC 405 EZ */
3071   - {
3072   - .name = "405ez",
3073   - .pvr = CPU_PPC_405EZ,
3074   - .pvr_mask = 0xFFFFFFFF,
3075   - .insns_flags = PPC_INSNS_405,
3076   - .flags = PPC_FLAGS_405,
3077   - .msr_mask = 0x00000000020EFF30ULL,
3078   - },
  4785 + /* PowerPC 7441g (G4) */
  4786 + POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
  4787 + /* PowerPC 7451g (G4) */
  4788 + POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
3079 4789 #endif
3080 4790 #if defined (TODO)
3081   - /* PowerPC 405 GPR */
3082   - {
3083   - .name = "405gpr",
3084   - .pvr = CPU_PPC_405GPR,
3085   - .pvr_mask = 0xFFFFFFFF,
3086   - .insns_flags = PPC_INSNS_405,
3087   - .flags = PPC_FLAGS_405,
3088   - .msr_mask = 0x00000000020EFF30ULL,
3089   - },
  4791 + /* PowerPC 7445 (G4) */
  4792 + POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
  4793 + /* PowerPC 7455 (G4) */
  4794 + POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
  4795 + /* Code name for PowerPC 7445/7455 */
  4796 + POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
3090 4797 #endif
3091 4798 #if defined (TODO)
3092   - /* PowerPC 405 LP */
3093   - {
3094   - .name = "405lp",
3095   - .pvr = CPU_PPC_405EZ,
3096   - .pvr_mask = 0xFFFFFFFF,
3097   - .insns_flags = PPC_INSNS_405,
3098   - .flags = PPC_FLAGS_405,
3099   - .msr_mask = 0x00000000020EFF30ULL,
3100   - },
3101   -#endif
3102   - /* Npe405 H */
3103   - {
3104   - .name = "Npe405H",
3105   - .pvr = CPU_PPC_NPE405H,
3106   - .pvr_mask = 0xFFFFFFFF,
3107   - .insns_flags = PPC_INSNS_405,
3108   - .flags = PPC_FLAGS_405,
3109   - .msr_mask = 0x00000000020EFF30ULL,
3110   - },
3111   - /* Npe405 H2 */
3112   - {
3113   - .name = "Npe405H2",
3114   - .pvr = CPU_PPC_NPE405H2,
3115   - .pvr_mask = 0xFFFFFFFF,
3116   - .insns_flags = PPC_INSNS_405,
3117   - .flags = PPC_FLAGS_405,
3118   - .msr_mask = 0x00000000020EFF30ULL,
3119   - },
3120   - /* Npe405 L */
3121   - {
3122   - .name = "Npe405L",
3123   - .pvr = CPU_PPC_NPE405L,
3124   - .pvr_mask = 0xFFFFFFFF,
3125   - .insns_flags = PPC_INSNS_405,
3126   - .flags = PPC_FLAGS_405,
3127   - .msr_mask = 0x00000000020EFF30ULL,
3128   - },
  4799 + /* PowerPC 7445 v1.0 (G4) */
  4800 + POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
  4801 + /* PowerPC 7455 v1.0 (G4) */
  4802 + POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
  4803 +#endif
3129 4804 #if defined (TODO)
3130   - /* PowerPC LP777000 */
3131   - {
3132   - .name = "lp777000",
3133   - .pvr = CPU_PPC_LP777000,
3134   - .pvr_mask = 0xFFFFFFFF,
3135   - .insns_flags = PPC_INSNS_405,
3136   - .flags = PPC_FLAGS_405,
3137   - .msr_mask = 0x00000000020EFF30ULL,
3138   - },
  4805 + /* PowerPC 7445 v2.1 (G4) */
  4806 + POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
  4807 + /* PowerPC 7455 v2.1 (G4) */
  4808 + POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
3139 4809 #endif
3140 4810 #if defined (TODO)
3141   - /* STB010000 */
3142   - {
3143   - .name = "STB01000",
3144   - .pvr = CPU_PPC_STB01000,
3145   - .pvr_mask = 0xFFFFFFFF,
3146   - .insns_flags = PPC_INSNS_405,
3147   - .flags = PPC_FLAGS_405,
3148   - .msr_mask = 0x00000000020EFF30ULL,
3149   - },
  4811 + /* PowerPC 7445 v3.2 (G4) */
  4812 + POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
  4813 + /* PowerPC 7455 v3.2 (G4) */
  4814 + POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
3150 4815 #endif
3151 4816 #if defined (TODO)
3152   - /* STB01010 */
3153   - {
3154   - .name = "STB01010",
3155   - .pvr = CPU_PPC_STB01010,
3156   - .pvr_mask = 0xFFFFFFFF,
3157   - .insns_flags = PPC_INSNS_405,
3158   - .flags = PPC_FLAGS_405,
3159   - .msr_mask = 0x00000000020EFF30ULL,
3160   - },
  4817 + /* PowerPC 7445 v3.3 (G4) */
  4818 + POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
  4819 + /* PowerPC 7455 v3.3 (G4) */
  4820 + POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
3161 4821 #endif
3162 4822 #if defined (TODO)
3163   - /* STB0210 */
3164   - {
3165   - .name = "STB0210",
3166   - .pvr = CPU_PPC_STB0210,
3167   - .pvr_mask = 0xFFFFFFFF,
3168   - .insns_flags = PPC_INSNS_405,
3169   - .flags = PPC_FLAGS_405,
3170   - .msr_mask = 0x00000000020EFF30ULL,
3171   - },
  4823 + /* PowerPC 7445 v3.4 (G4) */
  4824 + POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
  4825 + /* PowerPC 7455 v3.4 (G4) */
  4826 + POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
3172 4827 #endif
3173 4828 #if defined (TODO)
3174   - /* STB03xx */
3175   - {
3176   - .name = "STB03",
3177   - .pvr = CPU_PPC_STB03,
3178   - .pvr_mask = 0xFFFFFFFF,
3179   - .insns_flags = PPC_INSNS_405,
3180   - .flags = PPC_FLAGS_405,
3181   - .msr_mask = 0x00000000020EFF30ULL,
3182   - },
  4829 + /* PowerPC 7447 (G4) */
  4830 + POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
  4831 + /* PowerPC 7457 (G4) */
  4832 + POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
  4833 + /* Code name for PowerPC 7447/7457 */
  4834 + POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
3183 4835 #endif
3184 4836 #if defined (TODO)
3185   - /* STB043x */
3186   - {
3187   - .name = "STB043",
3188   - .pvr = CPU_PPC_STB043,
3189   - .pvr_mask = 0xFFFFFFFF,
3190   - .insns_flags = PPC_INSNS_405,
3191   - .flags = PPC_FLAGS_405,
3192   - .msr_mask = 0x00000000020EFF30ULL,
3193   - },
  4837 + /* PowerPC 7447 v1.0 (G4) */
  4838 + POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
  4839 + /* PowerPC 7457 v1.0 (G4) */
  4840 + POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
  4841 + /* Code name for PowerPC 7447A/7457A */
  4842 + POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
3194 4843 #endif
3195 4844 #if defined (TODO)
3196   - /* STB045x */
3197   - {
3198   - .name = "STB045",
3199   - .pvr = CPU_PPC_STB045,
3200   - .pvr_mask = 0xFFFFFFFF,
3201   - .insns_flags = PPC_INSNS_405,
3202   - .flags = PPC_FLAGS_405,
3203   - .msr_mask = 0x00000000020EFF30ULL,
3204   - },
3205   -#endif
3206   -#if defined (TODO) || 1
3207   - /* STB25xx */
3208   - {
3209   - .name = "STB25",
3210   - .pvr = CPU_PPC_STB25,
3211   - .pvr_mask = 0xFFFFFFFF,
3212   - .insns_flags = PPC_INSNS_405,
3213   - .flags = PPC_FLAGS_405,
3214   - .msr_mask = 0x00000000020EFF30ULL,
3215   - },
  4845 + /* PowerPC 7447 v1.1 (G4) */
  4846 + POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
  4847 + /* PowerPC 7457 v1.1 (G4) */
  4848 + POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
3216 4849 #endif
3217 4850 #if defined (TODO)
3218   - /* STB130 */
3219   - {
3220   - .name = "STB130",
3221   - .pvr = CPU_PPC_STB130,
3222   - .pvr_mask = 0xFFFFFFFF,
3223   - .insns_flags = PPC_INSNS_405,
3224   - .flags = PPC_FLAGS_405,
3225   - .msr_mask = 0x00000000020EFF30ULL,
3226   - },
3227   -#endif
3228   - /* Xilinx PowerPC 405 cores */
  4851 + /* PowerPC 7447 v1.2 (G4) */
  4852 + POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
  4853 + /* PowerPC 7457 v1.2 (G4) */
  4854 + POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
  4855 +#endif
  4856 + /* 64 bits PowerPC */
  4857 +#if defined (TARGET_PPC64)
3229 4858 #if defined (TODO)
3230   - {
3231   - .name = "x2vp4",
3232   - .pvr = CPU_PPC_X2VP4,
3233   - .pvr_mask = 0xFFFFFFFF,
3234   - .insns_flags = PPC_INSNS_405,
3235   - .flags = PPC_FLAGS_405,
3236   - .msr_mask = 0x00000000020EFF30ULL,
3237   - },
3238   - {
3239   - .name = "x2vp7",
3240   - .pvr = CPU_PPC_X2VP7,
3241   - .pvr_mask = 0xFFFFFFFF,
3242   - .insns_flags = PPC_INSNS_405,
3243   - .flags = PPC_FLAGS_405,
3244   - .msr_mask = 0x00000000020EFF30ULL,
3245   - },
3246   - {
3247   - .name = "x2vp20",
3248   - .pvr = CPU_PPC_X2VP20,
3249   - .pvr_mask = 0xFFFFFFFF,
3250   - .insns_flags = PPC_INSNS_405,
3251   - .flags = PPC_FLAGS_405,
3252   - .msr_mask = 0x00000000020EFF30ULL,
3253   - },
3254   - {
3255   - .name = "x2vp50",
3256   - .pvr = CPU_PPC_X2VP50,
3257   - .pvr_mask = 0xFFFFFFFF,
3258   - .insns_flags = PPC_INSNS_405,
3259   - .flags = PPC_FLAGS_405,
3260   - .msr_mask = 0x00000000020EFF30ULL,
3261   - },
3262   -#endif
3263   - /* PowerPC 440 EP */
3264   - {
3265   - .name = "440ep",
3266   - .pvr = CPU_PPC_440EP,
3267   - .pvr_mask = 0xFFFFFFFF,
3268   - .insns_flags = PPC_INSNS_440,
3269   - .flags = PPC_FLAGS_440,
3270   - .msr_mask = 0x000000000006D630ULL,
3271   - },
3272   - /* PowerPC 440 GR */
3273   - {
3274   - .name = "440gr",
3275   - .pvr = CPU_PPC_440GR,
3276   - .pvr_mask = 0xFFFFFFFF,
3277   - .insns_flags = PPC_INSNS_440,
3278   - .flags = PPC_FLAGS_440,
3279   - .msr_mask = 0x000000000006D630ULL,
3280   - },
3281   - /* PowerPC 440 GP */
3282   - {
3283   - .name = "440gp",
3284   - .pvr = CPU_PPC_440GP,
3285   - .pvr_mask = 0xFFFFFFFF,
3286   - .insns_flags = PPC_INSNS_440,
3287   - .flags = PPC_FLAGS_440,
3288   - .msr_mask = 0x000000000006D630ULL,
3289   - },
  4859 + /* PowerPC 620 */
  4860 + POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
  4861 +#endif
3290 4862 #if defined (TODO)
3291   - /* PowerPC 440 GRX */
3292   - {
3293   - .name = "440grx",
3294   - .pvr = CPU_PPC_440GRX,
3295   - .pvr_mask = 0xFFFFFFFF,
3296   - .insns_flags = PPC_INSNS_440,
3297   - .flags = PPC_FLAGS_440,
3298   - .msr_mask = 0x000000000006D630ULL,
3299   - },
3300   -#endif
3301   - /* PowerPC 440 GX */
3302   - {
3303   - .name = "440gx",
3304   - .pvr = CPU_PPC_440GX,
3305   - .pvr_mask = 0xFFFFFFFF,
3306   - .insns_flags = PPC_INSNS_440,
3307   - .flags = PPC_FLAGS_440,
3308   - .msr_mask = 0x000000000006D630ULL,
3309   - },
3310   - /* PowerPC 440 GXc */
3311   - {
3312   - .name = "440gxc",
3313   - .pvr = CPU_PPC_440GXc,
3314   - .pvr_mask = 0xFFFFFFFF,
3315   - .insns_flags = PPC_INSNS_440,
3316   - .flags = PPC_FLAGS_440,
3317   - .msr_mask = 0x000000000006D630ULL,
3318   - },
3319   - /* PowerPC 440 GXf */
3320   - {
3321   - .name = "440gxf",
3322   - .pvr = CPU_PPC_440GXf,
3323   - .pvr_mask = 0xFFFFFFFF,
3324   - .insns_flags = PPC_INSNS_440,
3325   - .flags = PPC_FLAGS_440,
3326   - .msr_mask = 0x000000000006D630ULL,
3327   - },
3328   - /* PowerPC 440 SP */
3329   - {
3330   - .name = "440sp",
3331   - .pvr = CPU_PPC_440SP,
3332   - .pvr_mask = 0xFFFFFFFF,
3333   - .insns_flags = PPC_INSNS_440,
3334   - .flags = PPC_FLAGS_440,
3335   - .msr_mask = 0x000000000006D630ULL,
3336   - },
3337   - /* PowerPC 440 SP2 */
3338   - {
3339   - .name = "440sp2",
3340   - .pvr = CPU_PPC_440SP2,
3341   - .pvr_mask = 0xFFFFFFFF,
3342   - .insns_flags = PPC_INSNS_440,
3343   - .flags = PPC_FLAGS_440,
3344   - .msr_mask = 0x000000000006D630ULL,
3345   - },
3346   - /* PowerPC 440 SPE */
3347   - {
3348   - .name = "440spe",
3349   - .pvr = CPU_PPC_440SPE,
3350   - .pvr_mask = 0xFFFFFFFF,
3351   - .insns_flags = PPC_INSNS_440,
3352   - .flags = PPC_FLAGS_440,
3353   - .msr_mask = 0x000000000006D630ULL,
3354   - },
3355   - /* Fake generic BookE PowerPC */
3356   - {
3357   - .name = "BookE",
3358   - .pvr = CPU_PPC_e500,
3359   - .pvr_mask = 0xFFFFFFFF,
3360   - .insns_flags = PPC_INSNS_BOOKE,
3361   - .flags = PPC_FLAGS_BOOKE,
3362   - .msr_mask = 0x000000000006D630ULL,
3363   - },
3364   - /* PowerPC 460 cores - TODO */
3365   - /* PowerPC MPC 5xx cores - TODO */
3366   - /* PowerPC MPC 8xx cores - TODO */
3367   - /* PowerPC MPC 8xxx cores - TODO */
3368   - /* e200 cores - TODO */
3369   - /* e500 cores - TODO */
3370   - /* e600 cores - TODO */
3371   -
3372   - /* 32 bits "classic" PowerPC */
  4863 + /* PowerPC 630 (POWER3) */
  4864 + POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
  4865 + POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
  4866 +#endif
3373 4867 #if defined (TODO)
3374   - /* PowerPC 601 */
3375   - {
3376   - .name = "601",
3377   - .pvr = CPU_PPC_601,
3378   - .pvr_mask = 0xFFFFFFFF,
3379   - .insns_flags = PPC_INSNS_601,
3380   - .flags = PPC_FLAGS_601,
3381   - .msr_mask = 0x000000000000FD70ULL,
3382   - },
  4868 + /* PowerPC 631 (Power 3+) */
  4869 + POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
  4870 + POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
3383 4871 #endif
3384 4872 #if defined (TODO)
3385   - /* PowerPC 602 */
3386   - {
3387   - .name = "602",
3388   - .pvr = CPU_PPC_602,
3389   - .pvr_mask = 0xFFFFFFFF,
3390   - .insns_flags = PPC_INSNS_602,
3391   - .flags = PPC_FLAGS_602,
3392   - .msr_mask = 0x0000000000C7FF73ULL,
3393   - },
3394   -#endif
3395   - /* PowerPC 603 */
3396   - {
3397   - .name = "603",
3398   - .pvr = CPU_PPC_603,
3399   - .pvr_mask = 0xFFFFFFFF,
3400   - .insns_flags = PPC_INSNS_603,
3401   - .flags = PPC_FLAGS_603,
3402   - .msr_mask = 0x000000000007FF73ULL,
3403   - },
3404   - /* PowerPC 603e */
3405   - {
3406   - .name = "603e",
3407   - .pvr = CPU_PPC_603E,
3408   - .pvr_mask = 0xFFFFFFFF,
3409   - .insns_flags = PPC_INSNS_603,
3410   - .flags = PPC_FLAGS_603,
3411   - .msr_mask = 0x000000000007FF73ULL,
3412   - },
3413   - {
3414   - .name = "Stretch",
3415   - .pvr = CPU_PPC_603E,
3416   - .pvr_mask = 0xFFFFFFFF,
3417   - .insns_flags = PPC_INSNS_603,
3418   - .flags = PPC_FLAGS_603,
3419   - .msr_mask = 0x000000000007FF73ULL,
3420   - },
3421   - /* PowerPC 603p */
3422   - {
3423   - .name = "603p",
3424   - .pvr = CPU_PPC_603P,
3425   - .pvr_mask = 0xFFFFFFFF,
3426   - .insns_flags = PPC_INSNS_603,
3427   - .flags = PPC_FLAGS_603,
3428   - .msr_mask = 0x000000000007FF73ULL,
3429   - },
3430   - /* PowerPC 603e7 */
3431   - {
3432   - .name = "603e7",
3433   - .pvr = CPU_PPC_603E7,
3434   - .pvr_mask = 0xFFFFFFFF,
3435   - .insns_flags = PPC_INSNS_603,
3436   - .flags = PPC_FLAGS_603,
3437   - .msr_mask = 0x000000000007FF73ULL,
3438   - },
3439   - /* PowerPC 603e7v */
3440   - {
3441   - .name = "603e7v",
3442   - .pvr = CPU_PPC_603E7v,
3443   - .pvr_mask = 0xFFFFFFFF,
3444   - .insns_flags = PPC_INSNS_603,
3445   - .flags = PPC_FLAGS_603,
3446   - .msr_mask = 0x000000000007FF73ULL,
3447   - },
3448   - /* PowerPC 603e7v2 */
3449   - {
3450   - .name = "603e7v2",
3451   - .pvr = CPU_PPC_603E7v2,
3452   - .pvr_mask = 0xFFFFFFFF,
3453   - .insns_flags = PPC_INSNS_603,
3454   - .flags = PPC_FLAGS_603,
3455   - .msr_mask = 0x000000000007FF73ULL,
3456   - },
3457   - /* PowerPC 603r */
3458   - {
3459   - .name = "603r",
3460   - .pvr = CPU_PPC_603R,
3461   - .pvr_mask = 0xFFFFFFFF,
3462   - .insns_flags = PPC_INSNS_603,
3463   - .flags = PPC_FLAGS_603,
3464   - .msr_mask = 0x000000000007FF73ULL,
3465   - },
3466   - {
3467   - .name = "Goldeneye",
3468   - .pvr = CPU_PPC_603R,
3469   - .pvr_mask = 0xFFFFFFFF,
3470   - .insns_flags = PPC_INSNS_603,
3471   - .flags = PPC_FLAGS_603,
3472   - .msr_mask = 0x000000000007FF73ULL,
3473   - },
  4873 + /* POWER4 */
  4874 + POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
  4875 +#endif
3474 4876 #if defined (TODO)
3475   - /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3476   - {
3477   - .name = "G2",
3478   - .pvr = CPU_PPC_G2,
3479   - .pvr_mask = 0xFFFFFFFF,
3480   - .insns_flags = PPC_INSNS_G2,
3481   - .flags = PPC_FLAGS_G2,
3482   - .msr_mask = 0x000000000006FFF2ULL,
3483   - },
3484   - {
3485   - .name = "G2h4",
3486   - .pvr = CPU_PPC_G2H4,
3487   - .pvr_mask = 0xFFFFFFFF,
3488   - .insns_flags = PPC_INSNS_G2,
3489   - .flags = PPC_FLAGS_G2,
3490   - .msr_mask = 0x000000000006FFF2ULL,
3491   - },
3492   - {
3493   - .name = "G2gp",
3494   - .pvr = CPU_PPC_G2gp,
3495   - .pvr_mask = 0xFFFFFFFF,
3496   - .insns_flags = PPC_INSNS_G2,
3497   - .flags = PPC_FLAGS_G2,
3498   - .msr_mask = 0x000000000006FFF2ULL,
3499   - },
3500   - {
3501   - .name = "G2ls",
3502   - .pvr = CPU_PPC_G2ls,
3503   - .pvr_mask = 0xFFFFFFFF,
3504   - .insns_flags = PPC_INSNS_G2,
3505   - .flags = PPC_FLAGS_G2,
3506   - .msr_mask = 0x000000000006FFF2ULL,
3507   - },
3508   - { /* Same as G2, with LE mode support */
3509   - .name = "G2le",
3510   - .pvr = CPU_PPC_G2LE,
3511   - .pvr_mask = 0xFFFFFFFF,
3512   - .insns_flags = PPC_INSNS_G2,
3513   - .flags = PPC_FLAGS_G2,
3514   - .msr_mask = 0x000000000007FFF3ULL,
3515   - },
3516   - {
3517   - .name = "G2legp",
3518   - .pvr = CPU_PPC_G2LEgp,
3519   - .pvr_mask = 0xFFFFFFFF,
3520   - .insns_flags = PPC_INSNS_G2,
3521   - .flags = PPC_FLAGS_G2,
3522   - .msr_mask = 0x000000000007FFF3ULL,
3523   - },
3524   - {
3525   - .name = "G2lels",
3526   - .pvr = CPU_PPC_G2LEls,
3527   - .pvr_mask = 0xFFFFFFFF,
3528   - .insns_flags = PPC_INSNS_G2,
3529   - .flags = PPC_FLAGS_G2,
3530   - .msr_mask = 0x000000000007FFF3ULL,
3531   - },
3532   -#endif
3533   - /* PowerPC 604 */
3534   - {
3535   - .name = "604",
3536   - .pvr = CPU_PPC_604,
3537   - .pvr_mask = 0xFFFFFFFF,
3538   - .insns_flags = PPC_INSNS_604,
3539   - .flags = PPC_FLAGS_604,
3540   - .msr_mask = 0x000000000005FF77ULL,
3541   - },
3542   - /* PowerPC 604e */
3543   - {
3544   - .name = "604e",
3545   - .pvr = CPU_PPC_604E,
3546   - .pvr_mask = 0xFFFFFFFF,
3547   - .insns_flags = PPC_INSNS_604,
3548   - .flags = PPC_FLAGS_604,
3549   - .msr_mask = 0x000000000005FF77ULL,
3550   - },
3551   - /* PowerPC 604r */
3552   - {
3553   - .name = "604r",
3554   - .pvr = CPU_PPC_604R,
3555   - .pvr_mask = 0xFFFFFFFF,
3556   - .insns_flags = PPC_INSNS_604,
3557   - .flags = PPC_FLAGS_604,
3558   - .msr_mask = 0x000000000005FF77ULL,
3559   - },
3560   - /* generic G3 */
3561   - {
3562   - .name = "G3",
3563   - .pvr = CPU_PPC_74x,
3564   - .pvr_mask = 0xFFFFFFFF,
3565   - .insns_flags = PPC_INSNS_7x0,
3566   - .flags = PPC_FLAGS_7x0,
3567   - .msr_mask = 0x000000000007FF77ULL,
3568   - },
3569   - /* MPC740 (G3) */
3570   - {
3571   - .name = "740",
3572   - .pvr = CPU_PPC_74x,
3573   - .pvr_mask = 0xFFFFFFFF,
3574   - .insns_flags = PPC_INSNS_7x0,
3575   - .flags = PPC_FLAGS_7x0,
3576   - .msr_mask = 0x000000000007FF77ULL,
3577   - },
3578   - {
3579   - .name = "Arthur",
3580   - .pvr = CPU_PPC_74x,
3581   - .pvr_mask = 0xFFFFFFFF,
3582   - .insns_flags = PPC_INSNS_7x0,
3583   - .flags = PPC_FLAGS_7x0,
3584   - .msr_mask = 0x000000000007FF77ULL,
3585   - },
3586   - /* 740E (G3) */
3587   - {
3588   - .name = "740e",
3589   - .pvr = CPU_PPC_740E,
3590   - .pvr_mask = 0xFFFFFFFF,
3591   - .insns_flags = PPC_INSNS_7x0,
3592   - .flags = PPC_FLAGS_7x0,
3593   - .msr_mask = 0x000000000007FF77ULL,
3594   - },
3595   - /* MPC740P (G3) */
3596   - {
3597   - .name = "740p",
3598   - .pvr = CPU_PPC_74xP,
3599   - .pvr_mask = 0xFFFFFFFF,
3600   - .insns_flags = PPC_INSNS_7x0,
3601   - .flags = PPC_FLAGS_7x0,
3602   - .msr_mask = 0x000000000007FF77ULL,
3603   - },
3604   - {
3605   - .name = "Conan/Doyle",
3606   - .pvr = CPU_PPC_74xP,
3607   - .pvr_mask = 0xFFFFFFFF,
3608   - .insns_flags = PPC_INSNS_7x0,
3609   - .flags = PPC_FLAGS_7x0,
3610   - .msr_mask = 0x000000000007FF77ULL,
3611   - },
  4877 + /* POWER4p */
  4878 + POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
  4879 +#endif
3612 4880 #if defined (TODO)
3613   - /* MPC745 (G3) */
3614   - {
3615   - .name = "745",
3616   - .pvr = CPU_PPC_74x,
3617   - .pvr_mask = 0xFFFFFFFF,
3618   - .insns_flags = PPC_INSNS_7x5,
3619   - .flags = PPC_FLAGS_7x5,
3620   - .msr_mask = 0x000000000007FF77ULL,
3621   - },
3622   - {
3623   - .name = "Goldfinger",
3624   - .pvr = CPU_PPC_74x,
3625   - .pvr_mask = 0xFFFFFFFF,
3626   - .insns_flags = PPC_INSNS_7x5,
3627   - .flags = PPC_FLAGS_7x5,
3628   - .msr_mask = 0x000000000007FF77ULL,
3629   - },
  4881 + /* POWER5 */
  4882 + POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
  4883 + /* POWER5GR */
  4884 + POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
3630 4885 #endif
3631 4886 #if defined (TODO)
3632   - /* MPC745P (G3) */
3633   - {
3634   - .name = "745p",
3635   - .pvr = CPU_PPC_74xP,
3636   - .pvr_mask = 0xFFFFFFFF,
3637   - .insns_flags = PPC_INSNS_7x5,
3638   - .flags = PPC_FLAGS_7x5,
3639   - .msr_mask = 0x000000000007FF77ULL,
3640   - },
3641   -#endif
3642   - /* MPC750 (G3) */
3643   - {
3644   - .name = "750",
3645   - .pvr = CPU_PPC_74x,
3646   - .pvr_mask = 0xFFFFFFFF,
3647   - .insns_flags = PPC_INSNS_7x0,
3648   - .flags = PPC_FLAGS_7x0,
3649   - .msr_mask = 0x000000000007FF77ULL,
3650   - },
3651   - /* MPC750P (G3) */
3652   - {
3653   - .name = "750p",
3654   - .pvr = CPU_PPC_74xP,
3655   - .pvr_mask = 0xFFFFFFFF,
3656   - .insns_flags = PPC_INSNS_7x0,
3657   - .flags = PPC_FLAGS_7x0,
3658   - .msr_mask = 0x000000000007FF77ULL,
3659   - },
3660   - /* 750E (G3) */
3661   - {
3662   - .name = "750e",
3663   - .pvr = CPU_PPC_750E,
3664   - .pvr_mask = 0xFFFFFFFF,
3665   - .insns_flags = PPC_INSNS_7x0,
3666   - .flags = PPC_FLAGS_7x0,
3667   - .msr_mask = 0x000000000007FF77ULL,
3668   - },
3669   - /* IBM 750CXe (G3 embedded) */
3670   - {
3671   - .name = "750cxe",
3672   - .pvr = CPU_PPC_750CXE,
3673   - .pvr_mask = 0xFFFFFFFF,
3674   - .insns_flags = PPC_INSNS_7x0,
3675   - .flags = PPC_FLAGS_7x0,
3676   - .msr_mask = 0x000000000007FF77ULL,
3677   - },
3678   - /* IBM 750CXr (G3 embedded) */
3679   - {
3680   - .name = "750cxr",
3681   - .pvr = CPU_PPC_750CXR,
3682   - .pvr_mask = 0xFFFFFFFF,
3683   - .insns_flags = PPC_INSNS_7x0,
3684   - .flags = PPC_FLAGS_7x0,
3685   - .msr_mask = 0x000000000007FF77ULL,
3686   - },
3687   - /* IBM 750FX (G3 embedded) */
3688   - {
3689   - .name = "750fx",
3690   - .pvr = CPU_PPC_750FX,
3691   - .pvr_mask = 0xFFFFFFFF,
3692   - .insns_flags = PPC_INSNS_7x0,
3693   - .flags = PPC_FLAGS_7x0,
3694   - .msr_mask = 0x000000000007FF77ULL,
3695   - },
3696   - /* IBM 750FL (G3 embedded) */
3697   - {
3698   - .name = "750fl",
3699   - .pvr = CPU_PPC_750FL,
3700   - .pvr_mask = 0xFFFFFFFF,
3701   - .insns_flags = PPC_INSNS_7x0,
3702   - .flags = PPC_FLAGS_7x0,
3703   - .msr_mask = 0x000000000007FF77ULL,
3704   - },
3705   - /* IBM 750GX (G3 embedded) */
3706   - {
3707   - .name = "750gx",
3708   - .pvr = CPU_PPC_750GX,
3709   - .pvr_mask = 0xFFFFFFFF,
3710   - .insns_flags = PPC_INSNS_7x0,
3711   - .flags = PPC_FLAGS_7x0,
3712   - .msr_mask = 0x000000000007FF77ULL,
3713   - },
3714   - /* IBM 750L (G3 embedded) */
3715   - {
3716   - .name = "750l",
3717   - .pvr = CPU_PPC_750L,
3718   - .pvr_mask = 0xFFFFFFFF,
3719   - .insns_flags = PPC_INSNS_7x0,
3720   - .flags = PPC_FLAGS_7x0,
3721   - .msr_mask = 0x000000000007FF77ULL,
3722   - },
3723   - /* IBM 750CL (G3 embedded) */
3724   - {
3725   - .name = "750cl",
3726   - .pvr = CPU_PPC_750CL,
3727   - .pvr_mask = 0xFFFFFFFF,
3728   - .insns_flags = PPC_INSNS_7x0,
3729   - .flags = PPC_FLAGS_7x0,
3730   - .msr_mask = 0x000000000007FF77ULL,
3731   - },
  4887 + /* POWER5+ */
  4888 + POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
  4889 + /* POWER5GS */
  4890 + POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
  4891 +#endif
3732 4892 #if defined (TODO)
3733   - /* MPC755 (G3) */
3734   - {
3735   - .name = "755",
3736   - .pvr = CPU_PPC_755,
3737   - .pvr_mask = 0xFFFFFFFF,
3738   - .insns_flags = PPC_INSNS_7x5,
3739   - .flags = PPC_FLAGS_7x5,
3740   - .msr_mask = 0x000000000007FF77ULL,
3741   - },
  4893 + /* POWER6 */
  4894 + POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
  4895 + /* POWER6 running in POWER5 mode */
  4896 + POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
  4897 + /* POWER6A */
  4898 + POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
3742 4899 #endif
3743 4900 #if defined (TODO)
3744   - /* MPC755D (G3) */
3745   - {
3746   - .name = "755d",
3747   - .pvr = CPU_PPC_755D,
3748   - .pvr_mask = 0xFFFFFFFF,
3749   - .insns_flags = PPC_INSNS_7x5,
3750   - .flags = PPC_FLAGS_7x5,
3751   - .msr_mask = 0x000000000007FF77ULL,
3752   - },
  4901 + /* PowerPC 970 */
  4902 + POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
3753 4903 #endif
3754 4904 #if defined (TODO)
3755   - /* MPC755E (G3) */
3756   - {
3757   - .name = "755e",
3758   - .pvr = CPU_PPC_755E,
3759   - .pvr_mask = 0xFFFFFFFF,
3760   - .insns_flags = PPC_INSNS_7x5,
3761   - .flags = PPC_FLAGS_7x5,
3762   - .msr_mask = 0x000000000007FF77ULL,
3763   - },
  4905 + /* PowerPC 970FX (G5) */
  4906 + POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
3764 4907 #endif
3765 4908 #if defined (TODO)
3766   - /* MPC755P (G3) */
3767   - {
3768   - .name = "755p",
3769   - .pvr = CPU_PPC_74xP,
3770   - .pvr_mask = 0xFFFFFFFF,
3771   - .insns_flags = PPC_INSNS_7x5,
3772   - .flags = PPC_FLAGS_7x5,
3773   - .msr_mask = 0x000000000007FF77ULL,
3774   - },
  4909 + /* PowerPC 970FX v1.0 (G5) */
  4910 + POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
3775 4911 #endif
3776 4912 #if defined (TODO)
3777   - /* generic G4 */
3778   - {
3779   - .name = "G4",
3780   - .pvr = CPU_PPC_7400,
3781   - .pvr_mask = 0xFFFFFFFF,
3782   - .insns_flags = PPC_INSNS_74xx,
3783   - .flags = PPC_FLAGS_74xx,
3784   - .msr_mask = 0x000000000205FF77ULL,
3785   - },
  4913 + /* PowerPC 970FX v2.0 (G5) */
  4914 + POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
3786 4915 #endif
3787 4916 #if defined (TODO)
3788   - /* PowerPC 7400 (G4) */
3789   - {
3790   - .name = "7400",
3791   - .pvr = CPU_PPC_7400,
3792   - .pvr_mask = 0xFFFFFFFF,
3793   - .insns_flags = PPC_INSNS_74xx,
3794   - .flags = PPC_FLAGS_74xx,
3795   - .msr_mask = 0x000000000205FF77ULL,
3796   - },
3797   - {
3798   - .name = "Max",
3799   - .pvr = CPU_PPC_7400,
3800   - .pvr_mask = 0xFFFFFFFF,
3801   - .insns_flags = PPC_INSNS_74xx,
3802   - .flags = PPC_FLAGS_74xx,
3803   - .msr_mask = 0x000000000205FF77ULL,
3804   - },
  4917 + /* PowerPC 970FX v2.1 (G5) */
  4918 + POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
3805 4919 #endif
3806 4920 #if defined (TODO)
3807   - /* PowerPC 7410 (G4) */
3808   - {
3809   - .name = "7410",
3810   - .pvr = CPU_PPC_7410,
3811   - .pvr_mask = 0xFFFFFFFF,
3812   - .insns_flags = PPC_INSNS_74xx,
3813   - .flags = PPC_FLAGS_74xx,
3814   - .msr_mask = 0x000000000205FF77ULL,
3815   - },
3816   - {
3817   - .name = "Nitro",
3818   - .pvr = CPU_PPC_7410,
3819   - .pvr_mask = 0xFFFFFFFF,
3820   - .insns_flags = PPC_INSNS_74xx,
3821   - .flags = PPC_FLAGS_74xx,
3822   - .msr_mask = 0x000000000205FF77ULL,
3823   - },
  4921 + /* PowerPC 970FX v3.0 (G5) */
  4922 + POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
3824 4923 #endif
3825 4924 #if defined (TODO)
3826   - /* PowerPC 7441 (G4) */
3827   - {
3828   - .name = "7441",
3829   - .pvr = CPU_PPC_7441,
3830   - .pvr_mask = 0xFFFFFFFF,
3831   - .insns_flags = PPC_INSNS_74xx,
3832   - .flags = PPC_FLAGS_74xx,
3833   - .msr_mask = 0x000000000205FF77ULL,
3834   - },
  4925 + /* PowerPC 970FX v3.1 (G5) */
  4926 + POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
3835 4927 #endif
3836 4928 #if defined (TODO)
3837   - /* PowerPC 7445 (G4) */
3838   - {
3839   - .name = "7445",
3840   - .pvr = CPU_PPC_7445,
3841   - .pvr_mask = 0xFFFFFFFF,
3842   - .insns_flags = PPC_INSNS_74xx,
3843   - .flags = PPC_FLAGS_74xx,
3844   - .msr_mask = 0x000000000205FF77ULL,
3845   - },
  4929 + /* PowerPC 970GX (G5) */
  4930 + POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
3846 4931 #endif
3847 4932 #if defined (TODO)
3848   - /* PowerPC 7447 (G4) */
3849   - {
3850   - .name = "7447",
3851   - .pvr = CPU_PPC_7447,
3852   - .pvr_mask = 0xFFFFFFFF,
3853   - .insns_flags = PPC_INSNS_74xx,
3854   - .flags = PPC_FLAGS_74xx,
3855   - .msr_mask = 0x000000000205FF77ULL,
3856   - },
  4933 + /* PowerPC 970MP */
  4934 + POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
3857 4935 #endif
3858 4936 #if defined (TODO)
3859   - /* PowerPC 7447A (G4) */
3860   - {
3861   - .name = "7447A",
3862   - .pvr = CPU_PPC_7447A,
3863   - .pvr_mask = 0xFFFFFFFF,
3864   - .insns_flags = PPC_INSNS_74xx,
3865   - .flags = PPC_FLAGS_74xx,
3866   - .msr_mask = 0x000000000205FF77ULL,
3867   - },
  4937 + /* PowerPC 970MP v1.0 */
  4938 + POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
3868 4939 #endif
3869 4940 #if defined (TODO)
3870   - /* PowerPC 7448 (G4) */
3871   - {
3872   - .name = "7448",
3873   - .pvr = CPU_PPC_7448,
3874   - .pvr_mask = 0xFFFFFFFF,
3875   - .insns_flags = PPC_INSNS_74xx,
3876   - .flags = PPC_FLAGS_74xx,
3877   - .msr_mask = 0x000000000205FF77ULL,
3878   - },
  4941 + /* PowerPC 970MP v1.1 */
  4942 + POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
3879 4943 #endif
3880 4944 #if defined (TODO)
3881   - /* PowerPC 7450 (G4) */
3882   - {
3883   - .name = "7450",
3884   - .pvr = CPU_PPC_7450,
3885   - .pvr_mask = 0xFFFFFFFF,
3886   - .insns_flags = PPC_INSNS_74xx,
3887   - .flags = PPC_FLAGS_74xx,
3888   - .msr_mask = 0x000000000205FF77ULL,
3889   - },
3890   - {
3891   - .name = "Vger",
3892   - .pvr = CPU_PPC_7450,
3893   - .pvr_mask = 0xFFFFFFFF,
3894   - .insns_flags = PPC_INSNS_74xx,
3895   - .flags = PPC_FLAGS_74xx,
3896   - .msr_mask = 0x000000000205FF77ULL,
3897   - },
  4945 + /* PowerPC Cell */
  4946 + POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
3898 4947 #endif
3899 4948 #if defined (TODO)
3900   - /* PowerPC 7450b (G4) */
3901   - {
3902   - .name = "7450b",
3903   - .pvr = CPU_PPC_7450B,
3904   - .pvr_mask = 0xFFFFFFFF,
3905   - .insns_flags = PPC_INSNS_74xx,
3906   - .flags = PPC_FLAGS_74xx,
3907   - .msr_mask = 0x000000000205FF77ULL,
3908   - },
  4949 + /* PowerPC Cell v1.0 */
  4950 + POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
3909 4951 #endif
3910 4952 #if defined (TODO)
3911   - /* PowerPC 7451 (G4) */
3912   - {
3913   - .name = "7451",
3914   - .pvr = CPU_PPC_7451,
3915   - .pvr_mask = 0xFFFFFFFF,
3916   - .insns_flags = PPC_INSNS_74xx,
3917   - .flags = PPC_FLAGS_74xx,
3918   - .msr_mask = 0x000000000205FF77ULL,
3919   - },
  4953 + /* PowerPC Cell v2.0 */
  4954 + POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
3920 4955 #endif
3921 4956 #if defined (TODO)
3922   - /* PowerPC 7451g (G4) */
3923   - {
3924   - .name = "7451g",
3925   - .pvr = CPU_PPC_7451G,
3926   - .pvr_mask = 0xFFFFFFFF,
3927   - .insns_flags = PPC_INSNS_74xx,
3928   - .flags = PPC_FLAGS_74xx,
3929   - .msr_mask = 0x000000000205FF77ULL,
3930   - },
  4957 + /* PowerPC Cell v3.0 */
  4958 + POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
3931 4959 #endif
3932 4960 #if defined (TODO)
3933   - /* PowerPC 7455 (G4) */
3934   - {
3935   - .name = "7455",
3936   - .pvr = CPU_PPC_7455,
3937   - .pvr_mask = 0xFFFFFFFF,
3938   - .insns_flags = PPC_INSNS_74xx,
3939   - .flags = PPC_FLAGS_74xx,
3940   - .msr_mask = 0x000000000205FF77ULL,
3941   - },
3942   - {
3943   - .name = "Apollo 6",
3944   - .pvr = CPU_PPC_7455,
3945   - .pvr_mask = 0xFFFFFFFF,
3946   - .insns_flags = PPC_INSNS_74xx,
3947   - .flags = PPC_FLAGS_74xx,
3948   - .msr_mask = 0x000000000205FF77ULL,
3949   - },
  4961 + /* PowerPC Cell v3.1 */
  4962 + POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
3950 4963 #endif
3951 4964 #if defined (TODO)
3952   - /* PowerPC 7455F (G4) */
3953   - {
3954   - .name = "7455f",
3955   - .pvr = CPU_PPC_7455F,
3956   - .pvr_mask = 0xFFFFFFFF,
3957   - .insns_flags = PPC_INSNS_74xx,
3958   - .flags = PPC_FLAGS_74xx,
3959   - .msr_mask = 0x000000000205FF77ULL,
3960   - },
  4965 + /* PowerPC Cell v3.2 */
  4966 + POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
3961 4967 #endif
3962 4968 #if defined (TODO)
3963   - /* PowerPC 7455G (G4) */
3964   - {
3965   - .name = "7455g",
3966   - .pvr = CPU_PPC_7455G,
3967   - .pvr_mask = 0xFFFFFFFF,
3968   - .insns_flags = PPC_INSNS_74xx,
3969   - .flags = PPC_FLAGS_74xx,
3970   - .msr_mask = 0x000000000205FF77ULL,
3971   - },
  4969 + /* RS64 (Apache/A35) */
  4970 + /* This one seems to support the whole POWER2 instruction set
  4971 + * and the PowerPC 64 one.
  4972 + */
  4973 + /* What about A10 & A30 ? */
  4974 + POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
  4975 + POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
  4976 + POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
3972 4977 #endif
3973 4978 #if defined (TODO)
3974   - /* PowerPC 7457 (G4) */
3975   - {
3976   - .name = "7457",
3977   - .pvr = CPU_PPC_7457,
3978   - .pvr_mask = 0xFFFFFFFF,
3979   - .insns_flags = PPC_INSNS_74xx,
3980   - .flags = PPC_FLAGS_74xx,
3981   - .msr_mask = 0x000000000205FF77ULL,
3982   - },
3983   - {
3984   - .name = "Apollo 7",
3985   - .pvr = CPU_PPC_7457,
3986   - .pvr_mask = 0xFFFFFFFF,
3987   - .insns_flags = PPC_INSNS_74xx,
3988   - .flags = PPC_FLAGS_74xx,
3989   - .msr_mask = 0x000000000205FF77ULL,
3990   - },
  4979 + /* RS64-II (NorthStar/A50) */
  4980 + POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
  4981 + POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
  4982 + POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
3991 4983 #endif
3992 4984 #if defined (TODO)
3993   - /* PowerPC 7457A (G4) */
3994   - {
3995   - .name = "7457A",
3996   - .pvr = CPU_PPC_7457A,
3997   - .pvr_mask = 0xFFFFFFFF,
3998   - .insns_flags = PPC_INSNS_74xx,
3999   - .flags = PPC_FLAGS_74xx,
4000   - .msr_mask = 0x000000000205FF77ULL,
4001   - },
4002   - {
4003   - .name = "Apollo 7 PM",
4004   - .pvr = CPU_PPC_7457A,
4005   - .pvr_mask = 0xFFFFFFFF,
4006   - .insns_flags = PPC_INSNS_74xx,
4007   - .flags = PPC_FLAGS_74xx,
4008   - .msr_mask = 0x000000000205FF77ULL,
4009   - },
  4985 + /* RS64-III (Pulsar) */
  4986 + POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
  4987 + POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
4010 4988 #endif
4011 4989 #if defined (TODO)
4012   - /* PowerPC 7457C (G4) */
4013   - {
4014   - .name = "7457c",
4015   - .pvr = CPU_PPC_7457C,
4016   - .pvr_mask = 0xFFFFFFFF,
4017   - .insns_flags = PPC_INSNS_74xx,
4018   - .flags = PPC_FLAGS_74xx,
4019   - .msr_mask = 0x000000000205FF77ULL,
4020   - },
  4990 + /* RS64-IV (IceStar/IStar/SStar) */
  4991 + POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
  4992 + POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
  4993 + POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
  4994 + POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
4021 4995 #endif
4022   - /* 64 bits PowerPC */
4023   -#if defined (TARGET_PPC64)
  4996 +#endif /* defined (TARGET_PPC64) */
  4997 + /* POWER */
4024 4998 #if defined (TODO)
4025   - /* PowerPC 620 */
4026   - {
4027   - .name = "620",
4028   - .pvr = CPU_PPC_620,
4029   - .pvr_mask = 0xFFFFFFFF,
4030   - .insns_flags = PPC_INSNS_620,
4031   - .flags = PPC_FLAGS_620,
4032   - .msr_mask = 0x800000000005FF73ULL,
4033   - },
  4999 + /* Original POWER */
  5000 + POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
  5001 + POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
  5002 + POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
  5003 + POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
  5004 + POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
4034 5005 #endif
4035 5006 #if defined (TODO)
4036   - /* PowerPC 630 (POWER3) */
4037   - {
4038   - .name = "630",
4039   - .pvr = CPU_PPC_630,
4040   - .pvr_mask = 0xFFFFFFFF,
4041   - .insns_flags = PPC_INSNS_630,
4042   - .flags = PPC_FLAGS_630,
4043   - .msr_mask = xxx,
  5007 + /* POWER2 */
  5008 + POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
  5009 + POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
  5010 + POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
  5011 +#endif
  5012 + /* PA semi cores */
  5013 +#if defined (TODO)
  5014 + /* PA PA6T */
  5015 + POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
  5016 +#endif
  5017 + /* Generic PowerPCs */
  5018 +#if defined (TARGET_PPC64)
  5019 +#if defined (TODO)
  5020 + POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
  5021 +#endif
  5022 +#endif
  5023 + POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
  5024 + /* Fallback */
  5025 + POWERPC_DEF("ppc", CPU_POWERPC_PPC, 0xFFFFFFFF, PPC),
  5026 +};
  5027 +
  5028 +/*****************************************************************************/
  5029 +/* Generic CPU instanciation routine */
  5030 +static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
  5031 +{
  5032 +#if !defined(CONFIG_USER_ONLY)
  5033 + env->irq_inputs = NULL;
  5034 +#endif
  5035 + /* Default MMU definitions */
  5036 + env->nb_BATs = 0;
  5037 + env->nb_tlb = 0;
  5038 + env->nb_ways = 0;
  5039 + /* Register SPR common to all PowerPC implementations */
  5040 + gen_spr_generic(env);
  5041 + spr_register(env, SPR_PVR, "PVR",
  5042 + SPR_NOACCESS, SPR_NOACCESS,
  5043 + &spr_read_generic, SPR_NOACCESS,
  5044 + def->pvr);
  5045 + /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
  5046 + (*def->init_proc)(env);
  5047 + /* Allocate TLBs buffer when needed */
  5048 + if (env->nb_tlb != 0) {
  5049 + int nb_tlb = env->nb_tlb;
  5050 + if (env->id_tlbs != 0)
  5051 + nb_tlb *= 2;
  5052 + env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
  5053 + /* Pre-compute some useful values */
  5054 + env->tlb_per_way = env->nb_tlb / env->nb_ways;
  5055 + }
  5056 +#if !defined(CONFIG_USER_ONLY)
  5057 + if (env->irq_inputs == NULL) {
  5058 + fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
  5059 + " Attempt Qemu to crash very soon !\n");
  5060 + }
  5061 +#endif
  5062 +}
  5063 +
  5064 +#if defined(PPC_DUMP_CPU)
  5065 +static void dump_ppc_sprs (CPUPPCState *env)
  5066 +{
  5067 + ppc_spr_t *spr;
  5068 +#if !defined(CONFIG_USER_ONLY)
  5069 + uint32_t sr, sw;
  5070 +#endif
  5071 + uint32_t ur, uw;
  5072 + int i, j, n;
  5073 +
  5074 + printf("Special purpose registers:\n");
  5075 + for (i = 0; i < 32; i++) {
  5076 + for (j = 0; j < 32; j++) {
  5077 + n = (i << 5) | j;
  5078 + spr = &env->spr_cb[n];
  5079 + uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
  5080 + ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
  5081 +#if !defined(CONFIG_USER_ONLY)
  5082 + sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
  5083 + sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
  5084 + if (sw || sr || uw || ur) {
  5085 + printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
  5086 + (i << 5) | j, (i << 5) | j, spr->name,
  5087 + sw ? 'w' : '-', sr ? 'r' : '-',
  5088 + uw ? 'w' : '-', ur ? 'r' : '-');
  5089 + }
  5090 +#else
  5091 + if (uw || ur) {
  5092 + printf("SPR: %4d (%03x) %-8s u%c%c\n",
  5093 + (i << 5) | j, (i << 5) | j, spr->name,
  5094 + uw ? 'w' : '-', ur ? 'r' : '-');
  5095 + }
  5096 +#endif
  5097 + }
  5098 + }
  5099 + fflush(stdout);
  5100 + fflush(stderr);
  5101 +}
  5102 +#endif
  5103 +
  5104 +/*****************************************************************************/
  5105 +#include <stdlib.h>
  5106 +#include <string.h>
  5107 +
  5108 +int fflush (FILE *stream);
  5109 +
  5110 +/* Opcode types */
  5111 +enum {
  5112 + PPC_DIRECT = 0, /* Opcode routine */
  5113 + PPC_INDIRECT = 1, /* Indirect opcode table */
  5114 +};
  5115 +
  5116 +static inline int is_indirect_opcode (void *handler)
  5117 +{
  5118 + return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
  5119 +}
  5120 +
  5121 +static inline opc_handler_t **ind_table(void *handler)
  5122 +{
  5123 + return (opc_handler_t **)((unsigned long)handler & ~3);
  5124 +}
  5125 +
  5126 +/* Instruction table creation */
  5127 +/* Opcodes tables creation */
  5128 +static void fill_new_table (opc_handler_t **table, int len)
  5129 +{
  5130 + int i;
  5131 +
  5132 + for (i = 0; i < len; i++)
  5133 + table[i] = &invalid_handler;
  5134 +}
  5135 +
  5136 +static int create_new_table (opc_handler_t **table, unsigned char idx)
  5137 +{
  5138 + opc_handler_t **tmp;
  5139 +
  5140 + tmp = malloc(0x20 * sizeof(opc_handler_t));
  5141 + if (tmp == NULL)
  5142 + return -1;
  5143 + fill_new_table(tmp, 0x20);
  5144 + table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
  5145 +
  5146 + return 0;
  5147 +}
  5148 +
  5149 +static int insert_in_table (opc_handler_t **table, unsigned char idx,
  5150 + opc_handler_t *handler)
  5151 +{
  5152 + if (table[idx] != &invalid_handler)
  5153 + return -1;
  5154 + table[idx] = handler;
  5155 +
  5156 + return 0;
  5157 +}
  5158 +
  5159 +static int register_direct_insn (opc_handler_t **ppc_opcodes,
  5160 + unsigned char idx, opc_handler_t *handler)
  5161 +{
  5162 + if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
  5163 + printf("*** ERROR: opcode %02x already assigned in main "
  5164 + "opcode table\n", idx);
  5165 + return -1;
  5166 + }
  5167 +
  5168 + return 0;
  5169 +}
  5170 +
  5171 +static int register_ind_in_table (opc_handler_t **table,
  5172 + unsigned char idx1, unsigned char idx2,
  5173 + opc_handler_t *handler)
  5174 +{
  5175 + if (table[idx1] == &invalid_handler) {
  5176 + if (create_new_table(table, idx1) < 0) {
  5177 + printf("*** ERROR: unable to create indirect table "
  5178 + "idx=%02x\n", idx1);
  5179 + return -1;
  5180 + }
  5181 + } else {
  5182 + if (!is_indirect_opcode(table[idx1])) {
  5183 + printf("*** ERROR: idx %02x already assigned to a direct "
  5184 + "opcode\n", idx1);
  5185 + return -1;
  5186 + }
4044 5187 }
4045   - {
4046   - .name = "POWER3",
4047   - .pvr = CPU_PPC_630,
4048   - .pvr_mask = 0xFFFFFFFF,
4049   - .insns_flags = PPC_INSNS_630,
4050   - .flags = PPC_FLAGS_630,
4051   - .msr_mask = xxx,
  5188 + if (handler != NULL &&
  5189 + insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
  5190 + printf("*** ERROR: opcode %02x already assigned in "
  5191 + "opcode table %02x\n", idx2, idx1);
  5192 + return -1;
4052 5193 }
  5194 +
  5195 + return 0;
  5196 +}
  5197 +
  5198 +static int register_ind_insn (opc_handler_t **ppc_opcodes,
  5199 + unsigned char idx1, unsigned char idx2,
  5200 + opc_handler_t *handler)
  5201 +{
  5202 + int ret;
  5203 +
  5204 + ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
  5205 +
  5206 + return ret;
  5207 +}
  5208 +
  5209 +static int register_dblind_insn (opc_handler_t **ppc_opcodes,
  5210 + unsigned char idx1, unsigned char idx2,
  5211 + unsigned char idx3, opc_handler_t *handler)
  5212 +{
  5213 + if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
  5214 + printf("*** ERROR: unable to join indirect table idx "
  5215 + "[%02x-%02x]\n", idx1, idx2);
  5216 + return -1;
  5217 + }
  5218 + if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
  5219 + handler) < 0) {
  5220 + printf("*** ERROR: unable to insert opcode "
  5221 + "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
  5222 + return -1;
  5223 + }
  5224 +
  5225 + return 0;
  5226 +}
  5227 +
  5228 +static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
  5229 +{
  5230 + if (insn->opc2 != 0xFF) {
  5231 + if (insn->opc3 != 0xFF) {
  5232 + if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
  5233 + insn->opc3, &insn->handler) < 0)
  5234 + return -1;
  5235 + } else {
  5236 + if (register_ind_insn(ppc_opcodes, insn->opc1,
  5237 + insn->opc2, &insn->handler) < 0)
  5238 + return -1;
  5239 + }
  5240 + } else {
  5241 + if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
  5242 + return -1;
  5243 + }
  5244 +
  5245 + return 0;
  5246 +}
  5247 +
  5248 +static int test_opcode_table (opc_handler_t **table, int len)
  5249 +{
  5250 + int i, count, tmp;
  5251 +
  5252 + for (i = 0, count = 0; i < len; i++) {
  5253 + /* Consistency fixup */
  5254 + if (table[i] == NULL)
  5255 + table[i] = &invalid_handler;
  5256 + if (table[i] != &invalid_handler) {
  5257 + if (is_indirect_opcode(table[i])) {
  5258 + tmp = test_opcode_table(ind_table(table[i]), 0x20);
  5259 + if (tmp == 0) {
  5260 + free(table[i]);
  5261 + table[i] = &invalid_handler;
  5262 + } else {
  5263 + count++;
  5264 + }
  5265 + } else {
  5266 + count++;
  5267 + }
  5268 + }
  5269 + }
  5270 +
  5271 + return count;
  5272 +}
  5273 +
  5274 +static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
  5275 +{
  5276 + if (test_opcode_table(ppc_opcodes, 0x40) == 0)
  5277 + printf("*** WARNING: no opcode defined !\n");
  5278 +}
  5279 +
  5280 +/*****************************************************************************/
  5281 +static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
  5282 +{
  5283 + opcode_t *opc, *start, *end;
  5284 +
  5285 + fill_new_table(env->opcodes, 0x40);
  5286 + if (&opc_start < &opc_end) {
  5287 + start = &opc_start;
  5288 + end = &opc_end;
  5289 + } else {
  5290 + start = &opc_end;
  5291 + end = &opc_start;
  5292 + }
  5293 + for (opc = start + 1; opc != end; opc++) {
  5294 + if ((opc->handler.type & def->insns_flags) != 0) {
  5295 + if (register_insn(env->opcodes, opc) < 0) {
  5296 + printf("*** ERROR initializing PowerPC instruction "
  5297 + "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
  5298 + opc->opc3);
  5299 + return -1;
  5300 + }
  5301 + }
  5302 + }
  5303 + fix_opcode_tables(env->opcodes);
  5304 + fflush(stdout);
  5305 + fflush(stderr);
  5306 +
  5307 + return 0;
  5308 +}
  5309 +
  5310 +#if defined(PPC_DUMP_CPU)
  5311 +static int dump_ppc_insns (CPUPPCState *env)
  5312 +{
  5313 + opc_handler_t **table, *handler;
  5314 + uint8_t opc1, opc2, opc3;
  5315 +
  5316 + printf("Instructions set:\n");
  5317 + /* opc1 is 6 bits long */
  5318 + for (opc1 = 0x00; opc1 < 0x40; opc1++) {
  5319 + table = env->opcodes;
  5320 + handler = table[opc1];
  5321 + if (is_indirect_opcode(handler)) {
  5322 + /* opc2 is 5 bits long */
  5323 + for (opc2 = 0; opc2 < 0x20; opc2++) {
  5324 + table = env->opcodes;
  5325 + handler = env->opcodes[opc1];
  5326 + table = ind_table(handler);
  5327 + handler = table[opc2];
  5328 + if (is_indirect_opcode(handler)) {
  5329 + table = ind_table(handler);
  5330 + /* opc3 is 5 bits long */
  5331 + for (opc3 = 0; opc3 < 0x20; opc3++) {
  5332 + handler = table[opc3];
  5333 + if (handler->handler != &gen_invalid) {
  5334 + printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
  5335 + opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
  5336 + handler->oname);
  5337 + }
  5338 + }
  5339 + } else {
  5340 + if (handler->handler != &gen_invalid) {
  5341 + printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
  5342 + opc1, opc2, opc1, opc2, handler->oname);
  5343 + }
  5344 + }
  5345 + }
  5346 + } else {
  5347 + if (handler->handler != &gen_invalid) {
  5348 + printf("INSN: %02x -- -- (%02d ----) : %s\n",
  5349 + opc1, opc1, handler->oname);
  5350 + }
  5351 + }
  5352 + }
  5353 +}
4053 5354 #endif
4054   -#if defined (TODO)
4055   - /* PowerPC 631 (Power 3+)*/
4056   - {
4057   - .name = "631",
4058   - .pvr = CPU_PPC_631,
4059   - .pvr_mask = 0xFFFFFFFF,
4060   - .insns_flags = PPC_INSNS_631,
4061   - .flags = PPC_FLAGS_631,
4062   - .msr_mask = xxx,
4063   - },
4064   - {
4065   - .name = "POWER3+",
4066   - .pvr = CPU_PPC_631,
4067   - .pvr_mask = 0xFFFFFFFF,
4068   - .insns_flags = PPC_INSNS_631,
4069   - .flags = PPC_FLAGS_631,
4070   - .msr_mask = xxx,
4071   - },
4072   -#endif
4073   -#if defined (TODO)
4074   - /* POWER4 */
4075   - {
4076   - .name = "POWER4",
4077   - .pvr = CPU_PPC_POWER4,
4078   - .pvr_mask = 0xFFFFFFFF,
4079   - .insns_flags = PPC_INSNS_POWER4,
4080   - .flags = PPC_FLAGS_POWER4,
4081   - .msr_mask = xxx,
4082   - },
4083   -#endif
4084   -#if defined (TODO)
4085   - /* POWER4p */
4086   - {
4087   - .name = "POWER4+",
4088   - .pvr = CPU_PPC_POWER4P,
4089   - .pvr_mask = 0xFFFFFFFF,
4090   - .insns_flags = PPC_INSNS_POWER4,
4091   - .flags = PPC_FLAGS_POWER4,
4092   - .msr_mask = xxx,
4093   - },
4094   -#endif
4095   -#if defined (TODO)
4096   - /* POWER5 */
4097   - {
4098   - .name = "POWER5",
4099   - .pvr = CPU_PPC_POWER5,
4100   - .pvr_mask = 0xFFFFFFFF,
4101   - .insns_flags = PPC_INSNS_POWER5,
4102   - .flags = PPC_FLAGS_POWER5,
4103   - .msr_mask = xxx,
4104   - },
4105   -#endif
4106   -#if defined (TODO)
4107   - /* POWER5+ */
4108   - {
4109   - .name = "POWER5+",
4110   - .pvr = CPU_PPC_POWER5P,
4111   - .pvr_mask = 0xFFFFFFFF,
4112   - .insns_flags = PPC_INSNS_POWER5,
4113   - .flags = PPC_FLAGS_POWER5,
4114   - .msr_mask = xxx,
4115   - },
4116   -#endif
4117   -#if defined (TODO)
4118   - /* POWER6 */
4119   - {
4120   - .name = "POWER6",
4121   - .pvr = CPU_PPC_POWER6,
4122   - .pvr_mask = 0xFFFFFFFF,
4123   - .insns_flags = PPC_INSNS_POWER6,
4124   - .flags = PPC_FLAGS_POWER6,
4125   - .msr_mask = xxx,
4126   - },
4127   -#endif
4128   -#if defined (TODO)
4129   - /* PowerPC 970 */
4130   - {
4131   - .name = "970",
4132   - .pvr = CPU_PPC_970,
4133   - .pvr_mask = 0xFFFFFFFF,
4134   - .insns_flags = PPC_INSNS_970,
4135   - .flags = PPC_FLAGS_970,
4136   - .msr_mask = 0x900000000204FF36ULL,
4137   - },
4138   -#endif
4139   -#if defined (TODO)
4140   - /* PowerPC 970FX (G5) */
4141   - {
4142   - .name = "970fx",
4143   - .pvr = CPU_PPC_970FX,
4144   - .pvr_mask = 0xFFFFFFFF,
4145   - .insns_flags = PPC_INSNS_970FX,
4146   - .flags = PPC_FLAGS_970FX,
4147   - .msr_mask = 0x800000000204FF36ULL,
4148   - },
4149   -#endif
4150   -#if defined (TODO)
4151   - /* PowerPC 970MP */
4152   - {
4153   - .name = "970MP",
4154   - .pvr = CPU_PPC_970MP,
4155   - .pvr_mask = 0xFFFFFFFF,
4156   - .insns_flags = PPC_INSNS_970,
4157   - .flags = PPC_FLAGS_970,
4158   - .msr_mask = 0x900000000204FF36ULL,
4159   - },
4160   -#endif
4161   -#if defined (TODO)
4162   - /* PowerPC Cell */
4163   - {
4164   - .name = "Cell",
4165   - .pvr = CPU_PPC_CELL,
4166   - .pvr_mask = 0xFFFFFFFF,
4167   - .insns_flags = PPC_INSNS_970,
4168   - .flags = PPC_FLAGS_970,
4169   - .msr_mask = 0x900000000204FF36ULL,
4170   - },
4171   -#endif
4172   -#if defined (TODO)
4173   - /* RS64 (Apache/A35) */
4174   - /* This one seems to support the whole POWER2 instruction set
4175   - * and the PowerPC 64 one.
4176   - */
4177   - {
4178   - .name = "RS64",
4179   - .pvr = CPU_PPC_RS64,
4180   - .pvr_mask = 0xFFFFFFFF,
4181   - .insns_flags = PPC_INSNS_RS64,
4182   - .flags = PPC_FLAGS_RS64,
4183   - .msr_mask = xxx,
4184   - },
4185   - {
4186   - .name = "Apache",
4187   - .pvr = CPU_PPC_RS64,
4188   - .pvr_mask = 0xFFFFFFFF,
4189   - .insns_flags = PPC_INSNS_RS64,
4190   - .flags = PPC_FLAGS_RS64,
4191   - .msr_mask = xxx,
4192   - },
4193   - {
4194   - .name = "A35",
4195   - .pvr = CPU_PPC_RS64,
4196   - .pvr_mask = 0xFFFFFFFF,
4197   - .insns_flags = PPC_INSNS_RS64,
4198   - .flags = PPC_FLAGS_RS64,
4199   - .msr_mask = xxx,
4200   - },
4201   -#endif
4202   -#if defined (TODO)
4203   - /* RS64-II (NorthStar/A50) */
4204   - {
4205   - .name = "RS64-II",
4206   - .pvr = CPU_PPC_RS64II,
4207   - .pvr_mask = 0xFFFFFFFF,
4208   - .insns_flags = PPC_INSNS_RS64,
4209   - .flags = PPC_FLAGS_RS64,
4210   - .msr_mask = xxx,
4211   - },
4212   - {
4213   - .name = "NortStar",
4214   - .pvr = CPU_PPC_RS64II,
4215   - .pvr_mask = 0xFFFFFFFF,
4216   - .insns_flags = PPC_INSNS_RS64,
4217   - .flags = PPC_FLAGS_RS64,
4218   - .msr_mask = xxx,
4219   - },
4220   - {
4221   - .name = "A50",
4222   - .pvr = CPU_PPC_RS64II,
4223   - .pvr_mask = 0xFFFFFFFF,
4224   - .insns_flags = PPC_INSNS_RS64,
4225   - .flags = PPC_FLAGS_RS64,
4226   - .msr_mask = xxx,
4227   - },
4228   -#endif
4229   -#if defined (TODO)
4230   - /* RS64-III (Pulsar) */
4231   - {
4232   - .name = "RS64-III",
4233   - .pvr = CPU_PPC_RS64III,
4234   - .pvr_mask = 0xFFFFFFFF,
4235   - .insns_flags = PPC_INSNS_RS64,
4236   - .flags = PPC_FLAGS_RS64,
4237   - .msr_mask = xxx,
4238   - },
4239   - {
4240   - .name = "Pulsar",
4241   - .pvr = CPU_PPC_RS64III,
4242   - .pvr_mask = 0xFFFFFFFF,
4243   - .insns_flags = PPC_INSNS_RS64,
4244   - .flags = PPC_FLAGS_RS64,
4245   - .msr_mask = xxx,
4246   - },
4247   -#endif
4248   -#if defined (TODO)
4249   - /* RS64-IV (IceStar/IStar/SStar) */
4250   - {
4251   - .name = "RS64-IV",
4252   - .pvr = CPU_PPC_RS64IV,
4253   - .pvr_mask = 0xFFFFFFFF,
4254   - .insns_flags = PPC_INSNS_RS64,
4255   - .flags = PPC_FLAGS_RS64,
4256   - .msr_mask = xxx,
4257   - },
4258   - {
4259   - .name = "IceStar",
4260   - .pvr = CPU_PPC_RS64IV,
4261   - .pvr_mask = 0xFFFFFFFF,
4262   - .insns_flags = PPC_INSNS_RS64,
4263   - .flags = PPC_FLAGS_RS64,
4264   - .msr_mask = xxx,
4265   - },
4266   - {
4267   - .name = "IStar",
4268   - .pvr = CPU_PPC_RS64IV,
4269   - .pvr_mask = 0xFFFFFFFF,
4270   - .insns_flags = PPC_INSNS_RS64,
4271   - .flags = PPC_FLAGS_RS64,
4272   - .msr_mask = xxx,
4273   - },
4274   - {
4275   - .name = "SStar",
4276   - .pvr = CPU_PPC_RS64IV,
4277   - .pvr_mask = 0xFFFFFFFF,
4278   - .insns_flags = PPC_INSNS_RS64,
4279   - .flags = PPC_FLAGS_RS64,
4280   - .msr_mask = xxx,
4281   - },
4282   -#endif
4283   - /* POWER */
4284   -#if defined (TODO)
4285   - /* Original POWER */
4286   - {
4287   - .name = "POWER",
4288   - .pvr = CPU_POWER,
4289   - .pvr_mask = 0xFFFFFFFF,
4290   - .insns_flags = PPC_INSNS_POWER,
4291   - .flags = PPC_FLAGS_POWER,
4292   - .msr_mask = xxx,
4293   - },
4294   -#endif
4295   -#endif /* defined (TARGET_PPC64) */
4296   -#if defined (TODO)
4297   - /* POWER2 */
4298   - {
4299   - .name = "POWER2",
4300   - .pvr = CPU_POWER2,
4301   - .pvr_mask = 0xFFFFFFFF,
4302   - .insns_flags = PPC_INSNS_POWER,
4303   - .flags = PPC_FLAGS_POWER,
4304   - .msr_mask = xxx,
4305   - },
4306   -#endif
4307   - /* Generic PowerPCs */
4308   -#if defined (TODO)
  5355 +
  5356 +int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
  5357 +{
  5358 + env->msr_mask = def->msr_mask;
  5359 + env->mmu_model = def->mmu_model;
  5360 + env->excp_model = def->excp_model;
  5361 + env->bus_model = def->bus_model;
  5362 + if (create_ppc_opcodes(env, def) < 0)
  5363 + return -1;
  5364 + init_ppc_proc(env, def);
  5365 +#if defined(PPC_DUMP_CPU)
4309 5366 {
4310   - .name = "ppc64",
4311   - .pvr = CPU_PPC_970FX,
4312   - .pvr_mask = 0xFFFFFFFF,
4313   - .insns_flags = PPC_INSNS_PPC64,
4314   - .flags = PPC_FLAGS_PPC64,
4315   - .msr_mask = 0xA00000000204FF36ULL,
4316   - },
  5367 + const unsigned char *mmu_model, *excp_model, *bus_model;
  5368 + switch (env->mmu_model) {
  5369 + case POWERPC_MMU_32B:
  5370 + mmu_model = "PowerPC 32";
  5371 + break;
  5372 + case POWERPC_MMU_64B:
  5373 + mmu_model = "PowerPC 64";
  5374 + break;
  5375 + case POWERPC_MMU_601:
  5376 + mmu_model = "PowerPC 601";
  5377 + break;
  5378 + case POWERPC_MMU_SOFT_6xx:
  5379 + mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
  5380 + break;
  5381 + case POWERPC_MMU_SOFT_74xx:
  5382 + mmu_model = "PowerPC 74xx with software driven TLBs";
  5383 + break;
  5384 + case POWERPC_MMU_SOFT_4xx:
  5385 + mmu_model = "PowerPC 4xx with software driven TLBs";
  5386 + break;
  5387 + case POWERPC_MMU_SOFT_4xx_Z:
  5388 + mmu_model = "PowerPC 4xx with software driven TLBs "
  5389 + "and zones protections";
  5390 + break;
  5391 + case POWERPC_MMU_REAL_4xx:
  5392 + mmu_model = "PowerPC 4xx real mode only";
  5393 + break;
  5394 + case POWERPC_MMU_BOOKE:
  5395 + mmu_model = "PowerPC BookE";
  5396 + break;
  5397 + case POWERPC_MMU_BOOKE_FSL:
  5398 + mmu_model = "PowerPC BookE FSL";
  5399 + break;
  5400 + case POWERPC_MMU_64BRIDGE:
  5401 + mmu_model = "PowerPC 64 bridge";
  5402 + break;
  5403 + default:
  5404 + mmu_model = "Unknown or invalid";
  5405 + break;
  5406 + }
  5407 + switch (env->excp_model) {
  5408 + case POWERPC_EXCP_STD:
  5409 + excp_model = "PowerPC";
  5410 + break;
  5411 + case POWERPC_EXCP_40x:
  5412 + excp_model = "PowerPC 40x";
  5413 + break;
  5414 + case POWERPC_EXCP_601:
  5415 + excp_model = "PowerPC 601";
  5416 + break;
  5417 + case POWERPC_EXCP_602:
  5418 + excp_model = "PowerPC 602";
  5419 + break;
  5420 + case POWERPC_EXCP_603:
  5421 + excp_model = "PowerPC 603";
  5422 + break;
  5423 + case POWERPC_EXCP_603E:
  5424 + excp_model = "PowerPC 603e";
  5425 + break;
  5426 + case POWERPC_EXCP_604:
  5427 + excp_model = "PowerPC 604";
  5428 + break;
  5429 + case POWERPC_EXCP_7x0:
  5430 + excp_model = "PowerPC 740/750";
  5431 + break;
  5432 + case POWERPC_EXCP_7x5:
  5433 + excp_model = "PowerPC 745/755";
  5434 + break;
  5435 + case POWERPC_EXCP_74xx:
  5436 + excp_model = "PowerPC 74xx";
  5437 + break;
  5438 + case POWERPC_EXCP_970:
  5439 + excp_model = "PowerPC 970";
  5440 + break;
  5441 + case POWERPC_EXCP_BOOKE:
  5442 + excp_model = "PowerPC BookE";
  5443 + break;
  5444 + default:
  5445 + excp_model = "Unknown or invalid";
  5446 + break;
  5447 + }
  5448 + switch (env->bus_model) {
  5449 + case PPC_FLAGS_INPUT_6xx:
  5450 + bus_model = "PowerPC 6xx";
  5451 + break;
  5452 + case PPC_FLAGS_INPUT_BookE:
  5453 + bus_model = "PowerPC BookE";
  5454 + break;
  5455 + case PPC_FLAGS_INPUT_405:
  5456 + bus_model = "PowerPC 405";
  5457 + break;
  5458 + case PPC_FLAGS_INPUT_970:
  5459 + bus_model = "PowerPC 970";
  5460 + break;
  5461 + case PPC_FLAGS_INPUT_401:
  5462 + bus_model = "PowerPC 401/403";
  5463 + break;
  5464 + default:
  5465 + bus_model = "Unknown or invalid";
  5466 + break;
  5467 + }
  5468 + printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
  5469 + " MMU model : %s\n",
  5470 + def->name, def->pvr, def->msr_mask, mmu_model);
  5471 + if (env->tlb != NULL) {
  5472 + printf(" %d %s TLB in %d ways\n",
  5473 + env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
  5474 + env->nb_ways);
  5475 + }
  5476 + printf(" Exceptions model : %s\n"
  5477 + " Bus model : %s\n",
  5478 + excp_model, bus_model);
  5479 + }
  5480 + dump_ppc_insns(env);
  5481 + dump_ppc_sprs(env);
  5482 + fflush(stdout);
4317 5483 #endif
4318   - {
4319   - .name = "ppc32",
4320   - .pvr = CPU_PPC_604,
4321   - .pvr_mask = 0xFFFFFFFF,
4322   - .insns_flags = PPC_INSNS_PPC32,
4323   - .flags = PPC_FLAGS_PPC32,
4324   - .msr_mask = 0x000000000005FF77ULL,
4325   - },
4326   - /* Fallback */
4327   - {
4328   - .name = "ppc",
4329   - .pvr = CPU_PPC_604,
4330   - .pvr_mask = 0xFFFFFFFF,
4331   - .insns_flags = PPC_INSNS_PPC32,
4332   - .flags = PPC_FLAGS_PPC32,
4333   - .msr_mask = 0x000000000005FF77ULL,
4334   - },
4335   -};
  5484 +
  5485 + return 0;
  5486 +}
4336 5487  
4337 5488 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
4338 5489 {
... ... @@ -4374,9 +5525,8 @@ void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4374 5525 int i;
4375 5526  
4376 5527 for (i = 0; ; i++) {
4377   - (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
4378   - ppc_defs[i].name,
4379   - ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
  5528 + (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
  5529 + ppc_defs[i].name, ppc_defs[i].pvr);
4380 5530 if (strcmp(ppc_defs[i].name, "ppc") == 0)
4381 5531 break;
4382 5532 }
... ...