uint64_texit_info_1;uint64_texit_info_2;uint32_texit_int_info;uint32_texit_int_info_err;uint64_tnested_ctl;uint8_treserved_4[16];uint32_tevent_inj;uint32_tevent_inj_err;uint64_tnested_cr3;uint64_tlbr_ctl;uint8_treserved_5[832];};#defineTLB_CONTROL_DO_NOTHING0#defineTLB_CONTROL_FLUSH_ALL_ASID1#defineV_TPR_MASK0x0f#defineV_IRQ_SHIFT8#defineV_IRQ_MASK(1<<V_IRQ_SHIFT)#defineV_INTR_PRIO_SHIFT16#defineV_INTR_PRIO_MASK(0x0f<<V_INTR_PRIO_SHIFT)#defineV_IGN_TPR_SHIFT20#defineV_IGN_TPR_MASK(1<<V_IGN_TPR_SHIFT)#defineV_INTR_MASKING_SHIFT24#defineV_INTR_MASKING_MASK(1<<V_INTR_MASKING_SHIFT)#defineSVM_INTERRUPT_SHADOW_MASK1#defineSVM_IOIO_STR_SHIFT2#defineSVM_IOIO_REP_SHIFT3#defineSVM_IOIO_SIZE_SHIFT4#defineSVM_IOIO_ASIZE_SHIFT7#defineSVM_IOIO_TYPE_MASK1#defineSVM_IOIO_STR_MASK(1<<SVM_IOIO_STR_SHIFT)#defineSVM_IOIO_REP_MASK(1<<SVM_IOIO_REP_SHIFT)#defineSVM_IOIO_SIZE_MASK(7<<SVM_IOIO_SIZE_SHIFT)#defineSVM_IOIO_ASIZE_MASK(7<<SVM_IOIO_ASIZE_SHIFT)struct__attribute__((__packed__))vmcb_seg{uint16_tselector;uint16_tattrib;uint32_tlimit;uint64_tbase;};struct__attribute__((__packed__))vmcb_save_area{structvmcb_seges;structvmcb_segcs;structvmcb_segss;structvmcb_segds;structvmcb_segfs;structvmcb_seggs;structvmcb_seggdtr;structvmcb_segldtr;structvmcb_segidtr;structvmcb_segtr;uint8_treserved_1[43];uint8_tcpl;uint8_treserved_2[4];uint64_tefer;uint8_treserved_3[112];uint64_tcr4;uint64_tcr3;uint64_tcr0;uint64_tdr7;uint64_tdr6;uint64_trflags;uint64_trip;uint8_treserved_4[88];uint64_trsp;uint8_treserved_5[24];uint64_trax;uint64_tstar;uint64_tlstar;uint64_tcstar;uint64_tsfmask;uint64_tkernel_gs_base;uint64_tsysenter_cs;uint64_tsysenter_esp;uint64_tsysenter_eip;uint64_tcr2;/* qemu: cr8 added to reuse this as hsave */uint64_tcr8;uint8_treserved_6[32-8];/* originally 32 */uint64_tg_pat;uint64_tdbgctl;uint64_tbr_from;uint64_tbr_to;uint64_tlast_excp_from;uint64_tlast_excp_to;};struct__attribute__((__packed__))vmcb{structvmcb_control_areacontrol;structvmcb_save_areasave;};#defineSVM_CPUID_FEATURE_SHIFT2#defineSVM_CPUID_FUNC0x8000000a#defineMSR_EFER_SVME_MASK(1ULL<<12)#defineSVM_SELECTOR_S_SHIFT4#defineSVM_SELECTOR_DPL_SHIFT5#defineSVM_SELECTOR_P_SHIFT7#defineSVM_SELECTOR_AVL_SHIFT8#defineSVM_SELECTOR_L_SHIFT9#defineSVM_SELECTOR_DB_SHIFT10#defineSVM_SELECTOR_G_SHIFT11#defineSVM_SELECTOR_TYPE_MASK(0xf)#defineSVM_SELECTOR_S_MASK(1<<SVM_SELECTOR_S_SHIFT)#defineSVM_SELECTOR_DPL_MASK(3<<SVM_SELECTOR_DPL_SHIFT)#defineSVM_SELECTOR_P_MASK(1<<SVM_SELECTOR_P_SHIFT)#defineSVM_SELECTOR_AVL_MASK(1<<SVM_SELECTOR_AVL_SHIFT)#defineSVM_SELECTOR_L_MASK(1<<SVM_SELECTOR_L_SHIFT)#defineSVM_SELECTOR_DB_MASK(1<<SVM_SELECTOR_DB_SHIFT)#defineSVM_SELECTOR_G_MASK(1<<SVM_SELECTOR_G_SHIFT)#defineSVM_SELECTOR_WRITE_MASK(1<<1)#defineSVM_SELECTOR_READ_MASKSVM_SELECTOR_WRITE_MASK#defineSVM_SELECTOR_CODE_MASK(1<<3)#defineINTERCEPT_CR0_MASK1#defineINTERCEPT_CR3_MASK(1<<3)#defineINTERCEPT_CR4_MASK(1<<4)#defineINTERCEPT_DR0_MASK1#defineINTERCEPT_DR1_MASK(1<<1)#defineINTERCEPT_DR2_MASK(1<<2)#defineINTERCEPT_DR3_MASK(1<<3)#defineINTERCEPT_DR4_MASK(1<<4)#defineINTERCEPT_DR5_MASK(1<<5)#defineINTERCEPT_DR6_MASK(1<<6)#defineINTERCEPT_DR7_MASK(1<<7)#defineSVM_EVTINJ_VEC_MASK0xff#defineSVM_EVTINJ_TYPE_SHIFT8#defineSVM_EVTINJ_TYPE_MASK(7<<SVM_EVTINJ_TYPE_SHIFT)#defineSVM_EVTINJ_TYPE_INTR(0<<SVM_EVTINJ_TYPE_SHIFT)#defineSVM_EVTINJ_TYPE_NMI(2<<SVM_EVTINJ_TYPE_SHIFT)#defineSVM_EVTINJ_TYPE_EXEPT(3<<SVM_EVTINJ_TYPE_SHIFT)#defineSVM_EVTINJ_TYPE_SOFT(4<<SVM_EVTINJ_TYPE_SHIFT)#defineSVM_EVTINJ_VALID(1<<31)#defineSVM_EVTINJ_VALID_ERR(1<<11)#defineSVM_EXITINTINFO_VEC_MASKSVM_EVTINJ_VEC_MASK#defineSVM_EXITINTINFO_TYPE_INTRSVM_EVTINJ_TYPE_INTR#defineSVM_EXITINTINFO_TYPE_NMISVM_EVTINJ_TYPE_NMI#defineSVM_EXITINTINFO_TYPE_EXEPTSVM_EVTINJ_TYPE_EXEPT#defineSVM_EXITINTINFO_TYPE_SOFTSVM_EVTINJ_TYPE_SOFT#defineSVM_EXITINTINFO_VALIDSVM_EVTINJ_VALID#defineSVM_EXITINTINFO_VALID_ERRSVM_EVTINJ_VALID_ERR#defineSVM_EXIT_READ_CR00x000#defineSVM_EXIT_READ_CR30x003#defineSVM_EXIT_READ_CR40x004#defineSVM_EXIT_READ_CR80x008#defineSVM_EXIT_WRITE_CR00x010#defineSVM_EXIT_WRITE_CR30x013#defineSVM_EXIT_WRITE_CR40x014#defineSVM_EXIT_WRITE_CR80x018#defineSVM_EXIT_READ_DR00x020#defineSVM_EXIT_READ_DR10x021#defineSVM_EXIT_READ_DR20x022#defineSVM_EXIT_READ_DR30x023#defineSVM_EXIT_READ_DR40x024#defineSVM_EXIT_READ_DR50x025#defineSVM_EXIT_READ_DR60x026#defineSVM_EXIT_READ_DR70x027#defineSVM_EXIT_WRITE_DR00x030#defineSVM_EXIT_WRITE_DR10x031#defineSVM_EXIT_WRITE_DR20x032#defineSVM_EXIT_WRITE_DR30x033#defineSVM_EXIT_WRITE_DR40x034#defineSVM_EXIT_WRITE_DR50x035#defineSVM_EXIT_WRITE_DR60x036#defineSVM_EXIT_WRITE_DR70x037#defineSVM_EXIT_EXCP_BASE0x040#defineSVM_EXIT_INTR0x060#defineSVM_EXIT_NMI0x061#defineSVM_EXIT_SMI0x062#defineSVM_EXIT_INIT0x063#defineSVM_EXIT_VINTR0x064#defineSVM_EXIT_CR0_SEL_WRITE0x065#defineSVM_EXIT_IDTR_READ0x066#defineSVM_EXIT_GDTR_READ0x067#defineSVM_EXIT_LDTR_READ0x068#defineSVM_EXIT_TR_READ0x069#defineSVM_EXIT_IDTR_WRITE0x06a#defineSVM_EXIT_GDTR_WRITE0x06b#defineSVM_EXIT_LDTR_WRITE0x06c#defineSVM_EXIT_TR_WRITE0x06d#defineSVM_EXIT_RDTSC0x06e#defineSVM_EXIT_RDPMC0x06f#defineSVM_EXIT_PUSHF0x070#defineSVM_EXIT_POPF0x071#defineSVM_EXIT_CPUID0x072#defineSVM_EXIT_RSM0x073#defineSVM_EXIT_IRET0x074#defineSVM_EXIT_SWINT0x075#defineSVM_EXIT_INVD0x076#defineSVM_EXIT_PAUSE0x077#defineSVM_EXIT_HLT0x078#defineSVM_EXIT_INVLPG0x079#defineSVM_EXIT_INVLPGA0x07a#defineSVM_EXIT_IOIO0x07b#defineSVM_EXIT_MSR0x07c#defineSVM_EXIT_TASK_SWITCH0x07d#defineSVM_EXIT_FERR_FREEZE0x07e#defineSVM_EXIT_SHUTDOWN0x07f#defineSVM_EXIT_VMRUN0x080#defineSVM_EXIT_VMMCALL0x081#defineSVM_EXIT_VMLOAD0x082#defineSVM_EXIT_VMSAVE0x083#defineSVM_EXIT_STGI0x084#defineSVM_EXIT_CLGI0x085#defineSVM_EXIT_SKINIT0x086#defineSVM_EXIT_RDTSCP0x087#defineSVM_EXIT_ICEBP0x088#defineSVM_EXIT_WBINVD0x089/* only included in documentation, maybe wrong */#defineSVM_EXIT_MONITOR0x08a#defineSVM_EXIT_MWAIT0x08b#defineSVM_EXIT_NPF0x400#defineSVM_EXIT_ERR-1#defineSVM_CR0_SELECTIVE_MASK(1<<3|1)/* TS and MP */#defineSVM_VMLOAD".byte 0x0f, 0x01, 0xda"#defineSVM_VMRUN".byte 0x0f, 0x01, 0xd8"#defineSVM_VMSAVE".byte 0x0f, 0x01, 0xdb"#defineSVM_CLGI".byte 0x0f, 0x01, 0xdd"#defineSVM_STGI".byte 0x0f, 0x01, 0xdc"#defineSVM_INVLPGA".byte 0x0f, 0x01, 0xdf"/* function references */#defineINTERCEPTED(mask)(env->intercept&mask)#defineINTERCEPTEDw(var,mask)(env->intercept##var&mask)#defineINTERCEPTEDl(var,mask)(env->intercept##var&mask)#defineSVM_LOAD_SEG(addr,seg_index,seg)\cpu_x86_load_seg_cache(env,\R_##seg_index,\lduw_phys(addr+offsetof(structvmcb,save.seg.selector)),\ldq_phys(addr+offsetof(structvmcb,save.seg.base)),\ldl_phys(addr+offsetof(structvmcb,save.seg.limit)),\vmcb2cpu_attrib(lduw_phys(addr+offsetof(structvmcb,save.seg.attrib)),ldq_phys(addr+offsetof(structvmcb,save.seg.base)),ldl_phys(addr+offsetof(structvmcb,save.seg.limit))))#defineSVM_LOAD_SEG2(addr,seg_qemu,seg_vmcb)\env->seg_qemu.selector=lduw_phys(addr+offsetof(structvmcb,save.seg_vmcb.selector));\env->seg_qemu.base=ldq_phys(addr+offsetof(structvmcb,save.seg_vmcb.base));\env->seg_qemu.limit=ldl_phys(addr+offsetof(structvmcb,save.seg_vmcb.limit));\env->seg_qemu.flags=vmcb2cpu_attrib(lduw_phys(addr+offsetof(structvmcb,save.seg_vmcb.attrib)),env->seg_qemu.base,env->seg_qemu.limit)#defineSVM_SAVE_SEG(addr,seg_qemu,seg_vmcb)\stw_phys(addr+offsetof(structvmcb,save.seg_vmcb.selector),env->seg_qemu.selector);\stq_phys(addr+offsetof(structvmcb,save.seg_vmcb.base),env->seg_qemu.base);\stl_phys(addr+offsetof(structvmcb,save.seg_vmcb.limit),env->seg_qemu.limit);\stw_phys(addr+offsetof(structvmcb,save.seg_vmcb.attrib),cpu2vmcb_attrib(env->seg_qemu.flags))#endif